ARM11 MPCore Processor - ARM Information Center

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MPCore Distributed Interrupt Controller 10.5.8 Interrupt configuration registers, 0xC00-0xC3C Interrupt configuration registers defines the assertion condition and the software model of each interrupt. There can be up to 16 interrupt configuration registers. Figure 10-6 shows their format. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ITn + ITn + ITn + ITn 0 + 0 ITn 0 + 0 ITn + ITn + ITn + ITn + ITn + ITn + ITn + ITn + ITn + ITn + ITn 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure 10-6 Interrupt configuration registers format Table 10-3 shows the individual ITn encoding for bit 1 and bit 0 of each bit pair. Table 10-3 Interrupt line encodings for bits 1 and 0 IT bit Value Meaning IT bit [1] 0 The interrupt line is level high active. 1 The interrupt line is rising edge sensitive. IT bit [0] 0 The interrupt line uses the N-N software model. 1 The interrupt line uses the 1-N software model. All Reserved interrupts, spurious interrupts, and not present interrupts (depending on the Interrupt Controller Type Register Interrupt number field) related fields are read as zero and writes to these fields have no effect. For ID0-ID15, bit 1 of the configuration pair is always read as one, that is, rising edge sensitive. For ID0-ID15, bit 0 (software model) can be configured and applies to the interrupts sent from the writing MP11 CPU. For ID29, and ID30, the configuration pair is always read as b10, that is rising edge sensitive and 1-N software model because these IDs are allocated to timer and watchdog interrupts that are CPU-specific. For ID31, the configuration pair is a Reserved field, and is read as zero, because this ID is allocated to the legacy nIRQ pin which is always level low active whether the Interrupt Controller is active or not. 10-16 Copyright © 2005, 2006, 2008 ARM Limited. All rights reserved. ARM DDI 0360E
MPCore Distributed Interrupt Controller 10.5.9 Interrupt Line Level register The Interrupt Line Level Register reflects the actual level of signals attached to the hardware interrupt lines at MPCore top level (INT pins). The format is one bit per interrupt line. 10.5.10 Software Interrupt Register, 0xF00 The Software Interrupt Register is a write-only register that is used to trigger an interrupt (identified with its ID) to a list of MP11 CPUs. Figure 10-7 shows the Software Interrupt Register format. 31 26 25 24 23 16 15 10 9 0 SBZ CPU target list SBZ Interrupt ID Target list filter Bit Value Meaning [31:26] SBZ Figure 10-7 Software Interrupt Register format MP11 CPU target list can be different from the one defined in CPU Targets List Register for the specified interrupt ID. Table 10-4 shows the Software Interrupt Register bit assignments. Table 10-4 Software Interrupt Register bit assignments [25:24] Target list filter b00 Interrupt sent to the MP11 CPUs listed in CPU Targets List b01 CPU Targets List is ignored, interrupt is sent to all but the requesting CPU. b10 CPU Targets List is ignored, interrupt is sent to the requesting CPU only. b11 RESERVED. [23:16] CPU targets list Notpresent MP11 CPUs in the CPU target list are ignored. [15:10] SBZ - [9:0] Interrupt ID Triggering an interrupt with an ID bigger than the number of supported interrupts has no effect. ARM DDI 0360E Copyright © 2005, 2006, 2008 ARM Limited. All rights reserved. 10-17
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ARM11 MPCore Processor Revision: r1
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This document is intended only to a
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Contents ARM11 MPCore Processor Tec
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Contents 6.5 Memory Barriers ......
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Contents 16.8 VFP11 treatment of br
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List of Tables ARM11 MPCore Process
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List of Tables Table 5-2 Access Per
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List of Tables Table 17-2 VFP11 MRC
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List of Figures ARM11 MPCore Proces
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List of Figures Figure 3-39 Context
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List of Figures Figure 16-3 LS pipe
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Preface This preface introduces the
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Preface Chapter 5 Memory Management
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Preface bold monospace monospace mo
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Preface ARM Limited periodically pr
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Chapter 1 Introduction This chapter
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Introduction
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Introduction 1.3 MP11 CPU overview
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Introduction • MAC operations. Mu
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Introduction Return stack A three-e
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Introduction Because cache lookups
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Introduction 1.4 Debug and programm
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Introduction The VFP supports a wid
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Introduction Interrupt generation e
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Introduction Shutdown mode This mod
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Introduction The MBIST solution you
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Introduction By overlapping the var
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Introduction Ex1 Ex2 Ex3 Sh ALU Sat
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Introduction 1.8.1 Instruction prog
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Introduction Ex1 Ex2 Ex3 Sh 5 ALU 6
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Introduction Thumb therefore offers
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Chapter 2 Programmer’s Model This
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Programmer’s Model 2.2 Processor
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Programmer’s Model 2.4 Data types
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Programmer’s Model Bit Higher add
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Programmer’s Model 4. If an exter
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Programmer’s Model 2.8 Registers
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Programmer’s Model ARM state gene
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Programmer’s Model Thumb state ge
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Programmer’s Model 2.9 The progra
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Programmer’s Model To determine t
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Programmer’s Model • For signed
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Programmer’s Model Table 2-4 PSR
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Programmer’s Model 2.10 Exception
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Programmer’s Model Table 2-5 Exce
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Programmer’s Model 2.10.6 Fast in
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Programmer’s Model • all aborts
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Programmer’s Model 2.10.12 Breakp
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Programmer’s Model Precise Data A
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Programmer’s Model Where: Is t
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Programmer’s Model The pair of re
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Programmer’s Model 2.11.5 STREXH
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Programmer’s Model Specifies th
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Programmer’s Model • ClearByAdd
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Programmer’s Model 31 28 27 20 19
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Programmer’s Model All others val
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Control Coprocessor CP15 3.1 About
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Control Coprocessor CP15 3.2 CP15 r
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Control Coprocessor CP15 Function R
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Control Coprocessor CP15 Table 3-2
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Control Coprocessor CP15 3.4 Regist
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Control Coprocessor CP15 Bit Name F
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Control Coprocessor CP15 Figure 3-5
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Control Coprocessor CP15 31 8 7 4 3
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Control Coprocessor CP15 31 28 27 2
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Control Coprocessor CP15 Bit Name V
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Control Coprocessor CP15 Instructio
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Control Coprocessor CP15 Instructio
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Control Coprocessor CP15 • a 32 b
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Control Coprocessor CP15 The Auxili
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Control Coprocessor CP15 Note In AM
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Control Coprocessor CP15 The Transl
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Control Coprocessor CP15 3.4.15 c5,
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Control Coprocessor CP15 Writing CP
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Control Coprocessor CP15 As such, D
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Control Coprocessor CP15 31 30 29 S
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Control Coprocessor CP15 Invalidate
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Control Coprocessor CP15 Note The p
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Control Coprocessor CP15 A locking
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Control Coprocessor CP15 0 Means su
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Control Coprocessor CP15 You must n
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Control Coprocessor CP15 • detect
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Control Coprocessor CP15 There is a
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Control Coprocessor CP15 MRC p15, 0
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Control Coprocessor CP15 3.5 Summar
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Control Coprocessor CP15 3-82 Copyr
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Unaligned and Mixed-Endian Data Acc
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Memory Management Unit 5.1 About th
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Memory Management Unit 5.2 TLB orga
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Memory Management Unit 5.2.5 Cohere
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Memory Management Unit Small pages
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Memory Management Unit • No memor
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Memory Management Unit One program
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Memory Management Unit The AP bits
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Memory Management Unit Table 5-3 TE
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Memory Management Unit 5.6.3 Page t
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Memory Management Unit 5.7 Memory a
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Memory Management Unit All explicit
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Memory Management Unit ARM11 MPCore
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Memory Management Unit Ordering req
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Memory Management Unit 2. If A1 and
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Memory Management Unit 5.7.6 Backwa
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Memory Management Unit External abo
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Memory Management Unit Virtual addr
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Memory Management Unit 5.9.2 Alignm
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Memory Management Unit 5.10 Fault s
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Memory Management Unit 5.11 Hardwar
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Memory Management Unit Figure 5-4 s
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Memory Management Unit • Three ac
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Memory Management Unit Translation
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Memory Management Unit 5.12 MMU des
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Memory Management Unit 5.12.2 First
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Memory Management Unit Second-level
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Memory Management Unit Second-level
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Memory Management Unit Register CRn
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Memory Management Unit Register CRn
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Memory Management Unit 5.14 MMU and
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Program Flow Prediction 6.1 About p
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Program Flow Prediction 6.2 Branch
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Program Flow Prediction 6.2.3 Stati
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Program Flow Prediction 6.3 Return
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Program Flow Prediction 6.5 Memory
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Program Flow Prediction 6-12 Copyri
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Page 378 and 379: Debug 12.1 Debug systems The ARM11
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Debug Table 12-12 Watchpoint Contro
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Debug 12.5 CP14 debug instructions
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Debug Table 12-14 Debug instruction
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Debug 12.6.2 External debug request
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Debug Table 12-16 shows the setting
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Debug • the CP15 IFSR register is
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Debug • A DBGTAP debugger can for
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Debug SWI If this instruction is ex
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Debug 12.10 Debugging in a system w
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Debug You can program a breakpoint
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Debug • BCRa[20] enable linking b
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Debug 3. Read the word from the rDT
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Debug • Setting software breakpoi
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Debug 12-48 Copyright © 2005, 2006
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Debug Test Access Port 13.1 Debug T
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Debug Test Access Port 13.3 Enterin
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Debug Test Access Port 13.5 DBGTAP
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Debug Test Access Port 13.6 Debug r
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Debug Test Access Port section. Thi
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Debug Test Access Port Description
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Debug Test Access Port Description
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Debug Test Access Port DBGTAP debug
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Debug Test Access Port — rDTR ove
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Debug Test Access Port A typical se
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Debug Test Access Port Interpreting
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Debug Test Access Port this bit is
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Debug Test Access Port 14. The leas
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Debug Test Access Port 5. The least
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Debug Test Access Port Target to ho
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Debug Test Access Port 16. Scan_N i
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Debug Test Access Port ITRsel 1. Sc
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Debug Test Access Port 13.8.2 Gener
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Debug Test Access Port b. Transfer
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Debug Test Access Port 11. Wait unt
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Debug Test Access Port 13.8.10 Read
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Debug Test Access Port 6. Scan out
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Debug Test Access Port 4. Now check
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Debug Test Access Port 13.9.3 Setti
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Debug Test Access Port 13-50 Copyri
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Trace Interface Port 14.1 About the
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Trace Interface Port Table 14-2 ETM
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Trace Interface Port 14.1.3 Data va
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Trace Interface Port 14.1.5 Coproce
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Trace Interface Port 14-10 Copyrigh
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Cycle Timings and Interlock Behavio
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Introduction to VFP 16.1 About the
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Introduction to VFP 16.3 Coprocesso
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Introduction to VFP Decode Read por
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Introduction to VFP 4. The sum is r
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Introduction to VFP Fetch Decode Is
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Introduction to VFP 16.5 Modes of o
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Introduction to VFP • the VFP11 c
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Introduction to VFP 16.7 Parallel e
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Introduction to VFP 16.9 Writing op
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Introduction to VFP 16-20 Copyright
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VFP Register File 17.1 About the re
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VFP Register File The IEEE 754 stan
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VFP Register File 17.4 Loading oper
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VFP Register File 17.5 Maintaining
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VFP Register File For double-precis
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VFP Register File Example 17-1 Regi
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VFP Register File FMULD D13, D9, D2
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VFP Register File Table 17-10 descr
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VFP Programmer’s Model 18.1 About
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VFP Programmer’s Model To execute
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VFP Programmer’s Model Table 18-2
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VFP Programmer’s Model FMRS Rx,Sn
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VFP Programmer’s Model 18.3 ARMv5
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VFP Programmer’s Model Architectu
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VFP Programmer’s Model 31 28 27 2
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VFP Programmer’s Model 18.4 VFP11
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VFP Programmer’s Model The follow
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VFP Programmer’s Model Table 18-6
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VFP Programmer’s Model The rules
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VFP Programmer’s Model Bit Name D
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VFP Programmer’s Model • access
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VFP Programmer’s Model 18-28 Copy
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VFP Instruction Execution 19.1 Abou
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VFP Instruction Execution 19.3 Inte
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VFP Instruction Execution In Exampl
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VFP Instruction Execution 19.6 Oper
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VFP Instruction Execution FADDS S8,
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VFP Instruction Execution In RunFas
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VFP Instruction Execution FMULD D6,
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VFP Instruction Execution FADDS S1,
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VFP Instruction Execution Table 19-
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VFP Instruction Execution 19.9 Reso
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VFP Instruction Execution 19.9.3 Sh
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VFP Instruction Execution Example 1
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VFP Instruction Execution Table 19-
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VFP Exception Handling 20.1 About e
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VFP Exception Handling instruction
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VFP Exception Handling If one or mo
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VFP Exception Handling 20.4 Excepti
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VFP Exception Handling 20.4.4 Examp
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VFP Exception Handling UFC 0 OFC 0
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VFP Exception Handling 20.5 Input S
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VFP Exception Handling The VFP11 co
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VFP Exception Handling 20.7 Divisio
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VFP Exception Handling Table 20-6 R
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VFP Exception Handling When the FZ
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VFP Exception Handling 20.11 Input
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VFP Exception Handling 20.12.1 FADD
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VFP Exception Handling b. SP = sing
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VFP Exception Handling the minimum
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VFP Exception Handling 20.12.10FTOU
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VFP Exception Handling Table 20-13
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VFP Exception Handling 20-36 Copyri
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Signal Descriptions A.1 AXI interfa
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Signal Descriptions Table A-3 Maste
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Signal Descriptions Table A-7 shows
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Signal Descriptions A.2 Interrupt l
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Signal Descriptions A.4 MBIST inter
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Signal Descriptions Table A-14 Powe
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Signal Descriptions Table A-15 Misc
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Signal Descriptions A.8 ETM interfa
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Signal Descriptions A-18 Copyright
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AC Characteristics B.1 MPCore timin
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AC Characteristics System CLK or HC
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MBIST Controller and Dispatch Unit
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Scan chain ordering with RVI D.1 Sc
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Scan chain ordering with RVI D-4 Co
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IEM E.1 Purpose of IEM The purpose
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IEM E.2 About AXI register slices T
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IEM E-6 Copyright © 2005, 2006, 20
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Glossary Advanced eXtensible Interf
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Glossary ATB bridge A synchronous A
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Glossary Write interleave capabilit
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Glossary Boundary scan chain Branch
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Glossary Cache way A group of cache
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Glossary Data cache DBGTAP A block
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Glossary Enabled exception Endianne
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Glossary Fm Fn Formatter Fraction F
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Glossary Instruction cache A block
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Glossary Memory Protection Unit (MP
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Glossary Remapping Replicator Reser
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Glossary behavior of the device. It
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Glossary exception processing. The
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Glossary Write-back (WB) Write buff
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Glossary Glossary-30 Copyright © 2
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