ARM11 MPCore Processor - ARM Information Center

MPCore Distributed Interrupt Controller
10.5.8 Interrupt configuration registers, 0xC00-0xC3C
Interrupt configuration registers defines the assertion condition and the software model
of each interrupt. There can be up to 16 interrupt configuration registers. Figure 10-6
shows their format.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITn
+
ITn
+
ITn
+
ITn
0 + 0
ITn
0 + 0
ITn
+
ITn
+
ITn
+
ITn
+
ITn
+
ITn
+
ITn
+
ITn
+
ITn
+
ITn
+ ITn
15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
Figure 10-6 Interrupt configuration registers format
Table 10-3 shows the individual ITn encoding for bit 1 and bit 0 of each bit pair.
Table 10-3 Interrupt line encodings for bits 1 and 0
IT bit Value Meaning
IT bit [1] 0 The interrupt line is level high active.
1 The interrupt line is rising edge sensitive.
IT bit [0] 0 The interrupt line uses the N-N software model.
1 The interrupt line uses the 1-N software model.
All Reserved interrupts, spurious interrupts, and not present interrupts (depending on
the Interrupt Controller Type Register Interrupt number field) related fields are read as
zero and writes to these fields have no effect.
For ID0-ID15, bit 1 of the configuration pair is always read as one, that is, rising edge
sensitive.
For ID0-ID15, bit 0 (software model) can be configured and applies to the interrupts
sent from the writing MP11 CPU.
For ID29, and ID30, the configuration pair is always read as b10, that is rising edge
sensitive and 1-N software model because these IDs are allocated to timer and watchdog
interrupts that are CPU-specific.
For ID31, the configuration pair is a Reserved field, and is read as zero, because this ID
is allocated to the legacy nIRQ pin which is always level low active whether the
Interrupt Controller is active or not.
10-16 Copyright © 2005, 2006, 2008 ARM Limited. All rights reserved. ARM DDI 0360E