Journal of Applied Science Studies - Ozean Publications

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Ozean Journal of Applied Sciences 1(1), 2008 EXPERIMENTS The experiments were performed on silicon substrates with polysilicon gate patterns already etched on the surface. The wafers also had a layer of BPSG deposited on top, as shown in figure 5(a). They were then passing through the following processing steps. (1) Dehydration bake at 200 o C for 100 seconds. (2) Cooling down to 23 o C for 60 seconds. (3) HMDS priming at 80 o C for 45 seconds. (4) Spin coating with positive photoresist PFI-34A at thickness of 1.5 µm, as shown in figure 5(b). (5) Soft bake at 90 o C for 100 seconds. (6) Exposure with Nikon stepper model NSR2005i8A. Using the condition of i-line (365 nm), contact holes mask with 5 times reduction, exposure energy range of 20 – 410 mJ/cm 2 , focus length range of -0.2 to 1.0 micron. (7) Post exposure bake at 110 o C for 80 seconds. (8) Developing the photoresist for 60 seconds and then rinsing in DI water, as shown in figure 5(c). (9) Hard baking at 120 o C for 80 seconds. (10) Inspection the patterns with an optical microscope and Critical Dimension Scanning Electron Microscope (CD-SEM). RESULTS AND DISCUSSION The most suitable conditions of photolithography for contact holes fabrication should be selected, such that, after developing the photoresist, the bottom of contact hole patterns should be as close to 0.8 micron as possible with sidewall slope greater than or equal to 85 o . Table 1 shows the contact hole size variation with respect to exposure energy and focus range as measured by CD-SEM. Table 1. Contact holes size (nominally 0.8 micron) variation at different exposure energy and focus. 50
Ozean Journal of Applied Sciences 1(1), 2008 (a) (b) Figure 5. Contact hole fabrication process, (a) polysilicon gate planarization using BPSG, (b) photoresist coating, and (c) contact holes patterning by photolithography. (c) The result of exposure energy and focus range variation show that the most suitable values for patterning 0.8 micron contact holes are 305 mJ/cm 2 of exposure energy and -1.0 micron of focus range. The top of contact hole is 1.12 micron, and the bottom is 0.884 micron. This value is close to the desired value of 0.8 micron. The sidewall angle is calculated to be 85 degrees. The result of these conditions is shown in Figure 6(b). Over exposure can cause the widening of hole size as shown in Figure 6(h). As a result, too large hole size can cause electrical connection between polysilicon gate and source/drain. This is highly undesirable. After obtaining the optimum process condition for photolithography, the test wafers were processed using 305 mJ/cm 2 of exposure energy and -1.0 micron focus range. The contact holes were then patterned using the plasma etching process. The etching process was optimized such that the process will stop at the surface of silicon and polysilicon. The cross-section of contact holes were examined using Hitachi S4700 FE-SEM as shown in Figure 7. 51
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Fig. 3 Simulated threshold voltage
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Fig. 7 CMOS test chip layout design
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Wolf, S. (1995). The Submicron MOSF
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Journal of Applied Science Studies - Ozean Publications

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