Carbon Cortex-A5 Model User Guide for SoC Designer

Carbon Cortex-A5 Model 

User Guide for 

SoC Designer Plus 

Carbon Model Version 4.0.1 

For the ARM® Cortex-A5 Single Core and Cortex-A5 MPCore Processor 

Silicon Version: r0p0 

The Trusted Path to Accuracy 

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Document revised May 2013.


Contents 

Chapter 1. 

Using the Model Kit Component in SoC Designer Plus 

Cortex-A5 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 

Implemented Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2 

Hardware Features not Implemented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2 

Features Additional to the Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3 

Adding and Configuring the SoC Designer Plus Component . . . . . . . . . . . . . . . . . . . . . . . .1-3 

Carbon SoC Designer Plus Component Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3 

Adding the Carbon Model to the Component Library . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 

Adding the Component to the SoC Designer Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4 

Available Component ESL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5 

Setting Component Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7 

Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10 

Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10 

Run To Debug Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-28 

Memory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-28 

Disassembly View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-29 

Available Profiling Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-30 

Software Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-30 

Hardware Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-30 


vi 

Contents 


Preface 

vii 

Preface 

A Carbon Model component is a library developed from ARM intellectual property (IP) 

that is generated through Carbon Model Studio. The model then can be used within a 

virtual platform tool, for example, Carbon SoC Designer Plus. 

About This Guide 

This guide provides all the information needed to configure and use the Carbon Cortex-A5 

single-processor (UNI) or multi-processor (MPCore) Model in Carbon SoC Designer 

Plus. 

Audience 

This guide is intended for experienced hardware and software developers who create components 

for use with Carbon SoC Designer Plus. You should be familiar with the following 

products and technology: 

• Carbon SoC Designer Plus 

• Hardware design verification 

• Verilog or VHDL programming language 


viii 

Preface 

Conventions 

This guide uses the following conventions: 

Convention Description Example 

courier 

italic 

bold 

 

Commands, functions, 

variables, routines, and 

code examples that are set 

apart from ordinary text. 

New or unusual words or 

phrases appearing for the 

first time. 

Action that the user performs. 

Values that you fill in, or 

that the system automatically 

supplies. 

[ text ] Square brackets [ ] indicate 

optional text. 

[ text1 | text2 ] The vertical bar | indicates 

“OR,” meaning that you 

can supply text1 or text 2. 

sparseMem_t SparseMemCreate- 

New(); 

Transactors provide the entry and exit 

points for data ... 

Click Close to close the dialog. 

/ represents the name of 

various platforms. 

$CARBON_HOME/bin/modelstudio 

[ ] 

$CARBON_HOME/bin/modelstudio 

[.symtab.db | 

.ccfg ] 

Also note the following references: 

• References to C code implicitly apply to C++ as well. 

• File names ending in .cc, .cpp, or .cxx indicate a C++ source file. 


Preface 

ix 

Further reading 

This section lists related publications by Carbon and by third parties. 

Carbon SoC Designer Plus Documentation 

The following publications provide information that relate directly to SoC Designer Plus: 

• Carbon SoC Designer Plus Installation Guide 

• Carbon SoC Designer Plus User Guide 

• Carbon SoC Designer Plus Standard Model Library Reference Manual 

External publications 

The following publications provide reference information about ARM® products: 

• ARM Cortex-A5 Technical Reference Manual 

• ARM Cortex-A5 MPCore Technical Reference Manual 

• Cortex-A5 Floating-Point Unit Technical Reference Manual 

• Cortex-A5 NEON Media Processing Engine Technical Reference Manual 

• Cortex-A5 Configuration and Sign-Off Guide 

• AMBA Specification 

• AMBA AHB Transaction Level Modeling Specification 

• AMBA AXI Transaction Level Modeling Specification 

• Architecture Reference Manual 

• ARM RealView Model Debugger User Guide 

See http://infocenter.arm.com/help/index.jsp for access to ARM documentation. 

The following publications provide additional information on simulation: 

• IEEE 1666 SystemC Language Reference Manual, (IEEE Standards Association) 

• SPIRIT User Guide, Revision 1.2, SPIRIT Consortium. 


x 

Preface 

Glossary 

AMBA 

AHB 

APB 

AXI 

Carbon Model 

Carbon Model 

Studio 

CASI 

CADI 

CAPI 

Component 

ESL 

HDL 

RTL 

SoC Designer 

SystemC 

Transactor 

Advanced Microcontroller Bus Architecture. The ARM open standard on-chip 

bus specification that describes a strategy for the interconnection and management 

of functional blocks that make up a System-on-Chip (SoC). 

Advanced High-performance Bus. A bus protocol with a fixed pipeline 

between address/control and data phases. It only supports a subset of the functionality 

provided by the AMBA AXI protocol. 

Advanced Peripheral Bus. A simpler bus protocol than AXI and AHB. It is 

designed for use with ancillary or general-purpose peripherals such as timers, 

interrupt controllers, UARTs, and I/O ports. 

Advanced eXtensible Interface. A bus protocol that is targeted at high performance, 

high clock frequency system designs and includes a number of features 

that make it very suitable for high speed sub-micron interconnect. 

A software object created by the Carbon Model Studio (or Carbon compiler) 

from an RTL design. The Carbon Model contains a cycle- and register-accurate 

model of the hardware design. 

Carbon’s graphical tool for generating, validating, and executing hardwareaccurate 

software models. It creates a Carbon Model, and it also takes a Carbon 

Model as input and generates a Carbon component that can be used in 

SoC Designer Plus, Platform Architect, or OSCI SystemC for simulation. 

ESL API Simulation Interface, is based on the SystemC communication 

library and manages the interconnection of components and communication 

between components. 

ESL API Debug Interface, enables reading and writing memory and register 

values and also provides the interface to external debuggers. 

ESL API Profiling Interface, enables collecting historical data from a component 

and displaying the results in various formats. 

Building blocks used to create simulated systems. Components are connected 

together with unidirectional transaction-level or signal-level connections. 

Electronic System Level. A type of design and verification methodology that 

models the behavior of an entire system using a high-level language such as C 

or C++. 

Hardware Description Language. A language for formal description of electronic 

circuits, for example, Verilog or VHDL. 

Register Transfer Level. A high-level hardware description language (HDL) 

for defining digital circuits. 

The full name is Carbon SoC Designer Plus. A high-performance, cycle accurate 

simulation framework which is targeted at System-on-a-Chip hardware 

and software debug as well as architectural exploration. 

SystemC is a single, unified design and verification language that enables verification 

at the system level, independent of any detailed hardware and software 

implementation, as well as enabling co-verification with RTL design. 

Transaction adaptors. You add transactors to your Carbon component to connect 

your component directly to transaction level interface ports for your particular 

platform. 


Cortex-A5 Functionality 1-1 

Chapter 1 

Using the Model Kit Component in 


This chapter describes the functionality of the Model component, and how to use it in 

Carbon SoC Designer Plus. It contains the following sections: 

• Cortex-A5 Functionality 

• Adding and Configuring the SoC Designer Plus Component 

• Available Component ESL Ports 

• Setting Component Parameters 

• Debug Features 

• Available Profiling Data 

1.1 Cortex-A5 Functionality 

The Cortex-A5 processors can be used in both a uniprocessor configuration and multiprocessor 

configurations. 

In the multiprocessor configuration, up to four Cortex-A5 processors are available in a 

cache-coherent cluster, under the control of a Snoop Control Unit (SCU), that maintains 

L1 data cache coherency. 

The Cortex-A5 MPCore multiprocessor has: 

• up to four Cortex-A5 processors 

• an SCU responsible for maintaining coherency among L1 data caches 

• an Interrupt Controller (IC) with support for legacy ARM interrupts 

• a private timer and a private watchdog per processor 

• a global timer 

• AXI high-speed Advanced Microprocessor Bus Architecture (AMBA) L2 interfaces. 

• an Accelerator Coherency Port (ACP), an optional AXI 64-bit slave port that can be 

connected to a DMA engine or a non-cached peripheral. 

It is possible to implement only one Cortex-A5 processor in a Cortex-A5 MPCore processor 

design. In this configuration, an SCU is still provided. The ACP, and an additional 

master port, are also available in this configuration. 


1-2 Using the Model Kit Component in SoC Designer Plus 

This section provides a summary of the functionality of the model compared to that of the 

hardware, and the performance and accuracy of the model. 

• Implemented Hardware Features 

• Hardware Features not Implemented 

• Features Additional to the Hardware 

1.1.1 Implemented Hardware Features 

Most hardware features have been implemented. Some functionality and register pin differences 

are listed in the next section. 

Note that when using semihosting you must use the semihost component from Carbon. 

This “CarbonSemihost” component is included in the Carbon SoC Designer Plus Standard 

Model Library, version 3.0 or greater. The ARM RVML semihost component will not 

work with the Carbon Model. Additionally, only a single core is currently supported for 

semihosting. 

See the ARM Cortex-A5 MPCore Technical Reference Manual for more information. 

1.1.2 Hardware Features not Implemented 

The following features of the Cortex-A5 hardware are not implemented in the Carbonized 

model: 

• TLB Lockdown is not supported. 

• The following registers are not available to be read / written via debug transactions — 

for example, in the SoC Designer Plus Registers window, or by accessing them 

directly from RealView Debugger: 

– Cache register; ICIALLU, ICIMVAU, FPB, BPIALL, BPIMVA, DCIMVAC, 

DCISW, DCCMVAC, DCCSW, DCCMVAU, DCCIMVAC, and DCCISW 

– TLB register; not supported 

– Virtual Address to Physical Address register; V2PCWPR, V2PCWPW, 

V2PCWUR, V2PCWUW, V2POWPR, V2POWPW, V2POWUR, and V2POWUW 

The functionality of these registers, however, does exist and can be accessed by software 

running on the virtual platform. 

• Some register pins are read-only as well. See the section “Register Information” on 

page 1-10 for more information. 

• Debug transactions do not fully support cache coherence. This means that the debug 

transaction could read or write data without realizing that it is accessing data that 

resides in the other cores’ L1 cache. Debug transactions are needed by RVD accesses 

to memory, as well as by semihosting. If you see a different memory value from RVD 

than what you see by opening the Memory view in the processor and memory, then 

your design may have encountered this limitation. 


Adding and Configuring the SoC Designer Plus Component 1-3 

1.1.3 Features Additional to the Hardware 

The following features that are implemented in the Cortex-A5 model do not exist in the 

Cortex-A5 hardware. These features have been added to the model for enhanced usability. 

• The component supports positive and negative level irq and fiq signal. This is configurable 

using the negLogic parameter (see Table 1-3 on page 1-8). 

• The “run to debug point” feature has been added. This feature forces the debugger to 

advance the processor to the debug state instead of having the model get into a nondebuggable 

state. See “Run To Debug Point” on page 1-28 for more information. 

1.2 Adding and Configuring the SoC Designer Plus Component 

The following topics briefly describe how to use the component. See the Carbon SoC 

Designer Plus User Guide for more information. 

• Carbon SoC Designer Plus Component Files 

• Adding the Carbon Model to the Component Library 

• Adding the Component to the SoC Designer Canvas 

1.2.1 Carbon SoC Designer Plus Component Files 

The component files are the final output from the Carbon Model Studio compile and are 

the input to SoC Designer Plus. There are two versions of the component; an optimized 

release version for normal operation, and a debug version. 

On Linux, the debug version of the component is compiled without optimizations and 

includes debug symbols for use with gdb. The release version is compiled without debug 

information and is optimized for performance. 

On Windows, the debug version of the component is compiled referencing the debug runtime 

libraries so it can be linked with the debug version of SoC Designer Plus. The release 

version is compiled referencing the release runtime library. Both release and debug versions 

generate debug symbols for use with the Visual C++ debugger on Windows. 

The provided component files are listed below: 

Table 1-1 Carbon SoC Designer Plus Component Files 

Platform File Description 

Linux 

Windows 

maxlib.lib.conf 

lib.mx.so 

lib.mx_DBG.so 

maxlib.lib.windows.conf 

lib.mx.dll 

lib.mx_DBG.dll 

SoC Designer Plus configuration file 

SoC Designer Plus component runtime file 

SoC Designer Plus component debug file 

SoC Designer Plus configuration file 

SoC Designer Plus component runtime file 

SoC Designer Plus component debug file 

Additionally, this User Guide PDF file and a ReadMe text file are provided with the component. 



1.2.2 Adding the Carbon Model to the Component Library 

The compiled Carbon Model component is provided as a configuration file (.conf). To 

make the component available in the Component Window in SoC Designer Canvas, perform 

the following steps: 

1. Launch SoC Designer Canvas. 

2. From the File menu, select Preferences. 

3. Click on Component Library in the list on the left. 

4. Under the Additional Component Configuration Files window, click Add. 

5. Browse to the location where the SoC Designer Plus model is located and select the 

component configuration file: 

– maxlib.lib.conf (for Linux) 

– maxlib.lib.windows.conf (for Windows) 

6. Click OK. 

7. To save the preferences permanently, click the OK & Save button. 

The component is now available from the SoC Designer Plus Component Window. 

1.2.3 Adding the Component to the SoC Designer Canvas 

Locate the component in the Component Window and drag it out to the Canvas. It will 

appear as shown in Figure 1-1. 

Uniprocessor 

Multi-processor 

Figure 1-1 Cortex-A5 MPCore and Uniprocessor Components in 



Available Component ESL Ports 1-5 

The figure shows the component with 2 Master AXI ports. The second master port appears 

only if was defined in the model RTL configuration file, e.g., CORTEXA5MP.conf. 

1.3 Available Component ESL Ports 

Table 1-2 describes the ESL ports that are exposed in SoC Designer Plus. Some ports may 

or may not appear depending on whether you are using the multi-processor or uniprocessor 

version of the ARM hardware. See the ARM Cortex-A5 Technical Reference Manual or 

ARM Cortex-A5 MPCore Technical Reference Manual for more information. 

Table 1-2 ESL Component Ports 

ESL Port Description Direction Type 

ACLKENM0 

ACLKENM1 

ACLKEN 

Master Port 0 Clock enable for a MP component: 

Default Value is 1 

Master Port 1 Clock enable for a MP component. Must be 

configured as part of the component 


Master Port 0 Clock enable for a UP component 


ACLKENS ACP AXI Bus clock enable. By default it is set to 1 

through a component parameter. If another component is 

connected through this port, it will override the default 

value. (Available only with the MPCore) 

CFGSDISABLE 

CP15SDISABLE 

EVENTI 

INT 

fiq 1 

irq 1 

Disables write access to some system control processor 

registers. See the MPCore TRM, page 4-12. 

Disabled write access to some system control processor 

registers. 

Event input for Cortex-A5 processor wake-up from WFE 

state. 

This port connects to external interrupt signals. It can be 

any size between 0 and 224, in increments of 32. The 

value must indicate the interrupt number [NumIRQ..0] 

and the *extValue must indicate whether the IRQ line is 

asserted (*extValue=1) or deasserted (*extValue=0). 

Cortex-A5 processor private FIQ request input lines. Size 

will be 1 for a UP and 4 for a MP. For each line the values 

may be: 

0 = do not activate fast interrupt 

1 = activate fast interrupt 

Cortex-A5 processor legacy IRQ request input lines. Size 

will be 1 for a UP and 4 for a MP. For each line the values 

may be: 

0 = do not activate interrupt 

1 = activate interrupt 

Input 

Input 

Input 

Input 

Input 

Input 

Input 

Input 

Input 

Input 

Signal Slave 

Signal Slave 

Signal Slave 

Signal slave 

Signal slave 

Signal slave 

Signal slave 

Signal slave 

Signal slave 

Signal slave 

apb_dbg APB debug interface Input APB Transaction 

slave 



acp 

Table 1-2 ESL Component Ports (Continued) 

ESL Port Description Direction Type 

AXI ACP (Accelerator Coherency Port) Slave port. 

(Available only when it has been enabled in the configuration 

file.) 

Input 

AXI Transaction 

slave 

clk_in Input clock. Input Clock slave 

EVENTO 

Event output. This signal is active when one SEV instruction 

Output Signal master 

is executed. 

SMPnAMP Signals AMP or SMP mode for each Cortex-A5 MPCore Output Signal master 

processor. 

PCLKENDBG apb_dbg Bus Clock Enable Input Signal Slave 

STANDBYWFE Indicates if a Cortex-A5 processor is in WFE state. Output Signal master 

STANBYWFI Indicates that a Cortex-A5 processor is in Standby mode. Output Signal master 

nCPURESET CPU Reset Input Signal Slave 

nDBGRESET Debug Reset Input Signal Slave 

nWDRESET Watch Reset Input Signal Slave 

nPEROPHRESET Peripharl Reset Input Signal Slave 

nSCURESET SCU Reset Input Signal Slave 

axi_m0 AXI Master port 0. Output AXI Transaction 

master 

axi_m1 

AXI Master port 1 (Available only when a second master 

has been defined in the configuration file). 

Output AXI Transaction 

master 

extSemi There is an extSemi port per core in a multi-core A5, 

where is 0-3 to represent the core. In the single-processor 

version, this port is simply extSemi0. Semihosting 

can be enabled by connecting these ports to the SoC 

Designer Plus semihost component contained in the Carbon 

SoC Designer Plus Standard Model Library (v3.0 or 

greater). 

Output 

Transaction 

master 

1. For these interrupt ports, the active high/low setting is controlled by the negLogic component parameter. 

The default is active high. 

All pins that are not listed in this table have been either tied or disconnected for performance 

reasons. 

Note: 

Some ESL component port values can be set using a component parameter. This 

includes the CFGEND and CLUSTERID ports. In those cases, the parameter 

value will be used whenever the ESL port is not connected. If the port is connected, 

the connection value takes precedence over the parameter value. 


Setting Component Parameters 1-7 

1.4 Setting Component Parameters 

You can change the settings of all the component parameters in SoC Designer Canvas, and 

of some of the parameters in SoC Designer Simulator. To modify the Carbon component’s 

parameters: 

1. In the Canvas, right-click on the Carbon component and select Edit Parameters.... 

You can also double-click the component. The Edit Parameters dialog box appears. 

Figure 1-2 Component Parameters Dialog Box 

The list of available parameters will be slightly different depending on the settings that 

you enabled in the configuration file (for example, CORTEXA5MP.conf) and depending 

on whether you are using the multi-processor or uniprocessor version of the ARM 

hardware. 

2. In the Parameters window, double-click the Value field of the parameter that you 

want to modify. 

3. If it is a text field, type a new value in the Value field. If a menu choice is offered, 

select the desired option. The parameters are described in Table 1-3. 



Table 1-3 Component Parameters 

Name 

Description 

Allowed 

Values 

Default Value Runtime 1 

ACLKENM0 MP Master Port 0 Bus clock enable. integer 1 Yes 

ACLKENM1 MP Master Port 1 Bus clock enable. integer 1 Yes 

ACLKEN UP Master Port Bus clock enable. integer 1 Yes 

ACLKENS ACP AXI Bus clock enable. integer 1 Yes 

Align Waveforms When set to true, waveforms dumped 

by the Carbon component are aligned 

with the SoC Designer Plus simulation 

time. The reset sequence, however, 

is not included in the dumped 

data. 

When set to false, the reset sequence 

is dumped to the waveform data, however, 

the Carbon component time is 

not aligned with SoC Designer Plus 

time. 

true, false true No 

apb_dbg Base Address Base address 0x0 – 

0xffffffff 

apb_dbg Enable Debug 

Messages 

Whether debug messages are logged 

for the APB port. 

apb_dbg Size Size 0x0 – 

0x100000000 

axi_m0 Enable Debug 

Messages 

axi_m1 Enable Debug 

Messages 

axi_s axi_size0 

axi_s axi_size[1-5] 

axi_s axi_start[0-5] 

axi_s Enable Debug 

Messages 

Carbon DB Path 


for master port 0. 


for master port 1. 

These parameters are obsolete and 

should be left at their default values. 2 


for the slave port. 

Sets the directory path to the Carbon 

database file. 

0x0 

No 

true, false false Yes 

0x100000000 

No 



0x100000000 

0x0 

0x00000000 

0x100000000 

0x0 

0x00000000 

No 


Not Used empty No 

CFGEND Endianness configuration. true, false false Yes 

CLUSTERID 

Value read in Cluster ID register field, 0-15 0 Yes 

bits[11:8] of the MPIDR. 

DataCacheSize 

For UP only, sets the Data Cache 

Size. 

04K, 08K, 

16K,32K, 

64K 

64K 

No 


Setting Component Parameters 1-9 

Table 1-3 Component Parameters (Continued) 

Name 

Description 

Allowed 

Values 

Default Value Runtime 1 

DataCache- 

SizeCPUXXX 

Dump Waveforms 

Enable Debug 

Messages 

InstrCacheSize 

InstrCache- 

SizeCPUXXX 

negLogic 

PERIPHBASE 

Secure Non-Invasive 

Debug Enable 

VINITHI 

For MP only, sets the Data Cache 

Size. XXX may be CPU0, CPU1, 

CPU2, CPU3 

Whether SoC Designer Plus dumps 

waveforms for this component. 


for the component. 

For UP only, sets the Instruction 

Cache Size. 

Sets the Instruction Cache Size. XXX 

may be CPU0, CPU1, CPU2, CPU3 

Sets IRQ/FIQ assertion to use negative 

logic. Default of false means 

0=off and 1=on. True means 0=on and 

1=off. 

32-bit parameter; the bottom 13 bits 

must be 0. Specifies the base address 

for Timers, Watchdogs, Interrupt 

Controller, and SCU registers. 

Enables non-invasive debug, including 

PC tracing and hardware profiling 

(see “Available Profiling Data” on 

page 1-30). 

Individual processor control of the 

location of the exception vectors at 

reset. 

04K, 08K, 

16K,32K, 

64K 

64K 

No 



04K, 08K, 

16K,32K, 

64K 

04K, 08K, 

16K,32K, 

64K 

64K 

64K 

No 

No 


any 318767104 

(0x13000000) 

Yes 

0 - 0xF 0xF No 

0, 1 0x0 Yes 

Waveform File 3 Name of the waveform file. string carbon_CORTEX 

A5.vcd or 

carbon_CORTEX 

A5MP.vcd 

Waveform Timescale 

Sets the timescale to be used in the 

waveform. 

Many values 

in drop-down 

No 

1 ns No 

1. Yes means the parameter can be dynamically changed during simulation, No means it can be changed only 

when building the system, Reset means it can be changed during simulation, but its new value will be taken 

into account only at the next reset. 

2. Carbon recommends using the Memory Map Editor (MME) in SoC Designer Plus, which provides centralized 

viewing and management of the memory regions available to the components in a system. For information 

about migrating existing systems to use the MME, refer to Chapter 9 of the SoC Designer Plus User Guide. 

3. When enabled, SoC Designer Plus writes accumulated waveforms to the waveform file in the following situations: 

when the waveform buffer fills, when validation is paused and when validation finishes, and at the end 

of each validation run. 



1.5 Debug Features 

The Cortex-A5 model has a debug interface (CADI) that allows the user to view, manipulate, 

and control the registers and memory. A view can be accessed in SoC Designer Plus 

by right clicking on the model and choosing the appropriate menu entry. 

The following topics are discussed in this section: 

• Register Information 

• Run To Debug Point 

• Memory Information 

• Disassembly View 

Note: 

The Cortex-A5 can have up to two slave ports. The apb_dbg port is used for Core- 

Sight debug, and the acp port is for ACP, which is used to connect to a DMA 

engine. These are supported as simulation interfaces, but they are not supported 

as debug interfaces. This means if a CADI operation is performed on one of these 

interfaces, it will not return data. 

1.5.1 Register Information 

Figure 1-3 shows the Register view of the Cortex-A5 model in SoC Designer Simulator. 

Figure 1-3 Cortex-A5 Registers View 

The Cortex-A5 model has many sets of registers that are accessible via the debug interface. 

Registers are grouped into sets according to functional area. 

• Core Registers 

• Debug Registers 

• ID Registers 

• VA to PA Registers 

• Pseudo Registers 


Debug Features 1-11 

1.5.1.1 Core Registers 

• Normal World Registers 

• Secure World Registers 

• Control Registers 

• Perf Registers 

• SCU Registers 

• Global Timer Registers 

• Timer/Watchdog Registers 

• Processor Interface (GIC_Core) Registers 

• Interrupt Distributor (GIC_Dist) Registers 

• VFP/Neon Registers 

See the ARM Cortex-A5 MPCore Technical Reference Manual for detailed descriptions of 

these registers. 

The Core group contains the ARM architectural registers. 

Table 1-4 Core Registers 

Name Description Type 

R0 R0 register read-write 1 













R13 SP register read-write 1 

R14 LR register read-write 1 

R15 PC register read-write 

R8_USR R8 USR register read-write 1 




Table 1-4 Core Registers (Continued) 





R13_USR SP USR register read-write 1 

R14_USR LR USR register read-write 1 

SPSR_usr Saved Program status register in USR mode read-write 

SPSR Current Program status register in USR mode read-write 

CPSR Current Program Status Register register read-only 

R13_irq SP IRQ register read-write 1 

R14_irq LR IRQ register read-write 1 

SPSR_irq Saved Program Status Register IRQ register read-only 

R13_svc SP SVC register read-write 1 

R14_svc LR SVC register read-write 1 

SPSR_svc Saved Program Status Register SVC register read-only 

R13_abt SP ABT register read-write 1 

R14_abt LR ABT register read-write 1 

SPSR_abt Saved Program Status Register ABT register read-only 

R13_UND SP UND register read-write 1 

R14_UND LR UND register read-write 1 

SPSR_UND Saved Program Status Register UND register read-only 

R8_fiq R8 FIQ register read-write 1 





R13_fiq SP FIQ register read-write 1 

R14_fiq LR FIQ register read-write 1 

SPSR_fiq Saved Program Status Register FIQ register read-only 

R13_mon SP MON register read-write 1 

R14_mon LR MON register read-write 1 

SPSR_mon Saved Program Status Register MON register read-only 

ExtendedTargetFeatures Used internally for TrustZone support read-only 

CCSIDR Cache Size ID register read-only 



Table 1-4 Core Registers (Continued) 


CLIDR Cache Level ID register read-only 

AIDR Auxiliary ID register read-only 

CSSELR Cache Size Selection register read-only 

1. Writeable at debug point only. 

1.5.1.2 Debug Registers 

The Debug group provides access to the current debug state. 

Table 1-5 Debug Registers 


CP14_DSCR Debug Status and Control register read-write 

DBGDIDR Debug ID register read-only 

DBGDRAR Debug ROM Address register read-only 

DBGDSAR Debug Self Address Offset register read-only 

DBGPCSR Program Counter Sampling register read-only 

DBGDRCR Debug Run Control register write-only 

DBGBVR0 Breakpoint Value register 0 read-write 



DBGBCR0 Breakpoint Control register 0 read-write 



DBGWVR0 Watchpoint Value register 0 read-write 

DBGWVR1 Watchpoint Value register 1 read-write 

DBGWCR0 Watchpoint Control register 0 read-only 

DBGWCR1 Watchpoint Control register 1 read-only 

DBGPRCR Device Powerdown and Rest Control register read-only 

DBGPRSR Device Powerdown and Rest Status register read-only 



1.5.1.3 ID Registers 

The ID group contains registers that describe the processor capabilities. 

Table 1-6 ID Registers 


MIDR Main ID register read-only 

CTR Cache Type register read-only 

TCMTR TCM Type register read-only 

TLBTR TLB Type register read-only 

MPIDR 

Multiprocessor Affinity register. Only valid with 

the Cortex-A5 MPCore. 

read-only 

ID_PFR0 Processor Feature 0 register read-only 

ID_PFR1 Processor Feature 1 register read-only 

ID_DFR0 Debug Feature 0 register read-only 

ID_AFR0 Auxiliary Feature 0 register read-only 

ID_MMFR0 Memory Model Feature 0 register read-only 




ID_ISAR0 ID_ISAR0 register read-only 





ID_ISAR5 ID_ISAR5 register (always returns 0) read-only 



1.5.1.4 VA to PA Registers 

The VA to PA group contains registers to perform virtual to physical address translations. 

Table 1-7 VA to PA Registers 


PAR Physical address register read-write 



1.5.1.5 Pseudo Registers 

The PSEUDO group contains registers to mirror functionality contained with ARM’s Fast 

Model version of the CortexA5. 

Table 1-8 VA to PA Registers 


PC_MEMSPACE Used internally for Fast Model mirroring read-only 

1.5.1.6 Normal World Registers 

The Normal World group contains control register that are only accessible in non-secure 

mode. 

Table 1-9 Normal World Registers 


N_CSSELR Cache Size Selection register read-only 

N_SCTLR [N] System Control register read-write 

N_ACTLR [N] Auxiliary Control register read-write 

N_TTBR0 [N] TTBR0 register read-write 

N_TTBR1 [N] TTBR1 register read-write 

N_TTBCR [N] TTBCR register read-write 

N_DACR [N] Domain Access Control register read-write 

N_DFSR [N] Data Fault Status register read-write 

N_IFSR [N] Instruction Fault Status register read-write 

N_ADFSR [N] Auxiliary Data Fault Status register read-only 

N_AIFSR [N] Auxiliary Data Fault Status register read-only 

N_DFAR [N] Data Fault Address register read-write 

N_IFAR [N] Instruction Fault Address register read-write 

N_PRRR [N] Primary Region Remap register read-write 

N_NMRR [N] Normal Memory Remap register read-write 

N_VBAR [N] Vector Base Address register read-write 

N_FCSEIDR Fast Context Switch Extenison register read-write 

N_CONTEXTIDR [N] Context ID register read-write 

N_TPIDRURW [N] User Read/Write Thread ID register read-write 

N_TPIDRURO [N] User Read Only Thread ID register read-write 

N_TPIDRPRW [N] Privileged Only Thread ID register read-write 

N_PAR Physical Address register read-write 



1.5.1.7 Secure World Registers 

The Secure group contains control registers that are only accessible in secure mode. 

Table 1-10 Secure World Registers 


S_CSSELR Cache Size Selection register read-only 

S_SCTLR [S] System Control register read-write 

S_ACTLR Auxiliary Control register read-write 

SCR Secure register read-write 

SDER Secure Debug Enable register read-write 

S_TTBR0 [S] TTBR0 register read-write 

S_TTBR1 [S] TTBR1 register read-write 

S_TTBCR [S] TTBCR register read-write 

S_DACR [S] Domain Access Control register read-write 

S_DFSR [S] Data Fault Status register read-write 

S_IFSR [S] Instruction Fault Status register read-write 

S_ADFSR [S] Auxiliary Data Fault Status register read-only 

S_AIFSR [S] Auxiliary Instruction Fault Status register read-only 

S_DFAR [S] Data Fault Address register read-write 

S_IFAR [S] Instruction Fault Address register read-write 

S_PRRR [S] Primary Region Remap register read-write 

S_NMRR [S] Normal Memory Remap register read-write 

S_VBAR [S] Vector Base Address register read-write 

MVBAR Monitor Vector Base Address register read-write 

S_FCSEIFR Fast Context Switch register read-write 

S_CONTEXTIDR [S] Context ID register read-write 

S_TPIDRURW [S] User Read/Write Thread ID register read-write 

S_TPIDRURO [S] User Read Only Thread ID register read-write 

S_TPIDRPRW [S] Privileged Only Thread ID register read-write 

S_PAR Physical Address register read-write 



1.5.1.8 Control Registers 

The Control group contains registers that dynamically configure the processor. 

Table 1-11 Control Registers 


SCTLR System Control register read-write 

ACTLR 

Auxiliary Control register. Only valid with the read-only 

Cortex-A5 MPCore. 

CPACR 

Coprocessor Access Control register. Only available 

if Neon and FPU processors are present. 

read-only 

NSACR Nonsecure Access Control register read-only 

VCR Virtualization Control register read-write 

TTBR0 TTBR0 register read-write 

TTBR1 TTBR1 register read-write 

TTBCR TTBCR register read-write 

DACR Domain Access Control register read-write 

DFSR Data Fault Status register read-write 

IFSR Instruction Fault Status register read-write 

ADFSR Auxiliary Data Fault Status register read-only 

AIFSR Auxiliary Instruction Fault Status register read-only 

DFAR Data Fault Address register read-write 

IFAR Instruction Fault Address register read-write 

PRRR Primary Region Remap register read-write 

NMRR Normal Memory Remap register read-write 

VBAR Vector Base Address register read-write 

ISR Interrupt Status register read-only 

VIR Virtualization Interrupt register read-only 

FCSEIDR Fast Context Switch Extension read-write 

CONTEXTIDR Context ID register read-write 

TPIDRURW User Read/Write Thread ID register read-write 

TPIDRURO User Read Only Thread ID register read-write 

TPIDRPRW Privileged Only Thread ID register read-write 

CBAR Configuration Base Address register read-write 1 

1. read-write in Secure privileged mode. read-only in Non-secure state and in user mode. 



1.5.1.9 Perf Registers 

The Perf group contains performance related registers. 

Table 1-12 Perf Registers 


PMCR Performance Monitor Control register read-write 

PMCNTENSET Count Enable Set register read-write 

PMCNTENCLR Count Enable Clear register read-write 

PMOVSR Overflow Flag Status register read-write 

PMSWINC Event Counter Selection register write-only 

PMSELR Event Counter Selection register read-write 

PMCEID0 Common Event Identification register 0 read-only 

PMCEID1 Common Event Identification register 1 read-only 

PMCCNTR Cycle Count register read-write 

PMXEVTYPER Event Selection register read-write 

PMCCFILTR 

read-write 

PMXEVCNTR Performance Count register read-write 

PMUSERENR User Enable register read-write 

PMINTENSET Interrupt Enable Set register read-write 

PMINTENCLR Interrupt Enable Clear register read-write 

1.5.1.10 SCU Registers 

The SCU group contains registers that control the Snoop Control Unit. Addresses are relative 

to the base address of the region for the SCU memory map. 

Table 1-13 SCU Registers 


SCU_CTRL SCU Control register read-write 

SCU_CONFIG SCU Configuration register read-only 

SCU_CPU_POW_ST SCU CPU Power Status register read-write 

SCU_FILT_START Filtering Start Address register read-write 

SCU_FILT_END Filtering End Address register read-write 

SCU_SAC SCU Access Control register read-write 

SCU_SSAC SCU Secure Access Control register read-write 



1.5.1.11 Global Timer Registers 

The Global Timer group contains and status registers related to the global timer.. 

Table 1-14 Global Timer Registers 


GT_TIMER_LO Lower 32-bit Timer Counter register read-write 

GT_TIMER_HI Upper 32-bit Timer Counter register read-write 

GT_TCR Timer Control register read-write 

GT_TSR Timer Comparator Status register read-write 

GT_COMP_LO Lower 32-bit Comparator register read-write 

GT_COMP_HI Upper 32-bit Comparator register read-write 

GT_AUTOINC Auto-Increment register for Comparator read-write 

1.5.1.12 Timer/Watchdog Registers 

The Timer/Watchdog group contains registers for controlling the timer and watchdog 

blocks for each CPU. Addresses are relative to the base address of the timer and watchdog 

region defined by the private memory map (see the ARM Cortex-A5 Technical Reference 

Manual for more information). 

Table 1-15 Timer/Watchdog Registers 


TWD_T_LOAD Timer Load register read-write 

TWD_T_CNT Timer Counter register read-write 

TWD_T_CTRL Timer Control register read-write 

TWD_T_IS Timer Interrupt Status register read-write 

TWD_WD_LOAD Watchdog Load register read-write 

TWD_WD_CNTr Watchdog Counter register read-write 

TWD_WD_CTRL Watchdog Control register read-write 

TWD_WD_IS Watchdog Interrupt Status register read-write 

TWD_WD_RST Watchdog Reset Status register read-write 



1.5.1.13 Processor Interface (GIC_Core) Registers 

The Int IF group contains the registers that each Cortex-A5 processor interface provides. 

Table 1-16 Int IF Registers 


GIC_C_CTRL_S Processor Interface Control Secure register read-write 

GIC_C_CTRL_N Processor Interface Control Non-secure register read-write 

GIC_C_PRIO_MASK Priority Mask register read-write 

GIC_C_BIN_PT_S Binary Point Secure register read-write 

GIC_C_BIN_PT_N Binary Point Non-secure register read-write 

GIC_C_INT_ACK Interrupt Acknowledge register read-only 

GIC_C_RUN_PRIO Running Priority register read-only 

GIC_C_HI_PEND Highest Pending Interrupt register read-only 

GIC_C_A_BIN_PT_N Aliased Non-secure Binary Point register read-write 

GIC_C_CPU_INDENT Processor Interface Implementer Identification register read-only 

1.5.1.14 Interrupt Distributor (GIC_Dist) Registers 

The Int Dist group describes the registers that the distributor provides. 

Table 1-17 Int Dist Registers 


GID_D_EN Distributor Enable register read-write 

GIC_D_INT_CTRL_TP Interrupt Controller Type read-only 

GIC_DIMPL_ID Distributor Implementation register read-only 

GIC_D_INT_SEU_0_31 Interrupt Security. Range defined in register name read-write 






GIC_D_INT_SEU_192-223 Interrupt Security. Range defined in register name read-write 

GIC_D_INT_SEU_224-255 Interrupt Security. Range defined in register name read-write 

GIC_D_EN_SET_0_31 Enable Set register. Range defined in register name read-write 


GIC_D_EN_SET_64-95 Enable Set register. Range defined in register name read-write 




Table 1-17 Int Dist Registers (Continued) 



GIC_D_EN_SET_160-191 Enable Set register. Range defined in register name read-write 



GIC_D_EN_CLR_0_31 Enable Clear register. Range defined in register name read-write 





GIC_D_EN_CLR_160-191 Enable Clear register. Range defined in register name read-write 



GIC_D_PEND_SET_0_31 Pending Set register. read-write 

GIC_D_PRI_LEV_STI_0_3 Priority Level STI. Range defined in register name read-write 




GIC_D_PRI_LEV_PPI_0_3 Priority Level PPI. Range defined in register name read-write 

GIC_D_PRI_LEV_PPI_4 Priority Level PPI. Range defined in register name read-write 

































































GIC_D_SPI_TARGET_0_3 SPI Target. Range defined in register name read-write 








































































GIC_D_INT_CONF_0_15 Interrupt Config. Range defined in register name read-write 
















GIC_D_PPI_ST PPI Status register read-only 

GIC_D_SPI_ST_0_31 SPI Status register. Range defined in register name read-write 








GIC_D_PERH_ID_0 Peripheral ID 1 read-only 












GID_D_PRIM_ID_0 Primecell ID 0 read-only 




1.5.1.15 VFP/Neon Registers 

The VFP/Neon group contains the floating point related registers. These are only present 

if the A5 was configured with an FPU or Neon coprocessor. 

Table 1-18 VFP/Neon Registers 


FPSID Floating-point System ID Register. read-only 

MVFR0 Media and VFP Feature Register0. read-only 

MVFR1 Media and VFP Feature Register1. read-only 

FPEXC Floating-point Exception Register. read-write 

FPSCR Floating-point Status and Control Register. read-write 

FPINST Floating-point instruction. read-only 

FPINST2 Floating-point instruction. read-only 

S0-S31 

Advanced SIMD and VFP extension registers 

(Single word). 

read-write 

S32-S63 

D0-D15 

D16-D31 

Additional SIMD and VFP extension registers. 

Only present with Neon. 


(Double word). 

Additional SIMD and VFP extension registers 

(Double word). Only present with Neon. 

read-write 

read-write 

read-write 



Table 1-18 VFP/Neon Registers (Continued) 


Q0-Q7 

Q8-Q15 


(Quad word). 

Additional SIMD and VFP extension registers 

(Quad word). Only present with Neon. 

read-write 

read-write 



1.5.2 Run To Debug Point 

The “run to debug point” feature has been added to enhance model debugging. The Cortex-A5 

processor is a dual issue out of order completion machine. This means that while 

the processor is running it does not present a coherent programmer’s view state; instructions 

in the pipeline may be in different execution states. 

This feature forces the processor into a coherent state called “run to debug point”. When 

debugging with the ARM RealView Development Suite (RVDS), the model is brought to 

the debug point automatically whenever a software breakpoint is hit (including single 

stepping). However, if a hardware breakpoint is reached, or the system is advanced by 

cycles within SoC Designer Plus, the model can get to a non-debuggable state. In this 

event, the run to debug point will advance the processor to the debug state. It does this by 

stalling the instruction within the decode stage and allowing all earlier instructions to complete. 

Once that has been accomplished, the model will cause the system to stop simulating. 

The run to debug point is available as a context menu item (Run to Debuggable Point) for 

the component within SoC Designer Simulator. It is also available in the disassembler 

view. 

1.5.3 Memory Information 

Figure 1-4 shows a Memory view of Cortex-A5 model. 

Figure 1-4 Cortex-A5 Memory View 



1.5.4 Disassembly View 

Figure 1-5 shows the disassembly view of a program running on the Cortex-A5 model in 

SoC Designer Simulator. To display the disassembly view in the SoC Designer Simulator, 

right-click on the Cortex-A5 model and select View Disassembly… from the context 

menu. 

Figure 1-5 Cortex-A5 Disassembly Window 

All CADI windows support breakpoints – when double-clicking on the proper location a 

red dot will indicate that a breakpoint is currently active. To remove the breakpoints simply 

double-click on the same location again. 



1.6 Available Profiling Data 

Profiling data is enabled, and can be viewed using the Profiling Manager, which is accessible 

via the Debug menu in the SoC Designer Simulator. Both hardware and software 

based profiling are available. 

1.6.1 Software Profiling 

Software-based profiling is provided by SoC Designer Plus. Profiling information is also 

available in the SoC Designer Plus Profiler. See the user guide for SoC Designer Plus or 

SoC Designer Plus Profiler for more information. 

1.6.2 Hardware Profiling 

Hardware profiling is broken down into five streams per processor core. They are the 

I-Cache, D-Cache, TLB, Stall, and Software streams. The buckets supported by each of 

these streams are shown in Table 1-19: 

Table 1-19 Cortex-A5 Profiling Events 

Stream Buckets X axis Y axis 

I-Cache Read Miss Cycle Instruction Cache 

Read Hit 

Prefetch Fill 

Prefetch Fill Dropped 

D-Cache Read Miss Cycle Data Cache 

Access 

Read 

Write 

Evication 

Memory Access 

External Memory Request 

Non-cacheable memory request 

Entering Read Allocate Mode 

Read Allocate Mode 

Date Write Stall 

TLB ITLB Miss Cycle TLB 

DTLB Miss 


Available Profiling Data 1-31 

Table 1-19 Cortex-A5 Profiling Events (Continued) 

Stream Buckets X axis Y axis 

Software Instructions Executed Cycle Software 

Exceptions Taken 

Exceptions Returned 

ContextID Retired Changed 

Software Change of PC 

Immediate Branch 

Function Return 

Unaligned Access 

Mispredicated Branch 

Branch 

IRQ Exception Taken 

FIQ Exception Taken 

The Cortex-A5 model sets PMCR[4] to 1 to enable the Hardware Profiling. This is done at 

reset time. 

The Cortex-A5 pin SPNIDEN must be set to one (1) to enable Hardware Profiling information. 

This is set using the component parameter Secure Non-Invasive Debug Enable 

(see Table 1-3 on page 1-8). The default value is 0xF, which enables non-invasive debug 

on up to four cores. 

An example of debug information for a software stream is shown below. 

Figure 1-6 Software Stream Debug Information 




Third Party Software Acknowledgement 

Carbon acknowledges and thanks the respective owners for the following software that is 

used by our product: 

• ELF (Executable and Linking Format) Tool Chain Product 

Copyright (c) 2006, 2008-2012 Joseph Koshy 

All rights reserved. 

Redistribution and use in source and binary forms, with or without modification, are permitted 

provided that the following conditions are met: 

1. Redistributions of source code must retain the above copyright notice, this list of conditions 

and the following disclaimer. 

2. Redistributions in binary form must reproduce the above copyright notice, this list of 

conditions and the following disclaimer in the documentation and/or other materials 

provided with the distribution. 

THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS “AS IS'' 

AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIM- 

ITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 

FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 

AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCI- 

DENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUD- 

ING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 

SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 

HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CON- 

TRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHER- 

WISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 

ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Carbon Cortex-A5 Model User Guide for SoC Designer

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