Carbon NIC-301 Model User Guide for SoC Designer

Carbon NIC-301 ModelUser Guide for SoC DesignerCarbon Model Version 4.1.0For the ARM AMBA® Network Interconnect (NIC-301)Silicon Version: r2p0, r2p1, r2p2, r2p3The Trusted Path to Accuracy The information contained in this document is confidential information of Carbon Design Systems, Inc.,and may not be duplicated or disclosed to unauthorized and/or third parties.

CopyrightCopyright © 2003-2013 Carbon Design Systems, Inc. All rights reserved.Files, documents or portions thereof presented on the Carbon Design Systems Internet server “Publication”, permits personsto view, copy, and print the Publication subject to the following conditions:• The Publication are to be kept strictly confidential• Copies of the Publication will not be distributed• Copies of the Publication must include the Carbon Design Systems copyright notice• Carbon Design Systems logos may only be used with Carbon's expressed written permission, including but not limitedto: linking through hyperlinks, electronic display, and print format.Disclaimer of WarrantyThis publication is provided “as is” without warranty of any kind, either expressed or implied, including, but not limitedto, the implied warranties of merchantability, fitness for a particular purpose, or non-infringement. Carbon Design Systemsassumes no responsibility for errors or omissions in this publication or other documents which are referenced by orlinked to this publication.References to corporations, their services and products, are provided “as is” without warranty of any kind, eitherexpressed or implied. In no event shall Carbon Design Systems be liable for any special, incidental, indirect or consequentialdamages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss ofuse, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or inconnection with the use or performance of this information.This publication may include technical or other inaccuracies or typographical errors. Carbon Design Systems may makeimprovements and/or changes in the product(s) and/or the program(s) described in this publication and in the publicationitself at any time.Trademarks© 2003-2013 Carbon Design Systems, Inc. All rights reserved. Carbon Design Systems, the Carbon Design Systemslogo, Carbon Model Studio, Replay, OnDemand, SoC Designer, Software Before Silicon, SOC-VSP, Swap & Play, VSP,The Answer to Validation, and The Trusted Path to Accuracy are trademarks or registered trademarks of Carbon DesignSystems, Incorporated in the United States and/or other countries.ARM, AMBA and RealView are registered trademarks of ARM Limited. AHB, APB and AXI are trademarks of ARMLimited. “ARM” is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiariesARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co.Ltd.; ARM Belgium N.V.; ARM Embedded Technologies Pvt. Ltd.; and ARM Physical IP, Inc.Microsoft, Windows 2000, and Windows XP are trademarks or registered trademarks of Microsoft Corporation in theUnited States and/or other countries.SystemC is a trademark of the Open SystemC Initiative.All other trademarks, registered trademarks, and products referenced herein are the property of their respective owners.Carbon Design Systems, Inc. Confidential

Technical SupportIf you have questions or problems concerning Carbon software, contact Technical Support.Phone Support Hours: Monday–Friday9:00 am–5:00 pm ESTCarbon Design Systems, Inc.125 Nagog ParkActon, MA 01720Voice: +1-978-264-7399Asia: +81-3-5524-1288Fax: +1-978-264-9990Email: support@carbondesignsystems.comWeb: www.carbondesignsystems.comVoice mail is available after hours. You may also access our on-line feedback form any time from the Support page ofthe Carbon web site.Document updated March 2013.

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ContentsChapter 1.Using the Model Kit Component in SoC DesignerNIC-301 Model Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1Implemented Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Hardware Features not Implemented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Features Additional to the Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Adding and Configuring the SoC Designer Component . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3Carbon SoC Designer Component Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3Adding the Carbon Model to the Component Library . . . . . . . . . . . . . . . . . . . . . . . . . .1-4Adding the Component to the SoC Designer Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4Available Component ESL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5Setting Component Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6Using the Track In-Flight Data parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9Available Profiling Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12Carbon Design Systems, Inc. Confidential

viContentsCarbon Design Systems, Inc. Confidential

PrefaceAbout This GuideA Carbon Model component is a library developed from ARM intellectual property (IP)that is generated through Carbon Model Studio. The model then can be used within avirtual platform tool, for example, Carbon SoC Designer Plus.This guide provides all the information needed to configure and use the Carbon NIC-301Model in Carbon SoC Designer Plus.AudienceThis guide is intended for experienced hardware and software developers who create componentsfor use with Carbon SoC Designer Plus. You should be familiar with the followingproducts and technology:• Carbon SoC Designer Plus• Hardware design verification• Verilog or VHDL programming languageCarbon Design Systems, Inc. Confidential

viiiPrefaceConventionsThis guide uses the following conventions:Convention Description ExamplecourieritalicboldCommands, functions,variables, routines, andcode examples that are setapart from ordinary text.New or unusual words orphrases appearing for thefirst time.Action that the user performs.Values that you fill in, orthat the system automaticallysupplies.[ text ] Square brackets [ ] indicateoptional text.[ text1 | text2 ] The vertical bar | indicates“OR,” meaning that youcan supply text1 or text 2.sparseMem_t SparseMemCreate-New();Transactors provide the entry and exitpoints for data ...Click Close to close the dialog./ represents the name ofvarious platforms.$CARBON_HOME/bin/modelstudio[ ]$CARBON_HOME/bin/modelstudio[.symtab.db |.ccfg ]Also note the following references:• References to C code implicitly apply to C++ as well.• File names ending in .cc, .cpp, or .cxx indicate a C++ source file.Carbon Design Systems, Inc. Confidential

xPrefaceGlossaryAMBAAHBAPBAXICarbon ModelCarbon ModelStudioCASICADICAPIComponentESLHDLRTLSoC DesignerSystemCTransactorAdvanced Microcontroller Bus Architecture. The ARM open standard on-chipbus specification that describes a strategy for the interconnection and managementof functional blocks that make up a System-on-Chip (SoC).Advanced High-performance Bus. A bus protocol with a fixed pipelinebetween address/control and data phases. It only supports a subset of the functionalityprovided by the AMBA AXI protocol.Advanced Peripheral Bus. A simpler bus protocol than AXI and AHB. It isdesigned for use with ancillary or general-purpose peripherals such as timers,interrupt controllers, UARTs, and I/O ports.Advanced eXtensible Interface. A bus protocol that is targeted at high performance,high clock frequency system designs and includes a number of featuresthat make it very suitable for high speed sub-micron interconnect.A software object created by the Carbon Model Studio (or Carbon compiler)from an RTL design. The Carbon Model contains a cycle- and register-accuratemodel of the hardware design.Carbon’s graphical tool for generating, validating, and executing hardwareaccuratesoftware models. It creates a Carbon Model, and it also takes a CarbonModel as input and generates a Carbon component that can be used inSoC Designer, Platform Architect, or OSCI SystemC for simulation.ESL API Simulation Interface, is based on the SystemC communicationlibrary and manages the interconnection of components and communicationbetween components.ESL API Debug Interface, enables reading and writing memory and registervalues and also provides the interface to external debuggers.ESL API Profiling Interface, enables collecting historical data from a componentand displaying the results in various formats.Building blocks used to create simulated systems. Components are connectedtogether with unidirectional transaction-level or signal-level connections.Electronic System Level. A type of design and verification methodology thatmodels the behavior of an entire system using a high-level language such as Cor C++.Hardware Description Language. A language for formal description of electroniccircuits, for example, Verilog or VHDL.Register Transfer Level. A high-level hardware description language (HDL)for defining digital circuits.The full name is Carbon SoC Designer. A high-performance, cycle accuratesimulation framework which is targeted at System-on-a-Chip hardware andsoftware debug as well as architectural exploration.SystemC is a single, unified design and verification language that enables verificationat the system level, independent of any detailed hardware and softwareimplementation, as well as enabling co-verification with RTL design.Transaction adaptors. You add transactors to your Carbon component to connectyour component directly to transaction level interface ports for your particularplatform.Carbon Design Systems, Inc. Confidential

1-6 Using the Model Kit Component in SoC Designer1.4 Setting Component ParametersYou can change the settings of all the component parameters in SoC Designer Canvas, andof some of the parameters in SoC Designer Simulator. To modify the Carbon component’sparameters:1. In the Canvas, right-click on the Carbon component and select Edit Parameters....You can also double-click the component. The Edit Parameters dialog box appears.Figure 1-2 Component Parameters Dialog Box2. In the Parameters window, double-click the Value field of the parameter that youwant to modify.Carbon Design Systems, Inc. Confidential

Setting Component Parameters 1-73. If it is a text field, type a new value in the Value field. If a menu choice is offered,select the desired option. The parameters are described in Table 1-3.Table 1-3 Component ParametersNameDescriptionAllowedValuesDefault Value Runtime 1Align WaveformsCarbon DB PathDump WaveformsEnable Debug Messagesresetnresetn_rWhen set to true, waveformsdumped from the Carbon componentare aligned with the SoCDesigner simulation time. The resetsequence, however, is not includedin the dumped data.When set to false, the resetsequence is dumped to the waveformdata, however, the Carboncomponent time is not aligned withthe SoC Designer time.Sets the directory path to the Carbondatabase file.Whether SoC Designer dumpswaveforms for this component.Whether debug messages arelogged for the component.Sets the value for the specifiedReset signal, or signals, correspondingto the specified clockdomain.If a resetn_rsignal exists, this parameter sets thevalue for the specified Reset signal,or signals, corresponding to thespecified clock domain._ Sizes of memory regions. 0x0 -size[0-5] 2 0x100000000true, false true NoNot Used empty Notrue, false false Yestrue, false false Yes0x0, 0x1 0x1 Yes0x0, 0x1 0x1 Yessize0 default is0x100000000,size1-5 defaultis 0_ Start addresses of memory regions. 0x0 - 0xffffffff 0x00000000 Nostart[0-5] 2Enable Debug MessagesEnable Debug MessagesWhether debug messages arelogged for the master ports. Thereis one parameter for each masterport.Whether debug messages arelogged for the slave ports. There isone parameter for each slave port.Notrue, false false Yestrue, false false YesCarbon Design Systems, Inc. Confidential

1-8 Using the Model Kit Component in SoC DesignerTable 1-3 Component Parameters (Continued)NameDescriptionAllowedValuesDefault Value Runtime 1Track In-Flight Data 3Enables or disables debug accessfor in-flight transactions.1.4.1 Using the Track In-Flight Data parametertrue, false true NoWaveform File 4 Name of the waveform file. string carbon_pl301_NIC301.vcdWaveform FormatWaveform TimescaleThe format of the waveform dumpfile.Sets the timescale to be used in thewaveform.The Track In-Flight Data parameter should be set to True (this is the default) if you areusing any debugAccess functions in the NIC-301. debugAccess functions are used toimplement the Memory view of a processor and any Disassembly view of memory. If inflighttracking is disabled, then the information in one of these views may be incorrectwhile there are incomplete write transactions within the NIC301.Disabling Track In-Flight Data may be appropriate if the accuracy of a processor’s Disassemblyview or Memory view is not critical. Whether or not Track In-Flight Data isenabled, opening a Memory view from the desired memory always provides an accurateview of its contents.NoVCD, FSDB VCD NoMany values indrop-down1 ns No1. Yes means the parameter can be dynamically changed during simulation, No means it can be changed onlywhen building the system, Reset means it can be changed during simulation, but its new value is taken intoaccount only at the next reset.2. The square brackets indicate the memory regions available for the model. For example, the parameter namefor the start addresses “s_[0-1]_start[0-5]” will be expanded to 12 possible parameter name combinations thatrange from “s_0_start0” to “s_1_start5”. The size of a memory region depends on the “s[N]_start[M]” and“s[N]_size[M]” parameters. The end address is calculated as StartAddr +Size -1. The size of the memoryregion must not exceed the value of 0x100000000. If the sum of StartAddr+Size is greater than 0x100000000,the size of the memory region is reduced to the difference: 0x100000000-StartAddr.3. Refer to the Section “Using the Track In-Flight Data parameter” below for more about this parameter.4. When enabled, SoC Designer writes accumulated waveforms to the waveform file in the following situations:when the waveform buffer fills, when validation is paused and when validation finishes, and at the end of eachvalidation run.Carbon Design Systems, Inc. Confidential

Debug Features 1-91.5 Debug FeaturesThe NIC-301 model has a debug interface (CADI) that allows the user to view, manipulate,and control the registers and memory. A view can be accessed in SoC Designer byright clicking on the model and choosing the appropriate menu entry.1.5.1 Register InformationFigure 1-3 shows the Register view of the NIC-301 model in SoC Designer Simulator.Figure 1-3 NIC-301 Registers ViewThe NIC-301 model has sets of registers that are accessible via the debug interface. Theslave interface, master interface, and internal interface port registers are described in theInterface Block registers section.The registers are listed below:• Address Control Registers• Peripheral ID Registers• Interface Block Registers1.5.1.1 Address Control RegistersTable 1-4 shows the Address Control registers.Table 1-4 Address Control RegistersName Description Typeremapsecurity0Remap register, up to eight global remap statesare available.Slave 0 security setting. 1 bit for non-virtualslaves, up to 16 for virtual or APB master interfaces,and you can configure it as follows:0 Secure1 Non-secureread-writeread-writeCarbon Design Systems, Inc. Confidential

1-10 Using the Model Kit Component in SoC DesignerTable 1-4 Address Control RegistersName Description Typesecurity1securitySlave 1 security setting. 1 bit for non-virtualslaves, up to 16 for virtual or APB master interfaces,and you can configure it as follows:0 Secure1 Non-secureSlave n security setting. 1 bit for non-virtualslaves, up to 16 for APB master interfaces.read-writeread-write1.5.1.2 Peripheral ID RegistersIf you configure any registers in the programmers view, peripheral ID registers are alwaysvisible. This provides a low gate count option for identification. Table 1-5 shows theperipheral ID registers.Table 1-5 Peripheral ID RegistersName Description TypePeripheral_ID0 Peripheral Identification Register 0 - Part Number read-onlyPeripheral_ID1 Peripheral Identification Register 1 - JEP106 and Part read-onlyNumberPeripheral_ID2Peripheral_ID3Peripheral_ID4Peripheral Identification Register 2 - Revision,JEP106 code flag, JEP106Peripheral Identification Register 3 - Can be set usingthe AMBA Designer Graphical User Interface (GUI)Peripheral Identification Register 4 - 4KB count,JEP106 continuation coderead-onlyread-onlyread-onlyPeripheral_ID5 Peripheral Identification Register 5 - Reserved read-onlyPeripheral_ID6 Peripheral Identification Register 6 - Reserved read-onlyPeripheral_ID7 Peripheral Identification Register 7 - Reserved read-onlyComponent_ID0 Component Identification Register 0 - Preamble read-onlyComponent_ID1 Component Identification Register 1 - Generic IPcomponent class, preambleread-onlyComponent_ID2 Component Identification Register 2 - Preamble read-onlyComponent_ID3 Component Identification Register 3 - Preamble read-onlyCarbon Design Systems, Inc. Confidential

Debug Features 1-111.5.1.3 Interface Block RegistersThere may be one register tab for each Interface Block (IB), where the IB can be:• Slave Interface Block (ASIB)• Master Interface Block (AMIB)• Internal network Interface Block (IB)Table 1-6 shows the Interface Block registers for the ASIB, AMID, and IB. Note that a tabmay be provided for each defined port (only for those ports that exist in the HDL). The tabwill show the type of port (SI, MI, or II) and the name of the port. Note that not all the registersare available for each IB type, or for each protocol type (AHB, AXI, APB).Table 1-6 Interface Block RegistersName Description Typesync_modefn_modfn_mod2fn_mod_ahbThis 3-bit register is valid only with a FIFO for all channels.You can configure the bits to create different clock domainboundaries as follows:0 sync 1:11 sync n:12 sync 1:n3 sync m:n4 async5 reserved6 reserved7 reservedThis 1-bit register is the issuing functionality modification register.Issuing override sets block issuing capability to be forcedto one transaction, and you can configure the bit as follows:0 Read issuing, read_iss_override1 Write issuing, write_iss_overrideBypass merge, only if upsizing or downsizing. See the Upsizingdata width function and Downsizing data width function sectionsin the TRM for more information.This 3-bit register is valid for AHB interfaces only. You canconfigure the bits of this register as follows:bit 0 rd_incr_overridebit 1 wr_incr_overridebit 2 lock_overrideIn the TRM, see Lock transactions for information on overridinglocks, and see Combination 4 for information onwr_incr_override and rd_incr_override.read-writeread-writeread-writeread-writefn_mod_iss_bm See the TRM for more information. read-writeCarbon Design Systems, Inc. Confidential

1-12 Using the Model Kit Component in SoC DesignerTable 1-6 Interface Block Registers (Continued)Name Description Typeahb_cntlwr_tidemarkread_qoswrite_qosThis 2-bit register is valid for AHB interfaces only. You canconfigure the bits as follows:bit 0 decerr_enbit 1 force_incrSee AHB master interfaces in the TRM for more information.This 4-bit register is valid only with a FIFO for the WFIFOchannel, and if not an AHB slave interface. See the FIFO andclocking function section in the TRM for more information.This 4-bit register is available in the ASIB only. This is theRead channel QoS value.This 4-bit register is available in the ASIB only. This is theWrite channel quality value.read-writeread-writeread-writeread-writeThe following registers are only available for interface blocks that were configured with the QoSextensions that are provided by the QoS Extension package for the NIC301. This configurationmust be done while defining the NIC301.qos_cntl QoS Control Register read-writemax_ot Maximum number of outstanding transactions Register read-writemax_comb_ot Maximum number of combined transactions Register read-writeaw_p AW channel peak rate Register read-writeaw_b AW channel burstiness allowance Register read-writeaw_r AW channel average rate Register read-writear_p AR channel peak rate Register read-writear_b AR channel burstiness allowance Register read-writear_r AR channel average rate Register read-writetgt_latency Target latency Register read-writeki Latency regulation Register read-writeqos_range QoS range Register read-write1.6 Available Profiling DataThe NIC-301 model component has no profiling capabilities.Carbon Design Systems, Inc. Confidential