Carbon Cortex-A9 Model User Guide for SoC Designer

Carbon Cortex-A9 ModelUser Guide forSoC Designer PlusCarbon Model Version 4.2.0For the ARM Cortex-A9 Single Core and Cortex-A9 MPCore ProcessorSilicon Version: r1p2, r2p2The Trusted Path to Accuracy The information contained in this document is confidential information of Carbon Design Systems, Inc.,and may not be duplicated or disclosed to unauthorized and/or third parties.

CopyrightCopyright © 2003-2013 Carbon Design Systems, Inc. All rights reserved.Files, documents or portions thereof presented on the Carbon Design Systems Internet server “Publication”, permits personsto view, copy, and print the Publication subject to the following conditions:• The Publication are to be kept strictly confidential• Copies of the Publication will not be distributed• Copies of the Publication must include the Carbon Design Systems copyright notice• Carbon Design Systems logos may only be used with Carbon's expressed written permission, including but not limitedto: linking through hyperlinks, electronic display, and print format.Disclaimer of WarrantyThis publication is provided “as is” without warranty of any kind, either expressed or implied, including, but not limitedto, the implied warranties of merchantability, fitness for a particular purpose, or non-infringement. Carbon Design Systemsassumes no responsibility for errors or omissions in this publication or other documents which are referenced by orlinked to this publication.References to corporations, their services and products, are provided “as is” without warranty of any kind, eitherexpressed or implied. In no event shall Carbon Design Systems be liable for any special, incidental, indirect or consequentialdamages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss ofuse, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or inconnection with the use or performance of this information.This publication may include technical or other inaccuracies or typographical errors. Carbon Design Systems may makeimprovements and/or changes in the product(s) and/or the program(s) described in this publication and in the publicationitself at any time.Trademarks© 2003-2012 Carbon Design Systems, Inc. All rights reserved. Carbon Design Systems, the Carbon Design Systemslogo, Carbon Model Studio, Replay, OnDemand, SoC Designer, Software Before Silicon, SOC-VSP, Swap & Play, VSP,The Answer to Validation, and The Trusted Path to Accuracy are trademarks or registered trademarks of Carbon DesignSystems, Incorporated in the United States and/or other countries.ARM, AMBA and RealView are registered trademarks of ARM Limited. AHB, APB and AXI are trademarks of ARMLimited. “ARM” is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiariesARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co.Ltd.; ARM Belgium N.V.; ARM Embedded Technologies Pvt. Ltd.; and ARM Physical IP, Inc.Microsoft, Windows 2000, and Windows XP are trademarks or registered trademarks of Microsoft Corporation in theUnited States and/or other countries.SystemC is a trademark of the Open SystemC Initiative.All other trademarks, registered trademarks, and products referenced herein are the property of their respective owners.Carbon Design Systems, Inc. Confidential

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ContentsPrefaceAbout This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiAudience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiConventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viiiFurther reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixGlossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixChapter 1.Using the Model Kit Component in SoC Designer PlusCortex-A9 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1Implemented Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Hardware Features not Implemented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Features Additional to the Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3Adding and Configuring the SoC Designer Plus Component . . . . . . . . . . . . . . . . . . . . . . . .1-3Carbon SoC Designer Plus Component Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3Adding the Carbon Model to the Component Library . . . . . . . . . . . . . . . . . . . . . . . . . .1-4Adding the Component to the SoC Designer Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5Available Component ESL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6Setting Component Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15VA to PA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16Normal World Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16Secure World Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17Cache Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18Perf Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19SCU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20Global Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20Timer/Watchdog Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21Processor Interface (Int IF) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21Interrupt Distributor (Int Dist) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22VFP/Neon Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22PLE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23Carbon Design Systems, Inc. Confidential

viRun To Debug Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-24Memory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-24Disassembly View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-25Available Profiling Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-26Hardware Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-26Software Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-28Carbon Design Systems, Inc. Confidential

PrefaceAbout This GuideA Carbon Model component is a library developed from ARM intellectual property (IP)that is generated through Carbon Model Studio. The model then can be used within avirtual platform tool, for example, Carbon SoC Designer Plus.This guide provides all the information needed to configure and use the Carbon Cortex-A9single-processor (UNI) or multi-processor (MPCore) Model in Carbon SoC DesignerPlus.AudienceThis guide is intended for experienced hardware and software developers who create componentsfor use with Carbon SoC Designer Plus. You should be familiar with the followingproducts and technology:• Carbon SoC Designer Plus• Hardware design verification• Verilog or VHDL programming languageCarbon Design Systems, Inc. Confidential

viiiPrefaceConventionsThis guide uses the following conventions:Convention Description ExamplecourieritalicboldCommands, functions,variables, routines, andcode examples that are setapart from ordinary text.New or unusual words orphrases appearing for thefirst time.Action that the user performs.Values that you fill in, orthat the system automaticallysupplies.[ text ] Square brackets [ ] indicateoptional text.[ text1 | text2 ] The vertical bar | indicates“OR,” meaning that youcan supply text1 or text 2.sparseMem_t SparseMemCreate-New();Transactors provide the entry and exitpoints for data ...Click Close to close the dialog./ represents the name ofvarious platforms.$CARBON_HOME/bin/modelstudio[ ]$CARBON_HOME/bin/modelstudio[.symtab.db |.ccfg ]Also note the following references:• References to C code implicitly apply to C++ as well.• File names ending in .cc, .cpp, or .cxx indicate a C++ source file.Carbon Design Systems, Inc. Confidential

PrefaceixFurther readingGlossaryThis section lists related publications by Carbon and by third parties.Carbon Model DocumentationThe following publications provide information that relate directly to models from CarbonDesign Systems:• Carbon Cortex-A9 Model Generation Guide• Carbon Model Installation and Licensing GuideCarbon SoC Designer Plus DocumentationThe following publications provide information that relate directly to SoC Designer Plus:• Carbon SoC Designer Plus Installation Guide• Carbon SoC Designer Plus User Guide• Carbon SoC Designer Plus RTOE User Guide• Carbon SoC Designer Plus Standard Component Library Reference ManualExternal publicationsThe following publications provide reference information about ARM® products:• ARM Cortex-A9 Technical Reference Manual• ARM Cortex-A9 MPCore Technical Reference Manual• Cortex-A9 Floating-Point Unit Technical Reference Manual• Cortex-A9 NEON Media Processing Engine Technical Reference Manual• Cortex-A9 Configuration and Sign-Off Guide• AMBA Specification• AMBA AHB Transaction Level Modeling Specification• AMBA AXI Transaction Level Modeling Specification• Architecture Reference Manual• ARM RealView Model Debugger User GuideSee http://infocenter.arm.com/help/index.jsp for access to ARM documentation.The following publications provide additional information on simulation:• IEEE 1666 SystemC Language Reference Manual, (IEEE Standards Association)• SPIRIT User Guide, Revision 1.2, SPIRIT Consortium.AMBAAdvanced Microcontroller Bus Architecture. The ARM open standard on-chipbus specification that describes a strategy for the interconnection and managementof functional blocks that make up a System-on-Chip (SoC).Carbon Design Systems, Inc. Confidential

xPrefaceAHBAPBAXICarbon ModelCarbon ModelStudioCASICADICAPIComponentESLHDLRTLSoC DesignerSystemCTransactorAdvanced High-performance Bus. A bus protocol with a fixed pipelinebetween address/control and data phases. It only supports a subset of the functionalityprovided by the AMBA AXI protocol.Advanced Peripheral Bus. A simpler bus protocol than AXI and AHB. It isdesigned for use with ancillary or general-purpose peripherals such as timers,interrupt controllers, UARTs, and I/O ports.Advanced eXtensible Interface. A bus protocol that is targeted at high performance,high clock frequency system designs and includes a number of featuresthat make it very suitable for high speed sub-micron interconnect.A software object created by the Carbon Model Studio (or Carbon compiler)from an RTL design. The Carbon Model contains a cycle- and register-accuratemodel of the hardware design.Carbon’s graphical tool for generating, validating, and executing hardwareaccuratesoftware models. It creates a Carbon Model, and it also takes a CarbonModel as input and generates a Carbon component that can be used inSoC Designer Plus, Platform Architect, or OSCI SystemC for simulation.ESL API Simulation Interface, is based on the SystemC communicationlibrary and manages the interconnection of components and communicationbetween components.ESL API Debug Interface, enables reading and writing memory and registervalues and also provides the interface to external debuggers.ESL API Profiling Interface, enables collecting historical data from a componentand displaying the results in various formats.Building blocks used to create simulated systems. Components are connectedtogether with unidirectional transaction-level or signal-level connections.Electronic System Level. A type of design and verification methodology thatmodels the behavior of an entire system using a high-level language such as Cor C++.Hardware Description Language. A language for formal description of electroniccircuits, for example, Verilog or VHDL.Register Transfer Level. A high-level hardware description language (HDL)for defining digital circuits.The full name is Carbon SoC Designer Plus. A high-performance, cycle accuratesimulation framework which is targeted at System-on-a-Chip hardwareand software debug as well as architectural exploration.SystemC is a single, unified design and verification language that enables verificationat the system level, independent of any detailed hardware and softwareimplementation, as well as enabling co-verification with RTL design.Transaction adaptors. You add transactors to your Carbon component to connectyour component directly to transaction level interface ports for your particularplatform.Carbon Design Systems, Inc. Confidential

Chapter 1Using the Model Kit Component inSoC Designer PlusThis chapter describes the functionality of the Model component, and how to use it inCarbon SoC Designer Plus. It contains the following sections:• Cortex-A9 Functionality• Adding and Configuring the SoC Designer Plus Component• Available Component ESL Ports• Setting Component Parameters• Debug Features• Available Profiling Data1.1 Cortex-A9 FunctionalityThe Cortex-A9 processors can be used in both a uniprocessor configuration and multiprocessorconfigurations.In the multiprocessor configuration, up to four Cortex-A9 processors are available in acache-coherent cluster, under the control of a Snoop Control Unit (SCU), that maintainsL1 data cache coherency.The Cortex-A9 MPCore multiprocessor has:• up to four Cortex-A9 processors• an SCU responsible for maintaining coherency among L1 data caches• an Interrupt Controller (IC) with support for legacy ARM interrupts• a private timer and a private watchdog per processor• a global timer• AXI high-speed Advanced Microprocessor Bus Architecture (AMBA) L2 interfaces.• an Accelerator Coherency Port (ACP), an optional AXI 64-bit slave port that can beconnected to a DMA engine or a non-cached peripheral.It is possible to implement only one Cortex-A9 processor in a Cortex-A9 MPCore processordesign. In this configuration, an SCU is still provided. The ACP, and an additionalmaster port, are also available in this configuration.Carbon Design Systems, Inc. Confidential

1-2 Using the Model Kit Component in SoC Designer PlusThis section provides a summary of the functionality of the model compared to that of thehardware, and the performance and accuracy of the model.• Implemented Hardware Features• Hardware Features not Implemented• Features Additional to the Hardware1.1.1 Implemented Hardware FeaturesMost hardware features have been implemented. Some functionality and register pin differencesare listed in the next section.Note that when using semihosting you must use the semihost component from Carbon.This “CarbonSemihost” component is included in the Carbon SoC Designer Plus StandardModel Library, version 3.0 or greater. The ARM RVML semihost component will notwork with the Carbon Model.See the ARM Cortex-A9 MPCore Technical Reference Manual for more information.1.1.2 Hardware Features not ImplementedThe following features of the Cortex-A9 hardware are not implemented in the Carbonizedmodel:• TLB Lockdown support is limited. If the system uses TLB lockdown to create entriesthat differ from the page table entries, the Virtual Address-to-Physical Address translationmay be incorrect. Consequently, debug access to the Memory View may returnincorrect data.• The following registers are not available to be read / written via debug transactions —for example, in the SoC Designer Plus Registers window, or by accessing themdirectly from RealView Debugger:– Control register; ADFSR, AIFSR, and FCSEIDR– Normal World register; N_ACTLR, N_ADFSR, N_AIFSR, and N_FCSEIDR– Secure World register; S_ACTLR, S_ADFSR, S_AIFSR, and S_FCSEIDR– Cache register; ICIALLU, ICIMVAU, FPB, BPIALL, BPIMVA, DCIMVAC,DCISW, DCCMVAC, DCCSW, DCCMVAU, DCCIMVAC, and DCCISW– TLB register; not supported– Virtual Address to Physical Address register; V2PCWPR, V2PCWPW,V2PCWUR, V2PCWUW, V2POWPR, V2POWPW, V2POWUR, and V2POWUW– Performance (Perf) register; PMSWINCThe functionality of these registers, however, does exist and can be accessed by softwarerunning on the virtual platform.• Some register pins are read-only as well. See the section “Register Information” onpage 1-12 for more information.• Features of the following profiling streams are not supported:– I-Cache; Read Hit, Uncached Read, Uncached Write, Line Fill, and Line EvictionCarbon Design Systems, Inc. Confidential

Adding and Configuring the SoC Designer Plus Component 1-3• Debug transactions do not fully support cache coherence. This means that the debugtransaction could read or write data without realizing that it is accessing data thatresides in the other cores’ L1 cache. Debug transactions are needed by RVD accessesto memory, as well as by semihosting. If you see a different memory value from RVDthan what you see by opening the Memory view in the processor and memory, thenyour design may have encountered this limitation.1.1.3 Features Additional to the HardwareThe following features that are implemented in the Cortex-A9 model do not exist in theCortex-A9 hardware. These features have been added to the model for enhanced usability.• The component supports positive and negative level irq and fiq signal. This is configurableusing the negLogic parameter (see Table 1-3 on page 1-9).• The “run to debug point” feature has been added. This feature forces the debugger toadvance the processor to the debug state instead of having the model get into a nondebuggablestate. See “Run To Debug Point” on page 1-24 for more information.1.2 Adding and Configuring the SoC Designer Plus ComponentThe following topics briefly describe how to use the component. See the Carbon SoCDesigner Plus User Guide for more information.• Carbon SoC Designer Plus Component Files• Adding the Carbon Model to the Component Library• Adding the Component to the SoC Designer Canvas1.2.1 Carbon SoC Designer Plus Component FilesThe component files are the final output from the Carbon Model Studio compile and arethe input to SoC Designer Plus. There are two versions of the component; an optimizedrelease version for normal operation, and a debug version.On Linux, the debug version of the component is compiled without optimizations andincludes debug symbols for use with gdb. The release version is compiled without debuginformation and is optimized for performance.On Windows, the debug version of the component is compiled referencing the debug runtimelibraries so it can be linked with the debug version of SoC Designer Plus. The releaseversion is compiled referencing the release runtime library. Both release and debug versionsgenerate debug symbols for use with the Visual C++ debugger on Windows.Carbon Design Systems, Inc. Confidential

1-4 Using the Model Kit Component in SoC Designer PlusThe provided component files are listed below:Table 1-1 Carbon SoC Designer Plus Component FilesPlatform File DescriptionLinuxWindowsmaxlib.lib.conflib.mx.solib.mx_DBG.somaxlib.lib.windows.conflib.mx.dlllib.mx_DBG.dllSoC Designer Plus configuration fileSoC Designer Plus component runtime fileSoC Designer Plus component debug fileSoC Designer Plus configuration fileSoC Designer Plus component runtime fileSoC Designer Plus component debug fileAdditionally, this User Guide PDF file and a ReadMe text file are provided with the component.1.2.2 Adding the Carbon Model to the Component LibraryThe compiled Carbon Model component is provided as a configuration file (.conf). Tomake the component available in the Component Window in SoC Designer Canvas, performthe following steps:1. Launch SoC Designer Canvas.2. From the File menu, select Preferences.3. Click on Component Library in the list on the left.4. Under the Additional Component Configuration Files window, click Add.5. Browse to the location where the SoC Designer Plus model is located and select thecomponent configuration file:– maxlib.lib.conf (for Linux)– maxlib.lib.windows.conf (for Windows)6. Click OK.7. To save the preferences permanently, click the OK & Save button.The component is now available from the SoC Designer Plus Component Window.Carbon Design Systems, Inc. Confidential

Adding and Configuring the SoC Designer Plus Component 1-51.2.3 Adding the Component to the SoC Designer CanvasLocate the component in the Component Window and drag it out to the Canvas. It appearsas shown in Figure 1-1. Note that ports may vary depending on your configuration.UniprocessorMulti-processorFigure 1-1 Cortex-A9 MPCore and Uniprocessor Components inSoC Designer PlusThe figure shows the component with two Master AXI ports. The second master portappears only if it was defined in the model RTL configuration file (CORTEXA9MP.conf).Carbon Design Systems, Inc. Confidential

1-6 Using the Model Kit Component in SoC Designer Plus1.3 Available Component ESL PortsACLKENSTable 1-2 describes the ESL ports that are exposed in SoC Designer Plus. Some ports mayor may not appear depending on whether you are using the multiprocessor or uniprocessorversion of the ARM hardware. See the ARM Cortex-A9 Technical Reference Manual orARM Cortex-A9 MPCore Technical Reference Manual for more information.Table 1-2 ESL Component PortsESL Port Description Direction TypeBus clock enable. By default it is set to 1 through a componentparameter. If another component is connectedthrough this port, it will override the default value. Availableonly with the MPCore.InputSignal slaveACLKENM[0,1] 1 Controls AXI ports. Available only with uniprocessor Input Signal slaveconfiguration.apb_dbg APB debug interface. Input APB Transactionslaveaxi_m0 AXI Master port 0. Output AXI Transactionmasteraxi_m1axi_sAXI Master port 1. Available only when a second masterhas been defined in the configuration file.AXI ACP (Accelerator Coherency Port) Slave port.Available only when it has been enabled in the configurationfile.OutputInputAXI TransactionmasterAXI TransactionslaveCFGSDISABLE 2 Disables write access to some system control processor Input Signal slaveregisters.clk_in Input clock. Input Clock slaveCP15SDISABLE Disabled write access to some system control processor Input Signal slaveregisters.DBGACK Debug acknowledge signal. (Used only with CoreSight). Output Signal masterDBGRESTARTED Used with DBGRESTART to move between Debug and Output Signal masterNormal state. (Used only with CoreSight).EDBGRQ External debug request. (Used only with CoreSight). Input Signal slaveEVENTIEvent input for Cortex-A9 processor wake-up from WFE Input Signal slavestate.EVENTOEvent output. This signal is active when one SEV instructionis executed.Output Signal masterextSemi There is an extSemi port per core in a multi-core A9,where is 0-3 to represent the core. In the single-processorversion, this port is simply extSemi0. Semihostingcan be enabled by connecting these ports to the SoCDesigner Plus semihost component contained in the CarbonSoC Designer Plus Standard Model Library (v3.0 orgreater).OutputTransaction masterCarbon Design Systems, Inc. Confidential

Available Component ESL Ports 1-7fiq 2Cortex-A9 processor private FIQ request input lines:0 = do not activate fast interrupt1 = activate fast interruptInputSignal slaveINCLKENM[0,1] 2 Controls bus speed of AXI ports. Input Signal slaveINTThis port connects to external interrupt signals. It can beany size between 0 and 224, in increments of 32. Thevalue must indicate the interrupt number [NumIRQ..0]and the *extValue must indicate whether the IRQ line isasserted (*extValue=1) or deasserted (*extValue=0).Input Signal slaveirq 1Cortex-A9 processor legacy IRQ request input lines:0 = do not activate interrupt1 = activate interruptInputSignal slavenCPureset 2 Active low reset, 4 bits wide. Input Signal slavenDBGRESET 2 Active low reset, 4 bits wide. Input Signal slavenNEONRESET 2 Active low reset, 4 bits wide. Available with Neon configurationsInput Signal slaveat version r2px only.nDERESET Active low reset, 4 bits wide. Available only with Neonconfurations at versions later than r2p0.Input Signal slavenPERIPHRESET 2nSCURESET 2nWDRESET 2Table 1-2 ESL Component Ports (Continued)ESL Port Description Direction TypeActive low reset, 1 bit wide. Available with MP configurationonly.Active low reset, 2 bit wide. Available with MP configurationonly.Active low reset, 4 bits wide. Available with MP configurationonly.InputInputInputSignal slaveSignal slaveSignal slaveOUTCLKENM[0,1] 2 Controls bus speed of AXI ports. Input Signal slavePERIPHCLK Clock for the timer and Interrupt Controller. Available Input Signal slavewith MP configuration only.PERIPHCLKEN Clock enable for the timer and Interrupt Controller. AvailableInput Signal slavewith MP configuration only.SMPnAMP Signals AMP or SMP mode for each Cortex-A9 MPCore Output Signal masterprocessor.STANDBYWFE Indicates if a Cortex-A9 processor is in WFE state. Output Signal masterSTANBYWFI Indicates that a Cortex-A9 processor is in Standby mode. Output Signal masterWDRESETREQ Watchdog reset request. Output Signal master1. Refer to the ARM Cortex-A9 Technical Reference Manual for details on driving these pins.2. For these interrupt ports, the active high/low setting is controlled by the negLogic component parameter. Thedefault is active high.All pins that are not listed in this table have been either tied or disconnected for performancereasons.Carbon Design Systems, Inc. Confidential

1-8 Using the Model Kit Component in SoC Designer PlusNote:Some ESL component port values can be set using a component parameter. Thisincludes the ACLKENS and CP15SDISABLE ports. In these cases, the parametervalue is used whenever the ESL port is not connected. If the port is connected, theconnection value takes precedence over the parameter value.1.4 Setting Component ParametersYou can change the settings of all the component parameters in SoC Designer Plus Canvas,and of some of the parameters in SoC Designer Simulator. To modify the Carboncomponent’s parameters:1. In the Canvas, right-click on the Carbon component and select Edit Parameters....You can also double-click the component. The Edit Parameters dialog box appears.Figure 1-2 Component Parameters Dialog BoxThe list of available parameters will be slightly different depending on the settings thatyou enabled in the configuration file (for example, CORTEXA9MP.conf) and dependingon whether you are using the multi-processor or uniprocessor version of the ARMhardware.2. In the Parameters window, double-click the Value field of the parameter that youwant to modify.3. If it is a text field, type a new value in the Value field. If a menu choice is offered,select the desired option. The parameters are described in Table 1-3.Carbon Design Systems, Inc. Confidential

Setting Component Parameters 1-9Table 1-3 Component ParametersNameDescriptionAllowedValuesDefault Value Runtime 1ACLKENS Bus clock enable. integer 1 YesAlign Waveforms When set to true, waveforms dumpedby the Carbon component are alignedwith the SoC Designer Plus simulationtime. The reset sequence, however,is not included in the dumpeddata.When set to false, the reset sequenceis dumped to the waveform data, however,the Carbon component time isnot aligned with SoC Designer Plustime.true, false true Noapb_dbg BaseAddressapb_dbg EnableDebug MessagesBase address 0x0 – 0xffffffff 0x0 NoWhether debug messages are loggedfor the APB port.apb_dbg Size Size 0x0 –0x100000000axi_m0 Enable DebugMessagesaxi_m1 Enable DebugMessagesaxi_s axi_size0axi_s axi_size[1-5]axi_s axi_start[0-5]axi_s Enable DebugMessagesCarbon DB PathWhether debug messages are loggedfor master port 0.Whether debug messages are loggedfor master port 1.These parameters are obsolete andshould be left at their default values. 2Whether debug messages are loggedfor the slave port.Sets the directory path to the Carbondatabase file.true, false false Yes0x100000000Notrue, false false Yestrue, false false Yes0x1000000000x00x00000000CFGEND Endianness configuration. 0 — 0xF forMPCore0,1 for UNICoreCFGNMFI Enables fast interrupts. 0 — 0xF forMPCore0,1 for UNICoreCLUSTERIDCP15SDISABLEValue read in Cluster ID register field,bits[11:8] of the MPIDR.Disables write access to some systemcontrol processor registers.0x1000000000x00x00000000Notrue, false false YesNot Used empty No0 NofalseNo0-15 0 No0 — 0xF forMPCore0,1 for UNICore0 YesCarbon Design Systems, Inc. Confidential

1-10 Using the Model Kit Component in SoC Designer PlusTable 1-3 Component Parameters (Continued)NameDescriptionAllowedValuesDefault Value Runtime 1DBGSWENABLE S/W Modify Debug Registers 0 — 0xF forMPCore0, 1 forUNICoreDump WaveformsEnable DebugMessagesFILTERENFILTERENDFILTERSTARTWhether SoC Designer Plus dumpswaveforms for this component.Whether debug messages are loggedfor the component.Enables filtering of address rangesAvailable only on MPCore, and onlyif the model has been configured withtwo AXI Master ports.End address[31:20] for filteringAvailable only on MPCore, and onlyif the model has been configured withtwo AXI Master ports.Start address[31:20] for filteringAvailable only on MPCore, and onlyif the model has been configured withtwo AXI Master ports.0xF for MPCore1 for UNICoreNotrue, false false Yestrue, false false Yes0,1 0 Noaddress 0 Noaddress 0 NoINCLKENM[0,1] Controls bus speed of AXI ports. value 1 NonegLogicSets IRQ/FIZ assertion to use negativelogic. Default of:false means 0 = off and 1 = on.true means 0 = on and 1 = offtrue, false false NoOUTCLKENM[0,1] 2 Controls bus speed of AXI ports. value 1 NoPC Tracing Core Enables dumping a PC trace to diskcontaining decode PCs and actualbranch PCs, where is 0-3 to representthe core. See “Software Profiling”on page 1-28.true, false false NoPC Tracing FileCorePERIPHBASEThe file to write the PC trace information,where is 0-3 to representthe core. The file is written in binaryformat. The C++ file pctracedump.cppcan be used to decode thedata.Specifies the base address for Timers,Watchdogs, Interrupt Controller, andSCU registers. Set to the base addressshifted right by 13 bits.Valid file nameCortexA9PC.datNoany 38976 (0x9800) YesCarbon Design Systems, Inc. Confidential

Setting Component Parameters 1-11Table 1-3 Component Parameters (Continued)NameDescriptionAllowedValuesDefault Value Runtime 1TEINITVINITHIDefault exception handling state:0 = ARM1 = ThumbIndividual processor control of thelocation of the exception vectors atreset.0 — 0xF forMPCore0, 1 forUNICore0 — 0xF forMPCore0,1 for UNICore0 NoWaveform File 3 Name of the waveform file. string carbon_CORTEX NoA9.vcd orcarbon_CORTEXA9MP.vcdWaveform Format Format of the waveform dump file. VCD, FSDB VCD NoWaveform Timescale Sets the timescale to be used in thewaveform.Many values indrop-down1 ns No1. Yes means the parameter can be dynamically changed during simulation, No means it can be changed onlywhen building the system, Reset means it can be changed during simulation, but its new value will be takeninto account only at the next reset.2. Carbon recommends using the Memory Map Editor (MME) in SoC Designer Plus, which provides centralizedviewing and management of the memory regions available to the components in a system. For informationabout migrating existing systems to use the MME, refer to Chapter 9 of the SoC Designer Plus User Guide.3. When enabled, SoC Designer Plus writes accumulated waveforms to the waveform file in the following situations:when the waveform buffer fills, when validation is paused and when validation finishes, and at the end ofeach validation run.0x0NoCarbon Design Systems, Inc. Confidential

1-12 Using the Model Kit Component in SoC Designer Plus1.5 Debug FeaturesThe Cortex-A9 model has a debug interface (CADI) that allows the user to view, manipulate,and control the registers and memory. A view can be accessed in SoC Designer Plusby right clicking on the model and choosing the appropriate menu entry.The following topics are discussed in this section:• Register Information• Run To Debug Point• Memory Information• Disassembly ViewNote:The Cortex-A9 can have up to two slave ports. The apb_dbg port is used for Core-Sight debug, and the axi_s port is for ACP, which is used to connect to a DMAengine. These are supported as simulation interfaces, but they are not supportedas debug interfaces. This means if a CADI operation is performed on one of theseinterfaces, it will not return data.1.5.1 Register InformationFigure 1-3 shows the Register view of the Cortex-A9 model in SoC Designer Simulator.Figure 1-3 Cortex-A9 Registers ViewThe Cortex-A9 model has many sets of registers that are accessible via the debug interface.Registers are grouped into sets according to functional area.• Core Registers• Debug Registers• ID Registers• VA to PA Registers• Normal World RegistersCarbon Design Systems, Inc. Confidential

Debug Features 1-13• Secure World Registers• Cache Registers• Control Registers• Perf Registers• SCU Registers• Global Timer Registers• Timer/Watchdog Registers• Processor Interface (Int IF) Registers• Interrupt Distributor (Int Dist) Registers• VFP/Neon Registers• PLE RegistersSee the ARM Cortex-A9 MPCore Technical Reference Manual for detailed descriptions ofthese registers.Note:Registers are accurate only at debuggable points. While SoC Designer Plus graysout the register view when the processor is not at a debuggable point, values arestill visible. Due to the speculative nature of the processor pipeline, these valuesare not guaranteed to be accurate.1.5.1.1 Core RegistersIn general, you can write to a register only at a debuggable point. If a value isdeposited at any other point, it may not be correctly propagated.The Core group contains the ARM architectural registers. This register is available onlywith the MPCore.Table 1-4 Core RegistersName Description TypeR0 R0 register read-write 1R1 R1 register read-write 1R2 R2 register read-write 1R3 R3 register read-write 1R4 R4 register read-write 1R5 R5 register read-write 1R6 R6 register read-write 1R7 R7 register read-write 1R8 R8 register read-write 1R9 R9 register read-write 1R10 R10 register read-write 1Carbon Design Systems, Inc. Confidential

1-14 Using the Model Kit Component in SoC Designer PlusTable 1-4 Core Registers (Continued)Name Description TypeR11 R11 register read-write 1R12 R12 register read-write 1R13 SP register read-write 1R14 LR register read-write 1R15 PC register read-writeR8_USR R8 USR register read-write 1R9_USR R9 USR register read-write 1R10_USR R10 USR register read-write 1R11_USR R11 USR register read-write 1R12_USR R12 USR register read-write 1R13_USR SP USR register read-write 1R14_USR LR USR register read-write 1CPSR Current Program Status Register register read-onlyR13_IRQ SP IRQ register read-write 1R14_IRQ LR IRQ register read-write 1SPSR_IRQ Saved Program Status Register IRQ register read-onlyR13_SVC SP SVC register read-write 1R14_SVC LR SVC register read-write 1SPSR_SVC Saved Program Status Register SVC register read-onlyR13_ABT SP ABT register read-write 1R14_ABT LR ABT register read-write 1SPSR_ABT Saved Program Status Register ABT register read-onlyR13_UND SP UND register read-write 1R14_UND LR UND register read-write 1SPSR_UND Saved Program Status Register UND register read-onlyR8_FIQ R8 FIQ register read-write 1R9_FIQ R9 FIQ register read-write 1R10_FIQ R10 FIQ register read-write 1R11_FIQ R11 FIQ register read-write 1R12_FIQ R12 FIQ register read-write 1R13_FIQ SP FIQ register read-write 1R14_FIQ LR FIQ register read-write 1Carbon Design Systems, Inc. Confidential

Debug Features 1-15Table 1-4 Core Registers (Continued)Name Description TypeSPSR_FIQ Saved Program Status Register FIQ register read-onlyR13_MON SP MON register read-write 1R14_MON LR MON register read-write 1SPSR_MON Saved Program Status Register MON register read-onlyExtendedTargetFeatures Used internally for TrustZone support read-onlyPC_MEMSPACE Used internally for TrustZone support read-only1. Writeable at debug point only.1.5.1.2 Debug RegistersThe Debug group provides access to the current debug state. This register is available onlywith the MPCore.Table 1-5 Debug RegistersName Description TypeCP14_DSCR Debug Status and Control Register Read-OnlyDBGBVR0 - DBGBVR5 Debug Breakpoint Value Registers Read/WriteDBGBCR0 - DBGBCR5 Debug Breakpoint Control Registers Read/Write1.5.1.3 ID RegistersThe ID group contains registers that describe the processor capabilities. This register isavailable only with the MPCore.Table 1-6 ID RegistersName Description TypeMIDR Main ID register read-onlyCTR Cache Type register read-onlyTCMTR TCM Type register read-onlyTLBTR TLB Type register read-onlyMPIDRMultiprocessor Affinity register. Only valid withthe Cortex-A9 MPCore.read-onlyID_PFR0 Processor Feature 0 register read-onlyID_PFR1 Processor Feature 1 register read-onlyID_DFR0 Debug Feature 0 register read-onlyID_AFR0 Auxiliary Feature 0 register read-onlyID_MMFR0 Memory Model Feature 0 register read-onlyID_MMFR1 Memory Model Feature 1 register read-onlyID_MMFR2 Memory Model Feature 2 register read-onlyCarbon Design Systems, Inc. Confidential

1-16 Using the Model Kit Component in SoC Designer PlusTable 1-6 ID Registers (Continued)Name Description TypeID_MMFR3 Memory Model Feature 3 register read-onlyID_ISAR0 ID_ISAR0 register read-onlyID_ISAR1 ID_ISAR1 register read-onlyID_ISAR2 ID_ISAR2 register read-onlyID_ISAR3 ID_ISAR3 register read-onlyID_ISAR4 ID_ISAR4 register read-onlyID_ISAR5 ID_ISAR5 register (always returns 0) read-onlyID_ISAR6 ID_ISAR6 register (always returns 0) read-onlyID_ISAR7 ID_ISAR7 register (always returns 0) read-only1.5.1.4 VA to PA RegistersThe VA to PA group contains registers to perform virtual to physical address translations.This register is available only with the MPCore.Table 1-7 VA to PA RegistersName Description TypePAR Physical address register read-write1.5.1.5 Normal World RegistersThe Normal World group contains control register that are only accessible in non-securemode This register is available only with the MPCore..Table 1-8 Normal World RegistersName Description TypeN_CSSELR Cache Size Selection register read-onlyN_SCTLR [N] System Control register read-writeN_TTBR0 [N] TTBR0 register read-writeN_TTBR1 [N] TTBR1 register read-writeN_TTBCR [N] TTBCR register read-writeN_DACR [N] Domain Access Control register read-writeN_DFSR [N] Data Fault Status register read-writeN_IFSR [N] Instruction Fault Status register read-writeN_DFAR [N] Data Fault Address register read-writeN_IFAR [N] Instruction Fault Address register read-writeN_PRRR [N] Primary Region Remap register read-writeN_NMRR [N] Normal Memory Remap register read-writeCarbon Design Systems, Inc. Confidential

Debug Features 1-17Table 1-8 Normal World Registers (Continued)Name Description TypeN_VBAR [N] Vector Base Address register read-writeN_CONTEXTIDR [N] Context ID register read-writeN_TPIDRURW [N] User Read/Write Thread ID register read-writeN_TPIDRURO [N] User Read Only Thread ID register read-writeN_TPIDRPRW [N] Privileged Only Thread ID register read-write1.5.1.6 Secure World RegistersThe Secure group contains control registers that are only accessible in secure mode. Thisregister is available only with the MPCore.Table 1-9 Secure World RegistersName Description TypeS_CSSELR Cache Size Selection register read-onlyS_SCTLR [S] System Control register read-writeS_TTBR0 [S] TTBR0 register read-writeS_TTBR1 [S] TTBR1 register read-writeS_TTBCR [S] TTBCR register read-writeS_DACR [S] Domain Access Control register read-writeS_DFSR [S] Data Fault Status register read-writeS_IFSR [S] Instruction Fault Status register read-writeS_DFAR [S] Data Fault Address register read-writeS_IFAR [S] Instruction Fault Address register read-writeS_PRRR [S] Primary Region Remap register read-writeS_NMRR [S] Normal Memory Remap register read-writeS_VBAR [S] Vector Base Address register read-writeS_CONTEXTIDR [S] Context ID register read-writeS_TPIDRURW [S] User Read/Write Thread ID register read-writeS_TPIDRURO [S] User Read Only Thread ID register read-writeS_TPIDRPRW [S] Privileged Only Thread ID register read-writeCarbon Design Systems, Inc. Confidential

1-18 Using the Model Kit Component in SoC Designer Plus1.5.1.7 Cache RegistersThe Cache group contains registers to access cache information. This register is availableonly with the MPCore.Table 1-10 Cache RegistersName Description TypeCCSIDR Cache Size ID register read-onlyCLIDR Cache Level ID register read-onlyAIDR Auxiliary ID register read-onlyCSSELR Cache Size Selection register read-onlyDCLR D-cache Lockdown register read-onlyICLR I-cache Lockdown register read-only1.5.1.8 Control RegistersThe Control group contains registers that dynamically configure the processor. This registeris available only with the MPCore.Table 1-11 Control RegistersName Description TypeSCTLR System Control register read-writeACTLRAuxiliary Control register. Only valid with the read-onlyCortex-A9 MPCore.CPACRCoprocessor Access Control register. Only availableif Neon and FPU processors are present.read-onlyNSACR Nonsecure Access Control register read-onlyVCR Virtualization Control register read-writeTTBR0 TTBR0 register read-writeTTBR1 TTBR1 register read-writeTTBCR TTBCR register read-writeDACR Domain Access Control register read-writeDFSR Data Fault Status register read-writeIFSR Instruction Fault Status register read-writeDFAR Data Fault Address register read-writeIFAR Instruction Fault Address register read-writePRRR Primary Region Remap register read-writeNMRR Normal Memory Remap register read-writeVBAR Vector Base Address register read-writeISR Interrupt Status register read-onlyVIR Virtualization Interrupt register read-onlyCarbon Design Systems, Inc. Confidential

Debug Features 1-19Table 1-11 Control Registers (Continued)Name Description TypeCONTEXTIDR Context ID register read-writeTPIDRURW User Read/Write Thread ID register read-writeTPIDRURO User Read Only Thread ID register read-writeTPIDRPRW Privileged Only Thread ID register read-writeSCR Secure Configuration register read-writeSDER Secure Debug Enable register read-writeMVBAR Monitor Vector Base Address register read-writeCBAR Configuration Base Address register read-write 11. read-write in Secure privileged mode. read-only in Non-secure state and in user mode.1.5.1.9 Perf RegistersThe Perf group contains performance related registers. This register is available only withthe MPCore.Table 1-12 Perf RegistersName Description TypePMCR Performance Monitor Control register read-writePMCNTENSET Count Enable Set register read-writePMCNTENCLR Count Enable Clear register read-writePMOVSR Overflow Flag Status register read-writePMSELR Event Counter Selection register read-writePMCCNTR Cycle Count register read-writePMXEVTYPER Event Selection register read-writePMXEVCNTR Performance Count register read-writePMUSERENR User Enable register read-writePMINTENSET Interrupt Enable Set register read-writePMINTENCLR Interrupt Enable Clear register read-writeCarbon Design Systems, Inc. Confidential

1-20 Using the Model Kit Component in SoC Designer Plus1.5.1.10 SCU RegistersThe SCU group contains registers that control the Snoop Control Unit. Addresses are relativeto the base address of the region for the SCU memory map. This register is availableonly with the MPCore.Table 1-13 SCU RegistersName Description TypeControl SCU Control register read-writeConfiguration SCU Configuration register read-onlyCPU Status SCU CPU Power Status register read-writeFilter Start Addr Filtering Start Address register read-writeFilter End Addr Filtering End Address register read-writeAccess Control SCU Access Control register read-writeSecure Access Control SCU Secure Access Control register read-write1.5.1.11 Global Timer RegistersThe Global Timer group contains and status registers related to the global timer added inthe r1p1 version of the model. This register is available only with the MPCore.Table 1-14 Global Timer RegistersName Description TypeLower Counter Lower 32-bit Timer Counter register read-writeUpper Counter Upper 32-bit Timer Counter register read-writeControl Timer Control register read-writeCompStatus Timer Comparator Status register read-writeLower Compare Lower 32-bit Comparator register read-writeUpper Compare Upper 32-bit Comparator register read-writeAuto-Increment Auto-Increment register for Comparator read-writeCarbon Design Systems, Inc. Confidential

Debug Features 1-211.5.1.12 Timer/Watchdog RegistersThe Timer/Watchdog group contains registers for controlling the timer and watchdogblocks for each CPU. Addresses are relative to the base address of the timer and watchdogregion defined by the private memory map (see the ARM Cortex-A9 Technical ReferenceManual for more information).This register is available only with the MPCore.Table 1-15 Timer/Watchdog RegistersName Description TypeCPUn Timer Load Timer Load register read-writeCPUn Timer Counter Timer Counter register read-writeCPUn Timer Control Timer Control register read-writeCPUn Timer Status Timer Interrupt Status register read-writeCPUn Watchdog Load Watchdog Load register read-writeCPUn Watchdog Counter Watchdog Counter register read-writeCPUn Watchdog Control Watchdog Control register read-writeCPUn Watchdog Status Watchdog Interrupt Status register read-writeCPUn Watchdog Reset Watchdog Reset Status register read-write1.5.1.13 Processor Interface (Int IF) RegistersThe Int IF group contains the registers that each Cortex-A9 processor interface provides.This register is available only with the MPCore.Table 1-16 Int IF RegistersName Description TypeControlS Processor Interface Control Secure register read-writeControlNS Processor Interface Control Non-secure register read-writePrioMaskS Priority Mask Secure register read-writePrioMaskNS Priority Mask Non-secure register read-writeBinPointS Binary Point Secure register read-writeBinPointNS Binary Point Non-secure register read-writeIntAck Interrupt Acknowledge register read-onlyRunPrioS Running Priority Secure register read-onlyRunPrioNS Running Priority Non-secure register read-onlyHiPendInt Highest Pending Interrupt register read-onlyAliasNSBinPoint Aliased Non-secure Binary Point register read-writeID Processor Interface Implementer Identification register read-onlyCarbon Design Systems, Inc. Confidential

1-22 Using the Model Kit Component in SoC Designer Plus1.5.1.14 Interrupt Distributor (Int Dist) RegistersThe Int Dist group describes the registers that the distributor provides. This register isavailable only with the MPCore.Table 1-17 Int Dist RegistersName Description TypeICDDCR ICDDCR Bit Assignments register read-writeN_ICDDCR ICDDCR Bit Assignments (Non-secure) register read-writeS_ICDDCR ICDDCR Bit Assignments (Secure) register read-writeICDICTR Interrupt Controller Type register read-onlyICDDIR Distributor Implementer Identification register read-onlyICDISR Interrupt Security registers read-writeICDISER Enable Set registers read-writeICDICER Enable Clear registers read-writeICDISPR Pending Set registers read-writeICDICPR Pending Clear registers read-writeICDABR Active Status registers read-onlyICDIPR Priority Level registers read-writeICDICR_CPUn_SGI Interrupt Configuration register SGI for CPUn read-writeICDICR_CPUn_PPI Interrupt Configuration register PPI for CPUn read-writeICDICR Interrupt Configuration registers SPI read-writePPI_Status PPI Status register read-onlySPI_Status SPI Status registers read-onlyPeriph_ID_[0-7] Peripheral Identification registers 0-7 read-onlyComponent_ID_[0-3] PrimeCell Identification registers 0-3 read-only1.5.1.15 VFP/Neon RegistersThe VFP/Neon group contains the floating point related registers. This register is availablewith both the UNICore and MPCore, but it is only present if the A9 was configured withan FPU or Neon coprocessor.Table 1-18 VFP/Neon RegistersName Description TypeFPSID Floating-point System ID Register. read-onlyMVFR0 Media and VFP Feature Register0. read-onlyMVFR1 Media and VFP Feature Register1. read-onlyFPEXC Floating-point Exception Register. read-writeFPSCR Floating-point Status and Control Register. read-writeCarbon Design Systems, Inc. Confidential

Debug Features 1-23Table 1-18 VFP/Neon Registers (Continued)Name Description TypeS0-S31S32-S63D0-D15D16-D31Q0-Q7Q8-Q15Advanced SIMD and VFP extension registers(Single word).Additional SIMD and VFP extension registers.Only present with Neon.Advanced SIMD and VFP extension registers(Double word).Additional SIMD and VFP extension registers(Double word). Only present with Neon.Advanced SIMD and VFP extension registers(Quad word).Additional SIMD and VFP extension registers(Quad word). Only present with Neon.read-writeread-writeread-writeread-writeread-writeread-write1.5.1.16 PLE RegistersThe PLE group contains system control registers for the Preload Engine. This group isavailable with the r2p2 revision of the UNICore and MPCore processors.Table 1-19 VFP/Neon RegistersName Description TypePLEIDR PLE ID Register Read onlyPLEASR PLE Activity Status Register Read onlyPLEFSR PLE FIFO Status Register Read onlyPLEUAR PLE User Accessibility Register Read/writePLEPCR PLE Parameters Control Register Read/writeCarbon Design Systems, Inc. Confidential

1-24 Using the Model Kit Component in SoC Designer Plus1.5.2 Run To Debug PointThe “run to debug point” feature has been added to enhance model debugging. The Cortex-A9processor is a dual issue out of order completion machine. This means that whilethe processor is running it does not present a coherent programmer’s view state; instructionsin the pipeline may be in different execution states.This feature forces the processor into a coherent state called “run to debug point”. Whendebugging with the ARM RealView Development Suite (RVDS), the model is brought tothe debug point automatically whenever a software breakpoint is hit (including singlestepping). However, if a hardware breakpoint is reached, or the system is advanced bycycles within SoC Designer Plus, the model can get to a non-debuggable state. In thisevent, the run to debug point will advance the processor to the debug state. It does this bystalling the instruction within the decode stage and allowing all earlier instructions to complete.Once that has been accomplished, the model will cause the system to stop simulating.The run to debug point is available as a context menu item (Run to Debuggable Point) forthe component within SoC Designer Simulator. It is also available in the disassemblerview.1.5.3 Memory InformationFigure 1-4 shows a Memory view of Cortex-A9 model.Figure 1-4 Cortex-A9 Memory ViewCarbon Design Systems, Inc. Confidential

Debug Features 1-251.5.4 Disassembly ViewFigure 1-5 shows the disassembly view of a program running on the Cortex-A9 model inSoC Designer Simulator. To display the disassembly view in the SoC Designer Simulator,right-click on the Cortex-A9 model and select View Disassembly… from the contextmenu.Figure 1-5 Cortex-A9 Disassembly WindowAll CADI windows support breakpoints – when double-clicking on the proper location ared dot will indicate that a breakpoint is currently active. To remove the breakpoints simplydouble-click on the same location again.Carbon Design Systems, Inc. Confidential

1-26 Using the Model Kit Component in SoC Designer Plus1.6 Available Profiling DataProfiling data is enabled, and can be viewed using the Profiling Manager, which is accessiblevia the Debug menu in the SoC Designer Simulator. Both hardware and softwarebased profiling is available.1.6.1 Hardware ProfilingHardware profiling includes several streams per processor core. The Cortex-A9 modelsets PMCR[4] to 1 to enable Hardware Profiling. This is done at reset time.Table 1-20 shows:• The event names supported by each stream, including event numbers as specified inthe ARM TRM.• The ARM silicon version for the Cortex A9 model.Table 1-20 Cortex-A9 Profiling EventsStream Event Name VersionsI-Cache Cache Miss (0x01) r1p1, r1p2, r2p0, r2p2D-Cache Cache Miss (0x03) r1p1, r1p2, r2p0, r2p2Cache Access (0x04)Data Read (0x06)Data Write (0x07)Data Eviction (0x65)Java Java Byte Code executed (0x40) r1p1, r1p2, r2p0, r2p2Software Java Byte Code executed (0x41)Jazelle backward branch executed (0x42)Memory STREX Passed (0x63) r1p1, r1p2, r2p0, r2p2STREX Failed (0x64)TLB Instr uTLB Miss (0x02) r1p1, r1p2, r2p0, r2p2Data uTLB Miss (0x05)Stall TLB Miss Stall (0x62) r1p1, r1p2, r2p0, r2p2DCache Miss Stall (0x61)ICache Miss Stall (0x60)PLD Stall (0x80)r2p0 and newerWrite Stall (0x81)Instruction Main TLB Miss Stall (0x82)Data Main TLB Miss Stall (0x83)Instruction uTLB Miss Stall (0x84)Data uTLB Miss Stall (0x85)DMB Stall (0x86)Carbon Design Systems, Inc. Confidential

Available Profiling Data 1-27Table 1-20 Cortex-A9 Profiling Events (Continued)Stream Event Name VersionsSoftware Decoded Instructions (0x68) r1p1, r1p2, r2p0, r2p2Exceptions Taken (0x09)Exceptions Returned (0x0A)Write Context ID (0x0B)Software change of PC (0x0C)Immediate Branch (0x0D)Predictable Function Returns (0x6E)Unaligned Access (0x0F)Mispredicted Branch (0x10)Predictable Branches (0x12)Coherent Line Fill Miss (0x50)Coherent Line Fill Hit (0x50)ISB (0x90)r1p1 and newerDSB (0x91)DMB (0x92)Issue does not dispatch any instruction(0x66)Issue is empty (0x67)Main Execution Unit Pipe (0x70)Second Execution Unit Pipe (0x71)Load/Store Pipe (0x72)FPU Instructions (0x73)Neon Instructions (0x74)Misc Integer core clock disabled (0x8A) r2p0 and newerData Engine clock disabled (0x8B)External interrupt (0x93)PLE Cache Line request completed (0xA0) r2p0 and newerCache Line request skipped (0xA1)FIFO Flush (0xA2)Request completed (0xA3)FIFO Overflow (0xA4)Request programmed (0xA5)Carbon Design Systems, Inc. Confidential

1-28 Using the Model Kit Component in SoC Designer PlusAn example of debug information for a software stream is shown below.Figure 1-6 Software Stream Debug Information1.6.2 Software ProfilingSoftware-based profiling is provided by SoC Designer Plus. Profiling information is alsoavailable in the SoC Designer Profiler. See the user guide for SoC Designer Plus or SoCDesigner Profiler for more information.Carbon Design Systems, Inc. Confidential