Carbon Cortex-A9 Model User Guide for SoC Designer

Debug Features 1-211.5.1.12 Timer/Watchdog RegistersThe Timer/Watchdog group contains registers for controlling the timer and watchdogblocks for each CPU. Addresses are relative to the base address of the timer and watchdogregion defined by the private memory map (see the ARM Cortex-A9 Technical ReferenceManual for more information).This register is available only with the MPCore.Table 1-15 Timer/Watchdog RegistersName Description TypeCPUn Timer Load Timer Load register read-writeCPUn Timer Counter Timer Counter register read-writeCPUn Timer Control Timer Control register read-writeCPUn Timer Status Timer Interrupt Status register read-writeCPUn Watchdog Load Watchdog Load register read-writeCPUn Watchdog Counter Watchdog Counter register read-writeCPUn Watchdog Control Watchdog Control register read-writeCPUn Watchdog Status Watchdog Interrupt Status register read-writeCPUn Watchdog Reset Watchdog Reset Status register read-write1.5.1.13 Processor Interface (Int IF) RegistersThe Int IF group contains the registers that each Cortex-A9 processor interface provides.This register is available only with the MPCore.Table 1-16 Int IF RegistersName Description TypeControlS Processor Interface Control Secure register read-writeControlNS Processor Interface Control Non-secure register read-writePrioMaskS Priority Mask Secure register read-writePrioMaskNS Priority Mask Non-secure register read-writeBinPointS Binary Point Secure register read-writeBinPointNS Binary Point Non-secure register read-writeIntAck Interrupt Acknowledge register read-onlyRunPrioS Running Priority Secure register read-onlyRunPrioNS Running Priority Non-secure register read-onlyHiPendInt Highest Pending Interrupt register read-onlyAliasNSBinPoint Aliased Non-secure Binary Point register read-writeID Processor Interface Implementer Identification register read-onlyCarbon Design Systems, Inc. Confidential