Carbon Cortex-A9 Model User Guide for SoC Designer

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1-6 Using the Model Kit Component in SoC Designer Plus1.3 Available Component ESL PortsACLKENSTable 1-2 describes the ESL ports that are exposed in SoC Designer Plus. Some ports mayor may not appear depending on whether you are using the multiprocessor or uniprocessorversion of the ARM hardware. See the ARM Cortex-A9 Technical Reference Manual orARM Cortex-A9 MPCore Technical Reference Manual for more information.Table 1-2 ESL Component PortsESL Port Description Direction TypeBus clock enable. By default it is set to 1 through a componentparameter. If another component is connectedthrough this port, it will override the default value. Availableonly with the MPCore.InputSignal slaveACLKENM[0,1] 1 Controls AXI ports. Available only with uniprocessor Input Signal slaveconfiguration.apb_dbg APB debug interface. Input APB Transactionslaveaxi_m0 AXI Master port 0. Output AXI Transactionmasteraxi_m1axi_sAXI Master port 1. Available only when a second masterhas been defined in the configuration file.AXI ACP (Accelerator Coherency Port) Slave port.Available only when it has been enabled in the configurationfile.OutputInputAXI TransactionmasterAXI TransactionslaveCFGSDISABLE 2 Disables write access to some system control processor Input Signal slaveregisters.clk_in Input clock. Input Clock slaveCP15SDISABLE Disabled write access to some system control processor Input Signal slaveregisters.DBGACK Debug acknowledge signal. (Used only with CoreSight). Output Signal masterDBGRESTARTED Used with DBGRESTART to move between Debug and Output Signal masterNormal state. (Used only with CoreSight).EDBGRQ External debug request. (Used only with CoreSight). Input Signal slaveEVENTIEvent input for Cortex-A9 processor wake-up from WFE Input Signal slavestate.EVENTOEvent output. This signal is active when one SEV instructionis executed.Output Signal masterextSemi There is an extSemi port per core in a multi-core A9,where is 0-3 to represent the core. In the single-processorversion, this port is simply extSemi0. Semihostingcan be enabled by connecting these ports to the SoCDesigner Plus semihost component contained in the CarbonSoC Designer Plus Standard Model Library (v3.0 orgreater).OutputTransaction masterCarbon Design Systems, Inc. Confidential
Available Component ESL Ports 1-7fiq 2Cortex-A9 processor private FIQ request input lines:0 = do not activate fast interrupt1 = activate fast interruptInputSignal slaveINCLKENM[0,1] 2 Controls bus speed of AXI ports. Input Signal slaveINTThis port connects to external interrupt signals. It can beany size between 0 and 224, in increments of 32. Thevalue must indicate the interrupt number [NumIRQ..0]and the *extValue must indicate whether the IRQ line isasserted (*extValue=1) or deasserted (*extValue=0).Input Signal slaveirq 1Cortex-A9 processor legacy IRQ request input lines:0 = do not activate interrupt1 = activate interruptInputSignal slavenCPureset 2 Active low reset, 4 bits wide. Input Signal slavenDBGRESET 2 Active low reset, 4 bits wide. Input Signal slavenNEONRESET 2 Active low reset, 4 bits wide. Available with Neon configurationsInput Signal slaveat version r2px only.nDERESET Active low reset, 4 bits wide. Available only with Neonconfurations at versions later than r2p0.Input Signal slavenPERIPHRESET 2nSCURESET 2nWDRESET 2Table 1-2 ESL Component Ports (Continued)ESL Port Description Direction TypeActive low reset, 1 bit wide. Available with MP configurationonly.Active low reset, 2 bit wide. Available with MP configurationonly.Active low reset, 4 bits wide. Available with MP configurationonly.InputInputInputSignal slaveSignal slaveSignal slaveOUTCLKENM[0,1] 2 Controls bus speed of AXI ports. Input Signal slavePERIPHCLK Clock for the timer and Interrupt Controller. Available Input Signal slavewith MP configuration only.PERIPHCLKEN Clock enable for the timer and Interrupt Controller. AvailableInput Signal slavewith MP configuration only.SMPnAMP Signals AMP or SMP mode for each Cortex-A9 MPCore Output Signal masterprocessor.STANDBYWFE Indicates if a Cortex-A9 processor is in WFE state. Output Signal masterSTANBYWFI Indicates that a Cortex-A9 processor is in Standby mode. Output Signal masterWDRESETREQ Watchdog reset request. Output Signal master1. Refer to the ARM Cortex-A9 Technical Reference Manual for details on driving these pins.2. For these interrupt ports, the active high/low setting is controlled by the negLogic component parameter. Thedefault is active high.All pins that are not listed in this table have been either tied or disconnected for performancereasons.Carbon Design Systems, Inc. Confidential
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