Carbon Cortex-A9 Model User Guide for SoC Designer

Debug Features 1-13• Secure World Registers• Cache Registers• Control Registers• Perf Registers• SCU Registers• Global Timer Registers• Timer/Watchdog Registers• Processor Interface (Int IF) Registers• Interrupt Distributor (Int Dist) Registers• VFP/Neon Registers• PLE RegistersSee the ARM Cortex-A9 MPCore Technical Reference Manual for detailed descriptions ofthese registers.Note:Registers are accurate only at debuggable points. While SoC Designer Plus graysout the register view when the processor is not at a debuggable point, values arestill visible. Due to the speculative nature of the processor pipeline, these valuesare not guaranteed to be accurate.1.5.1.1 Core RegistersIn general, you can write to a register only at a debuggable point. If a value isdeposited at any other point, it may not be correctly propagated.The Core group contains the ARM architectural registers. This register is available onlywith the MPCore.Table 1-4 Core RegistersName Description TypeR0 R0 register read-write 1R1 R1 register read-write 1R2 R2 register read-write 1R3 R3 register read-write 1R4 R4 register read-write 1R5 R5 register read-write 1R6 R6 register read-write 1R7 R7 register read-write 1R8 R8 register read-write 1R9 R9 register read-write 1R10 R10 register read-write 1Carbon Design Systems, Inc. Confidential