Carbon UART PL011 Model User Guide for SoC Designer

Carbon UART PL011 ModelUser Guide forSoC Designer PlusCarbon Model Version 4.2.2For the ARM PrimeCell® UART (PL011)Silicon Version: r1p4The Trusted Path to Accuracy The information contained in this document is confidential information of Carbon Design Systems, Inc.,and may not be duplicated or disclosed to unauthorized and/or third parties.

CopyrightCopyright © 2003-2013 Carbon Design Systems, Inc. All rights reserved.Files, documents or portions thereof presented on the Carbon Design Systems Internet server “Publication”, permits personsto view, copy, and print the Publication subject to the following conditions:• The Publication are to be kept strictly confidential• Copies of the Publication will not be distributed• Copies of the Publication must include the Carbon Design Systems copyright notice• Carbon Design Systems logos may only be used with Carbon's expressed written permission, including but not limitedto: linking through hyperlinks, electronic display, and print format.Disclaimer of WarrantyThis publication is provided “as is” without warranty of any kind, either expressed or implied, including, but not limitedto, the implied warranties of merchantability, fitness for a particular purpose, or non-infringement. Carbon Design Systemsassumes no responsibility for errors or omissions in this publication or other documents which are referenced by orlinked to this publication.References to corporations, their services and products, are provided “as is” without warranty of any kind, eitherexpressed or implied. In no event shall Carbon Design Systems be liable for any special, incidental, indirect or consequentialdamages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss ofuse, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or inconnection with the use or performance of this information.This publication may include technical or other inaccuracies or typographical errors. Carbon Design Systems may makeimprovements and/or changes in the product(s) and/or the program(s) described in this publication and in the publicationitself at any time.Trademarks© 2003-2013 Carbon Design Systems, Inc. All rights reserved. Carbon Design Systems, the Carbon Design Systemslogo, Carbon Model Studio, Replay, OnDemand, SoC Designer, Software Before Silicon, SOC-VSP, VSP, and TheAnswer to Validation are trademarks or registered trademarks of Carbon Design Systems, Incorporated in the UnitedStates and/or other countries.ARM, AMBA and RealView are registered trademarks of ARM Limited. AHB, APB and AXI are trademarks of ARMLimited. “ARM” is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiariesARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co.Ltd.; ARM Belgium N.V.; ARM Embedded Technologies Pvt. Ltd.; and ARM Physical IP, Inc.Microsoft, Windows 2000, and Windows XP are trademarks or registered trademarks of Microsoft Corporation in theUnited States and/or other countries.SystemC is a trademark of the Open SystemC Initiative.All other trademarks, registered trademarks, and products referenced herein are the property of their respective owners.Carbon Design Systems, Inc. Confidential

Technical SupportIf you have questions or problems concerning Carbon software, contact Technical Support.Phone Support Hours: Monday–Friday9:00 am–5:00 pm ESTCarbon Design Systems, Inc.125 Nagog ParkActon, MA 01720Voice: +1-978-264-7399Asia: +81-3-5524-1288Fax: +1-978-264-9990Email: support@carbondesignsystems.comWeb: www.carbondesignsystems.comVoice mail is available after hours. You may also access our on-line feedback form any time from the Support page ofthe Carbon web site.Document revised September 2013.

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ContentsPrefaceAbout This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Further reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 1.Using the Model Kit Component in SoC Designer PlusPL011 UART Model Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1Fully Functional and Accurate Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Fully Functional and Approximate Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Hardware Features not Implemented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3Features Additional to the Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4Differences from the ARM RVML Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5Adding and Configuring the SoC Designer Plus Component . . . . . . . . . . . . . . . . . . . . . . . .1-6Carbon SoC Designer Plus Component Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6Adding the Carbon Model to the Component Library . . . . . . . . . . . . . . . . . . . . . . . . . .1-7Adding the Component to the SoC Designer Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7Available Component ESL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8Setting Component Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-14Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-14Available Profiling Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-17Carbon Design Systems, Inc. Confidential

2 ContentsCarbon Design Systems, Inc. Confidential

PrefaceA Carbon Model component is a library developed from ARM intellectual property (IP)that is generated through Carbon Model Studio. The model then can be used within avirtual platform tool, for example, Carbon SoC Designer Plus.About This GuideThis guide provides all the information needed to configure and use the Carbon UARTPL011 Model in Carbon SoC Designer Plus.AudienceThis guide is intended for experienced hardware and software developers who create componentsfor use with Carbon SoC Designer Plus. You should be familiar with the followingproducts and technology:• Carbon SoC Designer Plus• Hardware design verification• Verilog or VHDL programming languageCarbon Design Systems, Inc. Confidential

Chapter 1Using the Model Kit Component inSoC Designer PlusThis chapter describes the functionality of the Model component, and how to use it in CarbonSoC Designer Plus. It contains the following sections:• PL011 UART Model Functionality• Adding and Configuring the SoC Designer Plus Component• Available Component ESL Ports• Setting Component Parameters• Debug Features• Available Profiling Data1.1 PL011 UART Model FunctionalityThe PrimeCell UART is an AMBA compliant System-on-Chip peripheral. The UART isan AMBA slave module that connects to the Advanced Peripheral Bus (APB). This modelsupports data transfer in both receive and transmit direction via a transaction port.This section provides a summary of the functionality of the model compared to that of thehardware, and the performance and accuracy of the model. For details of the functionalityof the hardware that the model simulates, refer to the ARM PrimeCell UART (PL011)Technical Reference Manual.• Fully Functional and Accurate Features• Fully Functional and Approximate Features• Hardware Features not Implemented• Features Additional to the Hardware• Differences from the ARM RVML ModelCarbon Design Systems, Inc. Confidential

PL011 UART Model Functionality 1-31.1.3 Hardware Features not ImplementedThe following features of the UART PL011 hardware are not implemented in the UARTPL011 model:• Standard asynchronous communication bits (start, stop, and parity) are not supported• False start bit detection is not supported• Line break generation and detection are not supported• Using different-frequency clocks for UARTCLK and clk-in is not supported• The modem control functions CTS, DCD, DSR, RTS, DTR, and RI are not supported• Programmable serial interface– data widths of 5, 6, 7, or 8 bits are not supported– even, odd, stick, or no-priority bit generation and diction are not supported– 1 or 2 stop bit generation is not supported• IrDA SIR ENDEC block is not supported.• Internal nominal clock frequency to generate low-power mode shorter bit duration isnot supported.• UARTMSINTR does not support changes on the RI, CTS, DCD, or DSR modem statuslines.• UARTEINTR – UART error interrupt does not support framing, parity, and breakerror interrupts.• The following registers are not available to be read / written via debug transactions —for example, in the SoC Designer Plus Registers window, or by accessing themdirectly from RealView Debugger:– Data register; UARTDR (bits 8:15)– Receive status/error clear register; UARTRSR/UARTECR (bits 0:2)– Flag register; UARTFR (bits 8, 0:3)– IrDA low-power counter register; UARTILPR (all bits)– Line control register; UARTLCR_H (bits 0:3, 5:7)– Control register; UARTCR (bits 1, 2, 10:15)– Interrupt mask set/clear register; UARTIMSC (bits 0:3, 7:9)– Raw interrupt status register; UARTRIS (bits 0:3, 7:9)– Masked interrupt status register; UARTMIS (bits 0:3, 7:9)– Interrupt clear register; UARTICR (bits 0:3, 7:9)– DMA control register; UARTDMACR (all bits)The functionality of these registers, however, does exist and can be accessed by softwarerunning on the virtual platform.Carbon Design Systems, Inc. Confidential

1-4 Using the Model Kit Component in SoC Designer Plus1.1.4 Features Additional to the HardwareThe following features are implemented in the UART PL011 model to enhance usability;they do not exist in the UART PL011 hardware:• Immediate UARTLCR register updates.According to the ARM PrimeCell® UART (PL011) Technical Reference Manual, thefollowing registers form a single 30-bit wide register (UARTLCR):– UARTLCR_H– UARTIBRD– UARTFBRDUARTLCR is updated on a single write strobe generated by a UARTLCR_H write.So, to internally update the contents of UARTIBRD or UARTFBRD, a UARTLCR_Hwrite must always be performed at the end.The Carbon model implements CADI access to these registers such that they do notrequire execution of a separate write to UARTLCR_H to internally update the contentsof the UARTLCR register.CADI access to the registers includes access via:– the View Registers window in SoC Designer Plus– CADI API access directly to the register (CADIRegWrite)– CADI API access via a memory mapped address (CADIMemWrite)All of these accesses update the appropriate bits of the 30-bit UARTLCR registerimmediately.In addition, a CADI write to UARTLCR_H also generates the "strobe generated by aUARTCR_H write" that is referred to in the TRM.The Carbon model implementation provides a convenient interface to the registerview in that if you write to one of these registers, that value is immediately storedinternally in the UARTLCR.• Rx/Tx FIFO-related pseudo registers display.You can view the Rx/Tx FIFO contents, size of FIFO, base pointer of FIFO and tippointer of FIFO in the “Transmit FIFO” and “Receive FIFO” register groups of theRegister Window. All of these registers are pseudo registers, for information only, andshould not be modified. Sixteen FIFO content registers are displayed.Carbon Design Systems, Inc. Confidential

PL011 UART Model Functionality 1-51.1.5 Differences from the ARM RVML ModelThe following differences exist between the Carbon Model and the older ARM®RealView® Model Library model.• The Direct Memory Access (DMA) ports are available: UARTTXDMASREQ,UARTTXDMABREQ, UARTTXDMACLR, UARTRXDMASREQ, UARTRXDMA-BREQ, and UARTRXDMACLR• The RXD and TXD ports are 1-bit, not 8-bit.• The reset port is not available on the component. The component reset ports have beenassociated with a reset generator. The reset is low for 15 cycles, then high for 10cycles.• The output from the UART, even when using Pseudo IO, is controlled by the baud ratethat you set. This is not the case for the RVML version, which set its own baud rate,independent of the baud rate set by the user when Pseudo IO was enabled.• The Debug registers DbgRemoveDataOnRead and MxDIRemoveDataOnRead are notsupported.• The following component parameters are not available in the Carbon Model: APBRegion Name, FIFO Depth, AutoStart Terminal, Flush input on enable, Mask,RxPeripNum, TxPeripNum, Wait States.Carbon Design Systems, Inc. Confidential

Adding and Configuring the SoC Designer Plus Component 1-71.2.2 Adding the Carbon Model to the Component LibraryThe compiled Carbon Model component is provided as a configuration file (.conf). Tomake the component available in the Component Window in SoC Designer Canvas, performthe following steps:1. Launch SoC Designer Canvas.2. From the File menu, select Preferences.3. Click on Component Library in the list on the left.4. Under the Additional Component Configuration Files window, click Add.5. Browse to the location where the SoC Designer Plus model is located and select thecomponent configuration file:– maxlib.lib.conf (for Linux)– maxlib.lib.windows.conf (for Windows)6. Click OK.7. To save the preferences permanently, click the OK & Save button.The component is now available from the SoC Designer Plus Component Window.1.2.3 Adding the Component to the SoC Designer CanvasLocate the component in the Component Window and drag it out to the Canvas. It willappear as shown in Figure 1-1.Figure 1-1 PrimeCell UART (PL011) Component in SoC Designer PlusCarbon Design Systems, Inc. Confidential

1-8 Using the Model Kit Component in SoC Designer Plus1.3 Available Component ESL PortsTable 1-2 describes the ESL ports that are exposed in SoC Designer Plus Plus. See theARM PrimeCell® UART (PL011) Technical Reference Manual for more information.Table 1-2 ESL Component PortsESL Port Description Direction TypePRESETn Bus reset signal, active LOW. Input Reset controllerRXD1-bit port for receiving data from signal master Input Signal Slaveport. The data received via this port is pushedinto Rx FIFO UART.UARTCLKClock input for UART.Input Clock SlaveNote: This clock input must be connected to thesame clock that is used for clk-in. If clkinis left unconnected then this clockinput must also be unconnected.UARTRXDMACLR Receive DMA Clear Input Signal SlaveUARTTXDMACLR Transmit DMA Clear Input Signal SlaveapbAllows the user to program the memory-mappedregisters. This interface is expected to be connectedto an APB-compliant device. This interfaceis clocked by the clk-in port.Input TransactionSlavenUARTRSTclk-inTXDUART reset signal to UARTCLK clock domain,active LOW.The reset controller must use PRESETn to assertnUARTRST asynchronously but negate it synchronouslywith UARTCLK.Input clock port. This component and the APBport are clocked at the frequency of the clockconnected to this port. If the clk-in port is notconnected, clock frequency is taken from SoCDesigner Plus System Properties.Note: This clock input must be connected to thesame clock that is used for UARTCLK, or ifUARTCLK is unconnected then clk-in must alsobe unconnected.1-bit port for transmitting data to connected signalslave port. The data transmitted via this portis popped out of Tx FIFO of UART.InputInputOutputReset TransactorClock SlaveSignal MasterUARTRXDMABREQ Receive DMA Burst Request Output Signal MasterUARTRXDMASREQ Receive DMA Single Request Output Signal MasterUARTTXDMABREQ Transmit DMA Burst Request Output Signal MasterUARTTXDMASREQ Transmit DMA Single Request Output Signal MasterCarbon Design Systems, Inc. Confidential

Available Component ESL Ports 1-9Table 1-2 ESL Component Ports (Continued)ESL Port Description Direction TypeintpProvides interrupts to the interrupt controller.The value contains the interrupt number andextended value (interrupt low or high). You canspecify unique interrupt numbers for each interruptsupported via parameters – see Table 1-3on page 1-10 for more details.OutputInterrupt MasternSIROUTTransmitted Serial Data Output, active LOW. Inthe idle state, this signal remains LOW (themarking state).OutputSignal MasterWhen this signal is HIGH, an infrared light pulseis generated that represents a logic 0 (spacingstate).nUARTDTRData Terminal Ready modem status output,active LOW. The reset value is 0.OutputSignal MasternUARTRTSRequest to Send modem status output, activeLOW. The reset value is 0.OutputSignal MasternUARTOut1Out1 modem status output, active LOW. Thereset value is 0.OutputSignal MasternUARTOut2Out2 modem status output, active LOW. Thereset value is 0.OutputSignal MasterAll pins that are not listed in this table have been either tied or disconnected for performancereasons.Carbon Design Systems, Inc. Confidential

1-10 Using the Model Kit Component in SoC Designer Plus1.4 Setting Component ParametersYou can change the settings of all the component parameters in SoC Designer Canvas, andof some of the parameters in SoC Designer Simulator. To modify the Carbon component’sparameters:1. In the Canvas, right-click on the Carbon component and select Edit Parameters....You can also double-click the component. The Edit Parameters dialog box appears.Figure 1-2 Component Parameters Dialog Box2. In the Parameters window, double-click the Value field of the parameter that youwant to modify.3. If it is a text field, type a new value in the Value field. If a menu choice is offered,select the desired option. The parameters are described in Table 1-3.Table 1-3 Component ParametersName Description Allowed Values Default Value Runtime 1Align Waveformsapb Base AddressWhen set to true, waveforms dumpedfrom the Carbon component are alignedwith the SoC Designer Plus simulationtime. The reset sequence, however, is notincluded in the dumped data.When set to false, the reset sequence isdumped to the waveform data, however,the Carbon component time is notaligned with the SoC Designer Plustime.Base address for APB region accessedvia APB slave port of UART.true, false true No0x00000000 -0xFFFFFFFF0x0NoCarbon Design Systems, Inc. Confidential

Setting Component Parameters 1-11apb EnableDebug MessagesEnable or disable debug messages. true, false false Yesapb Size Address range size. 0x00000000 -0xFFFFFFFFCarbon DB PathClone Output toConsole?Dump WaveformsEnable DebugMessagesintp int_1 idintp int_2 idintp int_3 idintp int_4 idintp int_5 idintp int_6 idTable 1-3 Component Parameters (Continued)Name Description Allowed Values Default Value Runtime 1Sets the directory path to the Carbondatabase file.The output of TXD port or file or Socketis also displayed on SoC Designer Plusconsole window.Whether SoC Designer Plus dumpswaveforms for this component.0x10000000NoNot Used empty Notrue, false false Notrue, false false YesEnable or disable debug messages. true, false false YesThe Intr value. It is the combined interruptof Rx_int, Tx_int, Receive timeoutinterrupt, and Overflow error interrupt.Always comes on “Intp” signal masterport after the individual interrupt hascome. Both come in same simulationcycle. Associated with UARTINTR.The Rx_int number. Rx FIFO tide interruptnumber. Associated with UARTRX-INTR.The Tx_int number. Tx FIFO tide interruptnumber. Associated with UARTTX-INTR.The Receive Timeout Interrupt Number.Interrupt number for receive timeoutinterrupt. Associated with UAR-TRTINTR.The Overflow Error Interrupt Number.Interrupt number for overflow error –which could occur on Rx FIFO. Associatedwith UARTEINTR.Interrupt controller UART modem statusinterrupt. Associated with UARTM-SINTR.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.1 Yes2 Yes3 Yes4 Yes5 Yes6 YesCarbon Design Systems, Inc. Confidential

1-12 Using the Model Kit Component in SoC Designer PlusIPFileNameOPFileNamePseudo I/O? 3Raw SocketData? 3TCP SocketNumber 4Use ExternalLoopback?Use Sockets? 3Input file name with path to be used forreceiving data. This file name takeseffect only when Pseudo I/O? is true andUseSockets? is false (see Table 1-4).Output file name with path which will beused to transmit data to. This file namecomes into effect only when Pseudo I/O?is true and UseSockets is false.Used to specify that RXD/TXD portswill not be used for receive or transmit.Instead either File IO for Socket IO willbe used.When set to true, Telnet terminal willnot automatically open. Instead the userneeds to create a server or a client tosend data to UART or receive data fromUART.TCP port number to use for Socket IO.Note: When using multiple instances ofthe PL011 model, each model’s TCPPort Number must be unique. DuplicateTCP port numbers result in data contentionand errors such as “Couldn’t initializesocket.”Used to loop back data from transmit toreceive of the same UART. File, Socket,or RXD/TXD ports are not used whenset to true.When both Use Sockets? = true andPseudo I/O? = true — Socket IO is usedfor Rx/Tx.When false — File IO is used for Rx/Tx.Any valid filename present inhost OS with pathabsolute pathAny valid filename present inhost OS with pathabsolute pathINPUTFILEOUTPUTFILENoNotrue, false true Notrue, false false No0x400 - 0xFFFF 0 Notrue, false false Notrue, false false NoWaveform File 5 Name of the waveform file. string pl011.fsdb NoWaveform The format of the waveform dump file. VCD, FSDB VCD NoFormatWaveformTimescaleTable 1-3 Component Parameters (Continued)Name Description Allowed Values Default Value Runtime 1Sets the timescale to be used in thewaveform.Many values indrop-down1 ns No1. Yes means the parameter can be dynamically changed during simulation, No means it can be changed onlywhen building the system, Reset means it can be changed during simulation, but its new value will be takeninto account only at the next reset.2. Range depends on the number of interrupts of the destination component.3. See Table 1-4 for information about how this parameter interacts with others.4. At its default setting (0), the model automatically selects an available TCP port.Carbon Design Systems, Inc. Confidential

1-14 Using the Model Kit Component in SoC Designer Plus1.5 Debug FeaturesThe UART PL011 model has a debug interface (CADI) that allows the user to view,manipulate, and control the registers of UART. The views shown in this section are for theSoC Designer Simulator.Figure 1-3 Registers View1.5.1 Register InformationThis section lists the register views available for the UART PL011 model in the SoCDesigner Simulator. The available groups are:• General Registers• Peripheral ID Registers• Primecell ID Registers• Transmit FIFO Registers• Receive FIFO RegistersSee the ARM PrimeCell UART (PL011) Technical Reference Manual for detailed descriptionsof these registers.Note:The contents of the “Transmit FIFO” and “Receive FIFO” Register tabs arepseudo registers and are for information only - they should not be modified.Carbon Design Systems, Inc. Confidential

Debug Features 1-151.5.1.1 General RegistersTable 1-5 shows the General registers.Table 1-5 General Registers SummaryBase Offset Name Description Type Reset Value0x00 UARTDR Data Register RW 0x00000x04UARTRSR_ Receive Status Register/Error Clear RW 0x00000000UARTECR Register0x18 UARTFR Flag Register RO 0x1970x20 UARTILPR IrDA Low-Power Counter Register RW 0x000x24 UARTIBRD Integer Baud Rate Register RW 0x000000000x28 UARTFBRD Fractional Baud Rate Register RW 0x000x2C UARTLCR_H Line Control Register RW 0x000x30 UARTCR 1 Control Register RW 0x03000x34 UARTIFLS Interrupt FIFO Level Select Register RW 0x120x38 UARTIMSC Interrupt Mask Set/Clear Register RW 0x0000x3C UARTRIS Raw Interrupt Status Register RO 0x0000x40 UARTMIS Masked Interrupt Status Register RO 0x0000x44 UARTICR Interrupt Clear Register WO 0x0000x48 UARTDMACR DMA Control Register RW 0x01. If you set the UART control register to Receive Enable, and the Pseudo I/O? parameter is set to True,the UARTCR register setting does not take effect. This approach prevents data contention to theUART FIFO memory buffers.1.5.1.2 Peripheral ID RegistersTable 1-6 shows the Peripheral ID registers.Table 1-6 Peripheral ID Registers SummaryBase Offset Name Description Type Reset Value0xFE0 UARTPeriphID0 UARTPeriphID0 Register. Always setto reset value.0xFE4 UARTPeriphID1 UARTPeriphID1 Register. Always setto reset value.0xFE8 UARTPeriphID2 UARTPeriphID2 Register. Always setto reset value.0xFEC UARTPeriphID3 UARTPeriphID3 Register. Always setto reset value.RO 0x0011RO 0x0010RO 0x00_4 1RO 0x00001. The value depends on the revision of the UART. For version r1p4 the value is 2, e.g. 0x24. For versionr1p5 the value is 3, e.g. 0x34. See the TRM for more information.Carbon Design Systems, Inc. Confidential

1-16 Using the Model Kit Component in SoC Designer Plus1.5.1.3 Primecell ID RegistersTable 1-7 shows the Primecell ID registers.Table 1-7 Primecell ID Registers SummaryBase Offset Name Description Type Reset Value0xFF0 UARTPCellID0 UARTPCellID0 Register. Always setto reset value.0xFF4 UARTOCellID1 UARTPCellID1 Register. Always setto reset value.0xFF8 UARTPCellID2 UARTPCellID2 Register. Always setto reset value.0xFFC UARTPCellID3 UARTPCellID3 Register. Always setto reset value.RORORORO0x000d0x00f00x00050x00b11.5.1.4 Transmit FIFO RegistersTable 1-8 shows the Transmit FIFO registersTable 1-8 Transmit FIFO Registers SummaryName Description TypeTxFIFOTip Register being transferred ROTxFIFOBase Last register written ROTxFIFOSize Difference between Tip and Base ROTxFIFOElement0-15 Transmit FIFOs RO1.5.1.5 Receive FIFO RegistersTable 1-9 shows the Receive FIFO registersTable 1-9 Receive FIFO Registers SummaryName Description TypeRxFIFOTip Register being received RORxFIFOBase Last register read RORxFIFOSize Difference between Tip and Base RORxFIFOElement0-15 Receive FIFOs ROCarbon Design Systems, Inc. Confidential

Available Profiling Data 1-171.6 Available Profiling DataThe UART PL011 component has no profiling capabilities.Carbon Design Systems, Inc. Confidential

1-18 Using the Model Kit Component in SoC Designer PlusCarbon Design Systems, Inc. Confidential