Carbon Cortex-A15 Model User Guide for SoC Designer

Carbon Cortex-A15 ModelUser Guide forSoC Designer PlusCarbon Model Version 5.1.7For the ARM® Cortex-A15 MPCore ProcessorSilicon Version: r2p3, r3p1The Trusted Path to Accuracy The information contained in this document is confidential information of Carbon Design Systems, Inc.,and may not be duplicated or disclosed to unauthorized and/or third parties.

CopyrightCopyright © 2012, 2014 Carbon Design Systems, Inc. All rights reserved.Files, documents or portions thereof presented on the Carbon Design Systems Internet server “Publication”, permits personsto view, copy, and print the Publication subject to the following conditions:• The Publication are to be kept strictly confidential• Copies of the Publication will not be distributed• Copies of the Publication must include the Carbon Design Systems copyright notice• Carbon Design Systems logos may only be used with Carbon's expressed written permission, including but not limitedto: linking through hyperlinks, electronic display, and print format.Disclaimer of WarrantyThis publication is provided “as is” without warranty of any kind, either expressed or implied, including, but not limitedto, the implied warranties of merchantability, fitness for a particular purpose, or non-infringement. Carbon Design Systemsassumes no responsibility for errors or omissions in this publication or other documents which are referenced by orlinked to this publication.References to corporations, their services and products, are provided “as is” without warranty of any kind, eitherexpressed or implied. In no event shall Carbon Design Systems be liable for any special, incidental, indirect or consequentialdamages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss ofuse, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or inconnection with the use or performance of this information.This publication may include technical or other inaccuracies or typographical errors. Carbon Design Systems may makeimprovements and/or changes in the product(s) and/or the program(s) described in this publication and in the publicationitself at any time.Trademarks© 2014 Carbon Design Systems, Inc. All rights reserved. Carbon Design Systems, the Carbon Design Systems logo,Carbon Model Studio, Replay, OnDemand, SoC Designer, Software Before Silicon, SOC-VSP, Swap & Play, VSP, TheAnswer to Validation, and The Trusted Path to Accuracy are trademarks or registered trademarks of Carbon Design Systems,Incorporated in the United States and/or other countries.ARM, AMBA and RealView are registered trademarks of ARM Limited. AHB, APB and AXI are trademarks of ARMLimited. “ARM” is used to represent ARM Holdings plc; its operating company ARM Limited; and the regional subsidiariesARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co.Ltd.; ARM Belgium N.V.; ARM Embedded Technologies Pvt. Ltd.; and ARM Physical IP, Inc.Microsoft, Windows 2000, and Windows XP are trademarks or registered trademarks of Microsoft Corporation in theUnited States and/or other countries.SystemC is a trademark of the Open SystemC Initiative.All other trademarks, registered trademarks, and products referenced herein are the property of their respective owners.Carbon Design Systems, Inc. Confidential

Technical SupportIf you have questions or problems concerning Carbon software, contact Technical Support.Phone Support Hours: Monday–Friday9:00 am–5:00 pm ESTCarbon Design Systems, Inc.125 Nagog ParkActon, MA 01720Voice: +1-978-264-7399Asia: +81-3-5524-1288Fax: +1-978-264-9990Email: support@carbondesignsystems.comWeb: www.carbondesignsystems.comVoice mail is available after hours. You may also access our on-line feedback form any time from the Support page ofthe Carbon web site.Document updated April 2014.

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Contents 1ContentsPrefaceAbout This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Further reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Chapter 1.Using the Model Kit Component in SoC Designer PlusCortex-A15 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1Implemented Hardware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Hardware Features not Implemented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2Features Additional to the Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4Adding and Configuring the SoC Designer Plus Component . . . . . . . . . . . . . . . . . . . . . . . .1-5Carbon SoC Designer Plus Component Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5Adding the Carbon Model to the Component Library . . . . . . . . . . . . . . . . . . . . . . . . . .1-6Adding the Component to the SoC Designer Canvas . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6Available Component ESL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6Setting Component Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14Secure World Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18Normal World Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19VA to PA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19Perf Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21Thumb-EE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22Jazelle Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23VFP/Neon Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23VGIC Physical CPU Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24VGIC Distributor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25VGIC VCPU Virtual Machine view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25VGIC VCPU Hypervisor view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26Run To Debug Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-27Carbon Design Systems, Inc. Confidential

2 ContentsMemory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-27Disassembly View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-27Available Profiling Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-28Hardware Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-28Software Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-35Carbon Design Systems, Inc. Confidential

PrefaceA Carbon Model component is a library developed from ARM intellectual property (IP)that is generated through Carbon Model Studio. The model then can be used within avirtual platform tool, for example, Carbon SoC Designer Plus.About This GuideThis guide provides all the information needed to configure and use the Carbon Cortex-A15 multi-processor model in Carbon SoC Designer Plus.AudienceThis guide is intended for experienced hardware and software developers who create componentsfor use with Carbon SoC Designer Plus. You should be familiar with the followingproducts and technology:• Carbon SoC Designer Plus• Hardware design verification• Verilog or VHDL programming languageCarbon Design Systems, Inc. Confidential

4 PrefaceConventionsThis guide uses the following conventions:Convention Description ExamplecourieritalicboldCommands, functions,variables, routines, andcode examples that are setapart from ordinary text.New or unusual words orphrases appearing for thefirst time.Action that the user performs.Values that you fill in, orthat the system automaticallysupplies.[ text ] Square brackets [ ] indicateoptional text.[ text1 | text2 ] The vertical bar | indicates“OR,” meaning that youcan supply text1 or text 2.sparseMem_t SparseMemCreate-New();Transactors provide the entry and exitpoints for data ...Click Close to close the dialog./ represents the name ofvarious platforms.$CARBON_HOME/bin/modelstudio[ ]$CARBON_HOME/bin/modelstudio[.symtab.db |.ccfg ]Also note the following references:• References to C code implicitly apply to C++ as well.• File names ending in .cc, .cpp, or .cxx indicate a C++ source file.Carbon Design Systems, Inc. Confidential

Preface 5Further readingThis section lists related publications by Carbon and by third parties.Carbon Model Studio DocumentationThe following publications provide information that relate directly to Model Studio:• Carbon Model Studio Installation Guide• Carbon Model Studio User Manual• Carbon Transactors OverviewCarbon SoC Designer Plus DocumentationThe following publication provides information that relates directly to SoC Designer Plus:• Carbon SoC Designer Plus User GuideExternal publicationsThe following publications provide reference information about ARM® products:• Cortex-A15 Technical Reference Manual• AMBA AXI Protocol V2 Specification• Large Physical Address Extensions Specification (ARM Architecture Group)See http://infocenter.arm.com/help/index.jsp for access to ARM documentation.The following publications provide additional information on simulation:• IEEE 1666 SystemC Language Reference Manual, (IEEE Standards Association)• SPIRIT User Guide, Revision 1.2, SPIRIT Consortium.Carbon Design Systems, Inc. Confidential

6 PrefaceGlossaryAMBAAHBAPBAXICarbon ModelCarbon ModelStudioCASICADICAPIComponentESLHDLRTLSoC DesignerSystemCTransactorAdvanced Microcontroller Bus Architecture. The ARM open standard on-chipbus specification that describes a strategy for the interconnection and managementof functional blocks that make up a System-on-Chip (SoC).Advanced High-performance Bus. A bus protocol with a fixed pipelinebetween address/control and data phases. It only supports a subset of the functionalityprovided by the AMBA AXI protocol.Advanced Peripheral Bus. A simpler bus protocol than AXI and AHB. It isdesigned for use with ancillary or general-purpose peripherals such as timers,interrupt controllers, UARTs, and I/O ports.Advanced eXtensible Interface. A bus protocol that is targeted at high performance,high clock frequency system designs and includes a number of featuresthat make it very suitable for high speed sub-micron interconnect.A software object created by the Carbon Model Studio (or Carbon compiler)from an RTL design. The Carbon Model contains a cycle- and register-accuratemodel of the hardware design.Carbon’s graphical tool for generating, validating, and executing hardwareaccuratesoftware models. It creates a Carbon Model, and it also takes a CarbonModel as input and generates a Carbon component that can be used inSoC Designer Plus, Platform Architect, or OSCI SystemC for simulation.ESL API Simulation Interface, is based on the SystemC communicationlibrary and manages the interconnection of components and communicationbetween components.ESL API Debug Interface, enables reading and writing memory and registervalues and also provides the interface to external debuggers.ESL API Profiling Interface, enables collecting historical data from a componentand displaying the results in various formats.Building blocks used to create simulated systems. Components are connectedtogether with unidirectional transaction-level or signal-level connections.Electronic System Level. A type of design and verification methodology thatmodels the behavior of an entire system using a high-level language such as Cor C++.Hardware Description Language. A language for formal description of electroniccircuits, for example, Verilog or VHDL.Register Transfer Level. A high-level hardware description language (HDL)for defining digital circuits.The full name is Carbon SoC Designer Plus. A high-performance, cycle accuratesimulation framework which is targeted at System-on-a-Chip hardwareand software debug as well as architectural exploration.SystemC is a single, unified design and verification language that enables verificationat the system level, independent of any detailed hardware and softwareimplementation, as well as enabling co-verification with RTL design.Transaction adaptors. You add transactors to your Carbon component to connectyour component directly to transaction level interface ports for your particularplatform.Carbon Design Systems, Inc. Confidential

Chapter 1Using the Model Kit Component inSoC Designer PlusThis chapter describes the functionality of the Model component, and how to use it inCarbon SoC Designer Plus. It contains the following sections:• Cortex-A15 Functionality• Adding and Configuring the SoC Designer Plus Component• Available Component ESL Ports• Setting Component Parameters• Debug Features• Available Profiling Data1.1 Cortex-A15 FunctionalityIn the multiprocessor configuration, up to four Cortex-A15 processors are available in acache-coherent cluster, under the control of a Snoop Control Unit (SCU), that maintainsL1 data cache coherency.The Cortex-A15 multiprocessor has:• up to four Cortex-A15 processors.• an SCU responsible for maintaining coherency among caches.• an optional Interrupt Controller (IC) with support for legacy ARM interrupts.• a generic 64-bit timer per processor.• support for AMBA 4.0 AXI Coherency Extension (ACE) master port and an AcceleratorCoherency Port (ACP) slave port configurable to 64-bit or 128-bits.• optional NEON and VFP units.• support for Virtualization Extensions for the development of virtualized systems thatenable the switching of guest operating systems.• support for Large Physical Address (LPA) Extension for address translation of up to40 bits physical addresses.Carbon Design Systems, Inc. Confidential

1-2 Using the Model Kit Component in SoC Designer PlusThis section provides a summary of the functionality of the model compared to that of thehardware, and the performance and accuracy of the model.• Implemented Hardware Features• Hardware Features not Implemented• Features Additional to the Hardware1.1.1 Implemented Hardware FeaturesMost hardware features have been implemented. Some functionality and register pin differencesare listed in the next section.Note that when using semihosting you must use the semihost component from Carbon.This “CarbonSemihost” component is included in the Carbon SoC Designer Plus StandardModel Library, version 3.0 or greater. The ARM RVML semihost component will notwork with the Carbon Model.See the ARM Cortex-A15 Technical Reference Manual for more information.1.1.2 Hardware Features not ImplementedThe following features of the Cortex-A15 hardware are not implemented in the Carbonizedmodel:• Debug access to virtual memory does not currently handle TLB lockdown.• Debug transactions do not fully support cache coherence. This means that the debugtransaction could read or write data without realizing that it is accessing data thatresides in the other cores’ caches. Debug transactions are needed by RVD accesses tomemory, as well as by semihosting. If you see a different memory value from RVDthan what you see by opening the Memory view in the processor and memory, thenyour design may have encountered this limitation.• Some registers are read-only. See the section “Register Information” on page 1-12 formore information.• The registers in Table 1-1 on page 1-3 are not available to be read/written via debugtransactions — for example, in the SoC Designer Plus Registers window, or byaccessing them directly from RealView Debugger.The functionality of these registers, however, does exist and can be accessed by softwarerunning on the virtual platform.Carbon Design Systems, Inc. Confidential

Cortex-A15 Functionality 1-3Table 1-1 Unavailable RegistersGroupRegister(s)ControlVA to PACache OpsTLBIMVAHTLBIMVAHISTLBIALLHTLBIALLHISTLBIALLNSNHTLBIALLNSNHISRAMINDEXATS1CPRATS1CPWATS1CPWATS1CPWATS1CUWATS12NSOPRATS12NSOPWATS12NSOURATS12NSOUWATS1HRATS1HWICIALLUISBPIALLISICIALLUICIMVAUCP15ISBBPIALLBPIMVADCIMVACDCISWDCCMVACDCCSWCP15DSBCP15DMBDCCMVAUDCCIMVACDCCISWCarbon Design Systems, Inc. Confidential

1-4 Using the Model Kit Component in SoC Designer PlusTable 1-1 Unavailable Registers (Continued)GroupRegister(s)TLBDebugVGIC VCPU Virtual machine viewVGIC Physical CPU InterfaceVGIC DistributorTLBIALLISTLBIMVAISTLBIASIDISTLBIMVAAISITLBIALLITLBIMVAITLBIASIDDTLBIALLDTLBIMVADTLBIASIDTLBIALLTLBIMVATLBIASIDTLBIMVAADBGDRCRDBGOSLARDBGLARGICV_EOIRGICV_AEOIRGICV_DIRGICC_EOIRGICC_AEOIRGICC_DIRGICC_BPR_NGICD_SGIR1.1.3 Features Additional to the HardwareThe following features that are implemented in the Cortex-A15 model do not exist in theCortex-A15 hardware. These features have been added to the model for enhanced usability.• The component supports positive- and negative-level irq, virq, fiq, and vfiq signals.This is configurable using the negLogic parameter (see Table 1-4 on page 1-9).• The “run to debug point” feature has been added. This feature forces the debugger toadvance the processor to the debug state instead of having the model get into a nondebuggablestate. See “Run To Debug Point” on page 1-27 for more information.Carbon Design Systems, Inc. Confidential

Adding and Configuring the SoC Designer Plus Component 1-51.2 Adding and Configuring the SoC Designer Plus ComponentThe Carbon SoC Designer Plus User Guide describes how to use the component. See thatguide for more information.• Carbon SoC Designer Plus Component Files• Adding the Carbon Model to the Component Library• Adding the Component to the SoC Designer Canvas1.2.1 Carbon SoC Designer Plus Component FilesThe component files are the final output from the Carbon Model Studio compile and arethe input to SoC Designer Plus. There are two versions of the component; an optimizedrelease version for normal operation, and a debug version.On Linux, the debug version of the component is compiled without optimizations andincludes debug symbols for use with gdb. The release version is compiled without debuginformation and is optimized for performance.On Windows, the debug version of the component is compiled referencing the debug runtimelibraries so it can be linked with the debug version of SoC Designer Plus. The releaseversion is compiled referencing the release runtime library. Both release and debug versionsgenerate debug symbols for use with the Visual C++ debugger on Windows.The provided component files are listed in Table 1-2 below:Table 1-2 Carbon SoC Designer Plus Component FilesPlatform File DescriptionLinuxWindowsmaxlib.lib.conflib.mx.solib.mx_DBG.somaxlib.lib.windows.conflib.mx.dlllib.mx_DBG.dllSoC Designer Plus configuration fileSoC Designer Plus component runtime fileSoC Designer Plus component debug fileSoC Designer Plus configuration fileSoC Designer Plus component runtime fileSoC Designer Plus component debug fileAdditionally, this User Guide PDF file and a ReadMe text file are provided with the component.Carbon Design Systems, Inc. Confidential

1-6 Using the Model Kit Component in SoC Designer Plus1.2.2 Adding the Carbon Model to the Component LibraryThe compiled Carbon Model component is provided as a configuration file (.conf). Tomake the component available in the Component Window in SoC Designer Canvas, useSoC Designer Canvas.For more information on SoC Designer Canvas, see the Carbon SoC Designer Plus UserGuide.1.2.3 Adding the Component to the SoC Designer CanvasLocate the component in the Component Window and drag it out to the Canvas. Dependingon your configuration, ports may differ from those listed in Table 1-3 (see “AvailableComponent ESL Ports” on page 1-6).1.3 Available Component ESL PortsTable 1-3 describes the ESL ports that are exposed in SoC Designer Plus. See the ARMCortex-A15 Technical Reference Manual for more information.Table 1-3 ESL Component PortsESL Port Description Direction Typeaxi_m ACE Master S2T. Output TransactorMasteracp AXI Slave T2S. Input TransactorSlaveapb_dbg APB3 Slave T2S. Input TransactorSlavefiq 1irq 1vfiq 1virq 1INTFIQ Interrupt Port. Size is 1 to 4 depending on the numberof CPUs.IRQ Interrupt Port.Size is 1 to 4 depending on the numberof CPUs.Virtual FIQ Interrupt Port. Size is 1 to 4 depending on thenumber of CPUs.Virtual IRQ Interrupt Port. Size is 1 to 4 depending on thenumber of CPUs.The ARM RTL IRQS port, which connects to the Carboninterrupt transactor. Connect to the INT port via theintVector component.INT can be any size between 0 and 224, in increments of32. The value must indicate the interrupt number[NumIRQ..0] and the *extValue must indicate whetherthe IRQ line is asserted (*extValue=1) or deasserted(*extValue=0).InputInputInputInputInputSignal SlaveSignal SlaveSignal SlaveSignal SlaveSignal SlaveCP15SDISABLE Disables write access to CP15 registers. Input Signal SlaveCFGSDISABLE Disables write access to secure IC registers. Input Signal SlaveEVENTI Event Input. Input Signal SlaveCarbon Design Systems, Inc. Confidential

Available Component ESL Ports 1-7Table 1-3 ESL Component Ports (Continued)ESL Port Description Direction TypeEVENTO Event Output. Output Signal MasterSTANDBYWFE Indicates the core is in the WFE State. Output Signal MasterSTANDBYWFI Indicates the core is in the WFI State. Output Signal MasterSTANDBYWFIL2 Indicates the L2 Cache is in the WFI State. Output Signal MasterACLKENM ACE Master Bus clock enable. Input Signal SlaveACLKENS ACP Bus clock enable. Input Signal SlaveACLKEN ACE Bus clock enable. Input Signal SlavePCLKENDBG apb_dbg Bus clock enable. Input Signal SlavenCPUPORESET CPU Power On Reset. Input Signal SlavenCORERESET CPU Reset (excluding DBG & PTM). Input Signal SlavenCXRESET Neon/VFP reset. Input Signal SlavenDBGRESET Debug Reset. Input Signal SlavenL2RESET L2 Reset. Input Signal SlavenPRESETDBG APB reset Input Signal SlaveextSemi Semihost Port. 1 to 4 ports for multiprocessor. Output TransactionMasternINTERRIRQ Internal L2 error. Output Signal MasternAXIERRIRQ Internal L2 error. Output Signal Masterfiqout 2 Output of individual processor fiq from the GIC. Output Signal Masterirqout 2 Output of individual processor irq from the GIC. Output Signal Mastercnthpirq 2 Hypervisor physical timer event. Output Signal Mastercntpnsirq 2 Non-secure physical timer event. Output Signal Mastercntpsirq 2 Secure physical timer event. Output Signal Mastercntvirq 2 Virtual timer event. Output Signal MasterCNTVALUEB Global system counter value in binary format. Input Signal SlaveACINACTM Snoop interface is inactive and no longer accepting Input Signal Slaverequests.AINACTS AXI slave inactive and no longer accepting requests. Input Signal SlavepmuirqPMU interrupt signal. Size is based on the number of configuredcores.Output Signal MasterCarbon Design Systems, Inc. Confidential

1-8 Using the Model Kit Component in SoC Designer PlusTable 1-3 ESL Component Ports (Continued)ESL Port Description Direction TypePMUEVENTn PMU event bus where n is the core number (0 to 3). Output Signal MasterCPUCLKOFF[n:0] Available only with silicon version r3p1. Individual processorclock disable where n is the processor number (0to 3).0 — Processor clock is enabled. This is the default.1 — Processor clock is stopped.Input Signal Slave1. For these interrupt ports, the active high/low setting is controlled by the negLogic component parameter.The default is active high.2. Size is based on the number of configured cores.All pins that are not listed in this table have been either tied or disconnected for performancereasons.Note:Some ESL component port values can be set using a component parameter. Thisincludes the ACLKENM, ACLKENS, and PCLKENDBG ports. In those cases, theparameter value will be used whenever the ESL port is not connected. If the portis connected, the connection value takes precedence over the parameter value.Carbon Design Systems, Inc. Confidential

Setting Component Parameters 1-91.4 Setting Component ParametersYou can change the settings of all the component parameters in SoC Designer Canvas, andof some of the parameters in SoC Designer Simulator.To modify the Carbon component’s parameters:1. In the Canvas, right-click on the Carbon component and select Edit Parameters....You can also double-click the component. The Edit Parameters dialog box appears.The list of available parameters shown will be slightly different depending on the settingsthat you enabled in the configuration.2. In the Parameters window, double-click the Value field of the parameter that youwant to modify.3. If it is a text field, type a new value in the Value field. If a menu choice is offered,select the desired option. The parameters are described in the following tables.The component parameters are described in Table 1-4.Table 1-4 Component ParametersNameDescriptionAllowedValuesDefault Value Runtime 1A64n128M ACE Master bus-width 0,1 0 NoA64n128S 2 ACP Slave bus-width 0,1 0 NoACEConfigurations 3Supported ACE configurations. Thefour supported values are:ACENonCoherentNoL3ACENonCoherentWithL3Note that “ACENonCoherent”settings use the ACE-Lite protocol.ACEOuterCoherentACEInnerCoherentNote that “ACEInner” and“ACEOuter” settings use theACE protocol.StringACEInnerCoherentACLKENM ACE Master Input Clock Enable 0,1 1 YesACLKENS 2 ACP AXI Slave Input Clock Enable 0,1 1 Yesacp axi_size0acp axi_size[1-5]acp axi_start[0-5]acp Enable DebugMessages 2These parameters are obsolete andshould be left at their default values. 20x1000000000x00x00x1000000000x00x0Enable acp port debug true,false false YesNoNoCarbon Design Systems, Inc. Confidential

1-10 Using the Model Kit Component in SoC Designer PlusTable 1-4 Component Parameters (Continued)NameDescriptionAllowedValuesDefault Value Runtime 1Align Waveformsapb_dbg Base Addressapb_dbg Enable DebugMessagesapb_dbg Sizeaxi_m Enable DebugMessagesCarbon DB PathCFGENDCFGENDn 4CFGTECFGTEn 4When set to true, waveforms dumpedby the Carbon component are alignedwith the SoC Designer Plus simulationtime. The reset sequence, however,is not included in the dumpeddata.When set to false, the reset sequenceis dumped to the waveform data, however,the Carbon component time isnot aligned with SoC Designer Plustime.Start of the apb_dbg port addressregiontrue, false true NoAddress 0x0 NoEnable apb_dbg port debug true,false false YesSize of the apb_dbg port addressregionSize 0x100000000 NoEnable axi_m port debug true,false false YesSets the directory path to the Carbondatabase file.Endianess configuration. 1-bit widefor UP, 4 bits wide for MP. Automaticallykept in sync with CFGENDn.Endianess configuration. Per-corevalue of CFGEND; automaticallykept in sync with CFGEND.Default exception handling state(ARM/Thumb). 1-bit wide for UP, 4bits wide for MP. Automatically keptin sync with CFGTEn.Default exception handling state(ARM/Thumb). Per-core value ofCFGTE; automatically kept in syncwith CFGTE.Not Used empty Nointeger 0 Nobool false Nointeger 0 Nobool false NoCLUSTERID Cluster ID in MPIDR[11:8]. integer 0 NoDump Waveforms Whether SoC Designer Plus dumps bool false Yeswaveforms for this component.Enable Debug MessagesIMINLNWhether debug messages are loggedfor the component.Instr Cache minimum line size(0=32,1=64-byte)bool false Yesinteger 1 NoCarbon Design Systems, Inc. Confidential

Setting Component Parameters 1-11Table 1-4 Component Parameters (Continued)NameDescriptionAllowedValuesDefault Value Runtime 1L2RSTDISABLE Disables L2 Cache Reset bool true NonegLogic Enables active low interrupts bool false YesPCLKENDBG APB DBG Clock Enable 0,1 1 YesPERIPHBASE 2VINITHIVINITHIn 4Peripheral base [39:0] (Bits 14 - 0 areignored)Use high vector addresses. 1-bit widefor UP, 4 bits wide for MP. Automaticallykept in sync with VINITHIn.Use high vector addresses. Per-corevalue of VINITHI; automatically keptin sync with VINITHI.integer 0x0013000000 Nointeger 0 Nobool false NoWaveform File 5 Name of the waveform file. string carbon_CORTEXA5.vcd orcarbon_CORTEXA5MP.vcdWaveform FormatWaveform TimescaleThe format of the waveform dumpfile.Sets the timescale to be used in thewaveform.NoVCD, FSDB VCD NoMany valuesin drop-down1 ns No1. Yes means the parameter can be dynamically changed during simulation, No means it can be changed onlywhen building the system, Reset means it can be changed during simulation, but its new value will be takeninto account only at the next reset.2. Carbon recommends using the Memory Map Editor (MME) in SoC Designer Plus, which provides centralizedviewing and management of the memory regions available to the components in a system. For informationabout migrating existing systems to use the MME, refer to Chapter 9 of the SoC Designer Plus User Guide.3. For additional details, refer to Table 7-4 "Supported ACE configurations" in the ARM Cortex-A15 TechnicalReference Manual.4. n = 0, 1, 2, or 35. When enabled, SoC Designer Plus writes accumulated waveforms to the waveform file in the following situations:when the waveform buffer fills, when validation is paused and when validation finishes, and at the endof each validation run.Carbon Design Systems, Inc. Confidential

1-12 Using the Model Kit Component in SoC Designer Plus1.5 Debug FeaturesThe Cortex-A15 model has a debug interface (CADI) that allows the user to view, manipulate,and control the registers and memory. A view can be accessed in SoC Designer Plusby right clicking on the model and choosing the appropriate menu entry.The following topics are discussed in this section:• Register Information• Run To Debug Point• Memory Information• Disassembly ViewNote:The Cortex-A15 can have up to two slave ports. The apb_dbg port is used forCoreSight debug, and the axi_s port is for ACP, which is used to connect to aDMA engine. These are supported as simulation interfaces, but they are not supportedas debug interfaces. This means if a CADI operation is performed on oneof these interfaces, it will not return data.1.5.1 Register InformationThe Cortex-A15 model has many sets of registers that are accessible via the debug interface.Registers are grouped into sets according to functional area:• Core Registers• ID Registers• Control Registers• Secure World Registers• Normal World Registers• VA to PA Registers• Perf Registers• Debug Registers• VGIC Physical CPU Interface Register• VGIC Distributor Register• VGIC VCPU Virtual Machine view• VGIC VCPU Hypervisor viewSee the ARM Cortex-A15 Technical Reference Manual for detailed descriptions of theseregisters.Note:Registers are accurate only at debuggable points. While SoC Designer Plus graysout the register view when the processor is not at a debuggable point, values arestill visible. Due to the speculative nature of the processor pipeline, these valuesare not guaranteed to be accurate.In general, you can write to a register only at a debuggable point. If a value isdeposited at any other point, it may not be correctly propagated.Carbon Design Systems, Inc. Confidential

Debug Features 1-131.5.1.1 Core RegistersThe Core group contains the ARM architectural registers.Table 1-5 Core RegistersName Description AccessR0-R14 General purpose registers Read/WriteR15 PC. Write at debug point only. Read/WriteCPSRCurrent Program StatusRead/WriteRegisterSPSRSaved Program Status Register for current Read/WritemodeR8_usr-R14_usr R8-R14 in USR mode Read/WriteSPSR_usr Saved program status register in USR mode Read/WriteR13_irq-R14_irq R13/R14 in IRQ mode Read/WriteSPSR_irq Saved program status register in IRQ mode Read/WriteR8_fiq-R14_fiq R8-R14 in FIQ mode Read/WriteSPSR_fiq Saved program status register in FIQ mode Read/WriteR13_svc-R14_svc R13/R14 in SVC mode Read/WriteSPSR_svc Saved program status register in SVC mode Read/WriteR13_abt-R14_abt R13/R14 in ABT mode Read/WriteSPSR_abt Saved program status register in ABT mode Read/WriteR13_und-R14_und R13/R14 in UND mode Read/WriteSPSR_und Saved program status register in UND mode Read/WriteR13_mon-R14_mon R13/R14 in MON mode Read/WriteSPSR_monSaved program status register in MON Read/WritemodeR13_hyp R13 in HYP mode Read/WriteELR_hyp Exception Link Register in HYP mode Read/WriteSPSR_hyp Saved program status register in HYP mode Read/WriteExtendedTargetFeatures Pseudo register that describes additional Read-Onlyprocessor featuresPC_MEMSPACE Pseudo register that indicates the currentmemory space (0=secure,1=normal)Read-Only1.5.1.2 ID RegistersThe ID group contains registers that describe the processor capabilities.Table 1-6 ID RegistersName Description AccessMIDR Main ID Read-OnlyCTR Cache Type Read-OnlyCarbon Design Systems, Inc. Confidential

1-14 Using the Model Kit Component in SoC Designer PlusTable 1-6 ID Registers (Continued)Name Description AccessTCMTR TCM Type Read-OnlyTLBTR TLB Type Read-OnlyMPIDR Multiprocessor Affinity Read-OnlyID_PFR0 Processor Feature 0 Read-OnlyID_PFR1 Processor Feature 1 Read-OnlyID_DFR0 Debug Feature 0 Read-OnlyID_AFR0 Auxiliary Feature 0 Read-OnlyID_MMFR0 Memory Model Feature 0 Read-OnlyID_MMFR1 Memory Model Feature 1 Read-OnlyID_MMFR2 Memory Model Feature 2 Read-OnlyID_MMFR3 Memory Model Feature 3 Read-OnlyID_ISAR0 Instruction Set Attribute Register 0 Read-OnlyID_ISAR1 Instruction Set Attribute Register 1 Read-OnlyID_ISAR2 Instruction Set Attribute Register 2 Read-OnlyID_ISAR3 Instruction Set Attribute Register 3 Read-OnlyID_ISAR4 Instruction Set Attribute Register 4 Read-OnlyID_ISAR5 Instruction Set Attribute Register 5 Read-OnlyID_ISAR6 Instruction Set Attribute Register 6 Read-OnlyID_ISAR7 Instruction Set Attribute Register 7 Read-OnlyCCSIDR Cache Size Identification Read/WriteCLIDR Cache Level ID Read/WriteAIDR AIDR Read-OnlyCSSELR Cache Size Select Register Read/Write1.5.1.3 Control RegistersThe Control group contains registers that dynamically configure the processor.Table 1-7 Control RegistersName Description AccessSCTLR System Control Read/WriteACTLR Auxiliary Control Read/WriteACTLR2 1 Auxiliary Control Register 2 Read/WriteCPACR Coprocessor Access Control Read/WriteNSACR Nonsecure Access Control Read/WriteCarbon Design Systems, Inc. Confidential

Debug Features 1-15Table 1-7 Control Registers (Continued)Name Description AccessTTBR0 Translation Table Base Register 0 Read/WriteTTBR1 Translation Table Base Register 1 Read/WriteTTBCR Translation Table Base Control Register Read/WriteDACR Domain Access Control Read/WriteDFSR Data Fault Status Read/WriteIFSR Instruction Fault Status Read/WriteADFSR Auxiliary Data Fault Status Read/WriteAIFSR Auxiliary Instruction Fault Status Read-OnlyDFAR Data Fault Address Read/WriteIFAR Data Fault Address Read/WriteL2CTLR L2 Control Register Read/WritePRRR Primary Region Remap Read/WriteNMRR Normal Region Remap Read/WriteVBAR Vector Base Address Read/WriteISR Interrupt Status Read/WriteFCSEIDR Fast Context Switch Extension Read-OnlyCONTEXTIDR Context ID Read/WriteTPIDRURW User Read/Write Thread ID Read/WriteTPIDRURO User Read/Write Thread ID Read/WriteTPIDRPRW User Read/Write Thread ID Read/WriteCNTFRQ Clock Ticks Per Second Read/WriteCNTKCTL Kernel Control Register Read/WriteCNTP_TVAL Physical Timer Value Read/WriteCNTP_CTL Physical Control Register Read/WriteCNTV_TVAL Virtual Timer Value Read/WriteCNTV_CTL Virtual Control Register Read/WriteCNTHCTL Hypervisor Control Register Read/WriteCNTHP_TVAL Virtual Timer Value Read/WriteCNTHP_CTL Virtual Control Register Read/WriteIL1DATA0 Instruction L1 Data0 Register Read/WriteIL1DATA1 Instruction L1 Data1 Register Read/WriteIL1DATA2 Instruction L1 Data2 Register Read/WriteDL1DATA0 Data L1 Data0 Register Read/WriteCarbon Design Systems, Inc. Confidential

1-16 Using the Model Kit Component in SoC Designer PlusTable 1-7 Control Registers (Continued)DL1DATA1 Data L1 Data1 Register Read/WriteDL1DATA2 Data L1 Data2 Register Read/WriteDL1DATA3 Data L1 Data3 Register Read/WriteL2ACTLR L2 Cache Auxiliary Control Read/WriteL2ECTLR L2 Extended Control Register Read/WriteL2PFR L2 Prefix Control Register Read/WriteCBAR Configuration Base Address Register Read/WriteVPIDR Virtualization Process ID Read/WriteVMPIDR Virtualization Multiprocessor ID Read/WriteHSCTLR Hypervisor System Control Read/WriteHCR Hypervisor Configuration Register Read/WriteHDCR Hypervisor Debug Configuration Register Read/WriteHCPTR Hypervisor Coprocessor Trap Register Read/WriteHSTR Hypervisor System Trap Register Read/WriteHTCR Virtualization Translation Control Read/WriteVTCR Virtualization Translation Control Read/WriteHADFSRHypervisor Auxiliary Data Fault Status SyndromeRead/WriteHAIFSRName Description AccessHypervisor Auxiliary Instruction Fault StatusSyndromeRead-OnlyHSR Hypervisor Syndrome Read/WriteHDFAR Hypervisor Data Fault Address Read/WriteHIFAR Hypervisor Instruction Fault Address Read/WriteHPFAR Hypervisor IPA Fault Address Read/WriteHMAIR0 Hypervisor Memory Attribute Indirection Read/WriteHMAIR1 Hypervisor Memory Attribute Indirection Read/WriteHVBAR Hypervisor Vector Base Address Read/WriteHTPIDR Hypervisor Software Thread ID Read/WriteCNTPCT Physical Count Read/WriteCNTVCT Physical Count - Virtual Offset Read/WriteCNTP_CVAL Physical Compare Value Read/WriteCNTV_CVAL Virtual Compare Value Read/WriteCNTVOFF Virtual Offset Read/WriteCNTHP_CVAL Virtual Compare Value Read/WriteCarbon Design Systems, Inc. Confidential

Debug Features 1-17Table 1-7 Control Registers (Continued)Name Description AccessCPUMERRSR CPU Memory Error Syndrome Register Read/WriteL2MERRSR L2 Memory Error Syndrome Register Read/WriteHTTBR Hypervisor Translation Table Base Read/WriteVTTBR Virtualization Translation Table Base Read/WriteTTBR0_64 Translation Table Base Register 0 (64-Bit) Read/WriteTTBR1_64 Translation Table Base Register 1 (64-Bit) Read/WritePAR_64 Physical Address Register (64-Bit) Read/Write1. Available with ARM Revision r3p1 only.Carbon Design Systems, Inc. Confidential

1-18 Using the Model Kit Component in SoC Designer Plus1.5.1.4 Secure World RegistersThe Secure World group contains control registers that are only accessible in secure mode.Table 1-8 Secure World RegistersName Description AccessS_SCTLR SCTLR Read/WriteS_ACTLR Auxiliary Control Read/WriteS_ACTLR2 1Auxiliary Control Register 2Read/WriteS_TTBR0 TTBR0 Read/WriteS_TTBR1 TTBR1 Read/WriteS_TTBCR TTBCR Read/WriteS_DACR Domain Access Control Read/WriteS_DFSR Data Fault Status Read/WriteS_IFSR Instruction Fault Status Read/WriteS_ADFSR Auxiliary Data Fault Status Read/WriteS_AIFSR Auxiliary Instruction Fault Status Read-OnlyS_DFAR Data Fault Address Read/WriteS_IFAR Instruction Fault Address Read/WriteS_PAR Physical Address Read/WriteS_PRRR Primary Region Remap Read/WriteS_NMRR Normal Region Remap Read/WriteS_VBAR Vector Base Address Read/WriteS_FCSEIDR Fast Context Switch Extension Read-OnlyS_CONTEXTIDR Context ID Read/WriteS_TPIDRURW User Read/Write Thread ID Read/WriteS_TPIDRURO User Read Only Thread ID Read/WriteS_TPIDRPRW Privileged Only Thread ID Read/WriteS_CSSELR Cache Size Selection Read/Write1. Available with ARM Revision r3p1 only.Carbon Design Systems, Inc. Confidential

Debug Features 1-191.5.1.5 Normal World RegistersThe Normal World group contains control register that are only accessible in non-securemode.Table 1-9 Normal World RegistersName Description AccessN_SCTLR SCTLR Read/WriteN_ACTLR Auxiliary Control Read/WriteN_ACTLR2 1Auxiliary Control Register 2Read/WriteN_TTBR0 TTBR0 Read/WriteN_TTBR1 TTBR1 Read/WriteN_TTBCR TTBCR Read/WriteN_DACR Domain Access Control Read/WriteN_DFSR Data Fault Status Read/WriteN_IFSR Instruction Fault Status Read/WriteN_ADFSR Auxiliary Data Fault Status Read-WriteN_AIFSR Auxiliary Instruction Fault Status Read-OnlyN_DFAR Data Fault Address Read/WriteN_IFAR Instruction Fault Address Read/WriteN_PAR Physical Address Read/WriteN_PRRR Primary Region Remap Read/WriteN_NMRR Normal Region Remap Read/WriteN_VBAR Vector Base Address Read/WriteN_FCSEIDR Fast Context Switch Extension Read-OnlyN_CONTEXTIDR Context ID Read/WriteN_TPIDRURW User Read/Write Thread ID Read/WriteN_TPIDRURO User Read Only Thread ID Read/WriteN_TPIDRPRW Privileged Only Thread ID Read/WriteN_CSSELR Cache Size Selection Read/Write1. Available with ARM Revision r3p1 only.1.5.1.6 VA to PA RegistersThe VA to PA group contains registers related to virtual to physical address translations.Table 1-10 VA to PA RegistersName Description AccessPAR Physical address read-writeCarbon Design Systems, Inc. Confidential

1-20 Using the Model Kit Component in SoC Designer Plus1.5.1.7 Perf RegistersThe Perf group contains performance-related registers.Note:The registers PMXEVCNTRn and PMXEVTYPERn allow direct access to theevent count and event type registers without requiring that the specific registernumber be programmed into PMSELR. For example, if PMSELR contains thevalue 2 then PMXEVCNTR2 and PMXEVCNTR will display the contents of thesame register.Table 1-11 Perf RegistersName Description AccessPMCR Performance Monitor Control Register Read-WritePMCNTENSET Count Enable Set Read-WritePMCNTENCLR Count Enable Clear Read-WritePMOVSR Overflow Flag Status Register Read-WritePMSWINC Software Increment Register Write-OnlyPMSELR Event Counter Selection Register Read-WritePMCEID0Performance Monitor Common Event IdentificationRegister 0Read-OnlyPMCEID1Performance Monitor Common Event IdentificationRegister 1Read-OnlyPMCCNTR Cycle count Read-WritePMXEVTYPER Event Type Select Read-WritePMXEVCNTR Event Count Read-WritePMUSERENR User Enable Register Read-WritePMINTENSET Interrupt Enable Set Read-WritePMINTENCLR Interrupt Enable Clear Read-WritePMXEVCNTR0 Event Count Register 0 Read-WritePMXEVCNTR1 Event Count Register 1 Read-WritePMXEVCNTR2 Event Count Register 2 Read-WritePMXEVCNTR3 Event Count Register 3 Read-WritePMXEVCNTR4 Event Count Register 4 Read-WritePMXEVCNTR5 Event Count Register 5 Read-WritePMXEVTYPER0 Event Type Select Register 0 Read-WritePMXEVTYPER1 Event Type Select Register 1 Read-WritePMXEVTYPER2 Event Type Select Register 0 Read-WritePMXEVTYPER3 Event Type Select Register 3 Read-WritePMXEVTYPER4 Event Type Select Register 4 Read-WritePMXEVTYPER5 Event Type Select Register 0 Read-WriteCarbon Design Systems, Inc. Confidential

Debug Features 1-21Table 1-11 Perf Registers (Continued)PMCCFILTR Cycle Count Filter Control Register Read-WritePMOVSSET Overflow Flag Status Set Register Read-WritePMCFGR Performance Monitor Configuration Register Read-OnlyPMLAR Performance Monitor Lock Access Register Write-OnlyPMLSR Performance Monitor Lock Status Register Read-OnlyPMAUTHSTATUS Performance Monitor Authentication StatusRegisterRead-OnlyPMDEVTYPE Performance Monitor Device Type Register Read-OnlyPMPIDnPerformance Monitor Peripheral Identification RegistersRead-OnlyPMCIDnName Description AccessPerformance Monitor Component IdentificationRegisters1.5.1.8 Debug RegistersThe Debug group provides access to the current debug state.Table 1-12 Debug RegistersRead-OnlyName Description AccessDBGDIDR Debug ID Register Read-OnlyDBGDSCRint Debug Status and Control Register (Internal) Read-WriteDBGWFAR Watchpoint Fault Address Register Read-OnlyDBGPCSR Debug Program Counter Sampling Register Read-WriteDBGVIDSR Virtualization ID Sampling Register Read-WriteDBGDRAR Debug ROM Address Register Read-WriteDBGOSLSR OS Lock Status Register Read-WriteDBGPRSR Powerdown and Reset Status Register Read-WriteDBGLSR Lock Status Register Read-WriteDBGAUTHSTATUS Authentication Status Register Read-WriteDBGDEVTYPE Device Type Register Read-WriteDBGPID0 Peripheral Identification Register 0 Read-WriteDBGPID1 Peripheral Identification Register 1 Read-WriteDBGPID2 Peripheral Identification Register 2 Read-WriteDBGPID3 Peripheral Identification Register 3 Read-WriteDBGPID4 Peripheral Identification Register 4 Read-WriteDBGCID0 Component Identification Register 0 Read-WriteDBGCID1 Component Identification Register 1 Read-WriteCarbon Design Systems, Inc. Confidential

1-22 Using the Model Kit Component in SoC Designer PlusTable 1-12 Debug Registers (Continued)Name Description AccessDBGCID2 Component Identification Register 2 Read-WriteDBGCID3 Component Identification Register 3 Read-WriteDBGITR Instruction Transfer Register Read-WriteDBGVCR Vector Catch Register Read-WriteDBGECR Event Catch Register Read-WriteDBGDTRRXext Debug Translation Register - Receive Read/WriteDBGDTRTXext Debug Transfer Register - Transmit Read/WriteDBGBVR0-5 Breakpoint Value Register 0-5 Read/WriteDBGBCR0-5 Breakpoint Control Register 0-5 Read/WriteDBGWVR0-3 Watchpoint Value Register 0-3 Read/WriteDBGWCR0-3 Watchpoint Control Register 0-3 Read/WriteDBGBXVR4-5 Breakpoint Extended Value Register 4-5 Read/WriteDBGOSDLR OS Double Lock Register Read/WriteDBGPRCR Device Power Down and Reset Control Register Read/WriteDBGITCTRL Integration Mode Control Register Read/WriteDBGCLAIMSET Claim Tag Set Register Read/WriteDBGCLAIMCLR Claim Tag Clear Register Read/WriteDBGDSCRext Debug Status and Control Register (External) Read-Write1.5.1.9 Thumb-EE RegistersThe Thumb-EE group contains registers related to the Thumb Execution environment.Table 1-13 Thumb-EE RegistersName Description AccessTEECR ThumbEE Configuration Register Read/WriteTEEHBR ThumbEE Handler Base Register Read/WriteCarbon Design Systems, Inc. Confidential

Debug Features 1-231.5.1.10 Jazelle RegistersThe Jazelle group contains registers related to Jazelle extension to the ARM Architecture.The Cortex-A15 only implements a trivial Jazelle Extension so all the registers are readonly and read as zero.Table 1-14 Jazelle RegistersName Description AccessJIDR Jazelle ID Register Read-OnlyJOSCR Jazelle OS Control Register Read-OnlyJMCR Jazelle Main Configuration Register Read-Only1.5.1.11 VFP/Neon RegistersThe VFP/Neon group contains registers related to the VFP (Vector Floating-Point) coprocessorand the SIMD (Single Instruction Multiple Data) extensions to the ARM Architecture.Some of the registers are only available if the Neon extension is included.Table 1-15 VFP/Neon RegistersName Description AccessFPSID Floating-point System ID Register Read-OnlyFPSCR Floating-point Status and Control Register Read-WriteFPEXC Floating-point Exception Register Read-WriteFPINST Floating-point Instruction RegisterNot implemented by processorRead-OnlyFPINST2Floating-point Instruction RegisterNot implemented by processorRead-OnlyMVFR0 Media and VFP Feature Register 0 Read-OnlyMVFR1 Media and VFP Feature Register 1 Read-OnlyS0-S31 Advanced SIMD and VFP Extension Single Word Registers Read-WriteD0-D31 Advanced SIMD and VFP Extension Double Word Registers Read-WriteQ0-Q15 Advanced SIMD and VFP Extension Quad Word RegistersNeon onlyRead-WriteCarbon Design Systems, Inc. Confidential

1-24 Using the Model Kit Component in SoC Designer Plus1.5.1.12 VGIC Physical CPU Interface RegisterThis group contains General Interrupt Controller registers for the CPU interface.Table 1-16 VGIC Physical CPU Interface RegistersName Description AccessGICC_CTLR_S CPU Interface Control Register (secure) Read-WriteGICC_CTLR_S CPU Interface Control Register (secure) Read-WriteGICC_CTLR_N CPU Interface Control Register (non-secure) Read-WriteGICC_PMR Interrupt Priority Mask Registers Read-WriteGICC_BPR_S Binary Point Register (secure) Read-WriteGICC_IAR Interrupt Acknowledge Register Read-OnlyGICC_RPR Running Priority Register Read-OnlyGICC_HPPIR Highest Pending Interrupt Register Read-OnlyGICC_ABPR Aliased Binary Point Register Read-WriteGICC_AIAR Aliased Interrupt Acknowledge Register Read-OnlyGICC_AHPPIR Aliased Highest Priority Pending Interrupt Read-OnlyGICC_APRn Active Priority Registers Read-WriteGICC_NSAPRn Non Secure Active Priority Registers Read-WriteGICC_IIDR CPU Interface Identification Register Read-OnlyCarbon Design Systems, Inc. Confidential

Debug Features 1-251.5.1.13 VGIC Distributor RegisterThis group contains General Interrupt Controller Distributor registers.Table 1-17 VGIC Distributor RegistersName Description AccessGICD_CTLR Distributor control register (secure) Read-WriteGICD_DCR_NS Distributor control register (non-secure) Read-WriteGICD_TYPER Interrupt Controller Type Register Read-OnlyGICD_IIDR Distributor Implementer Identification Register Read-OnlyGICD_IGROUPRn Interrupt Security Registers Read-WriteGICD_ISENABLERn Interrupt Set-Enable Registers Read-WriteGICD_ICENABLERn Interrupt Clear-Enable Registers Read-WriteGICD_ISPENDRn Interrupt Set-Pending Registers Read-WriteGICD_ICPENDRn Interrupt Clear-Pending Registers Read-WriteGICD_ISACTIVERn Interrupt Set-Active Register Read-WriteGICD_ICACTIVERn Interrupt Clear-Active Register Read-WriteGICD_IPRIORITYRn Interrupt Priority Register Read-WriteGICD_ITARGETSRn Interrupt Processor Targets Registers Read-OnlyGICD_ICFGRn Interrupt Configuration Registers Read-WriteGICD_PPISR Private Peripheral Interrupt Status Register Read-OnlyGICD_SPISRn Shared Peripheral Interrupt Status Registers Read-OnlyGICD_CPENDSGIRn Clear pending Software Generated Interrupt Read-WriteGICD_SPENDSGIRn Set pending Software Generated Interrupt Read-WriteGICD_PIDRn Peripheral ID registers Read-OnlyGICD_CIDRn Component ID registers Read-Only1.5.1.14 VGIC VCPU Virtual Machine viewThis group contains VCPU Virtual Machine registers.Table 1-18 VGIC VCPU Virtual Machine RegistersName Description AccessGICV_CTLR VM Control Register Read-WriteGICV_PMR VM Priority Mask Register Read-WriteGICV_BPR VM Binary Point Register Read-WriteGICV_IAR VM Interrupt Acknowledge Register Read-OnlyGICV_RPR VM Running Priority Register Read-OnlyGICV_HPPIR VM Highest Priority Pending Interrupt Register Read-OnlyCarbon Design Systems, Inc. Confidential

1-26 Using the Model Kit Component in SoC Designer PlusTable 1-18 VGIC VCPU Virtual Machine Registers (Continued)Name Description AccessGICV_ABPR VM Aliased Binary Point Register Read-WriteGICV_AIAR VM Aliased Interrupt Acknowledge Register Read-OnlyGICV_AHPPIR VM Aliased Highest Priority Pending InterruptRegisterRead-OnlyGICV_APR0 VM Active Priority Register Read-Only 1GICV_IIDR VM Cpu Interface Identification Register Read-Only1. See GICC_APR0 or GICH_APR0 to write this register.1.5.1.15 VGIC VCPU Hypervisor viewThis group contains VCPU Hypervisor registers.Table 1-19 VGIC VCPU Hypervisor RegistersName Description AccessGICH_HCR Hypervisor Control Register Read-WriteGICH_VTR VGIC Type Register Read-OnlyGICH_VMCR Virtual Machine Control Register Read-WriteGICH_MISR Maintenance Interface Status Register Read-OnlyGICH_EISRn End of Interrupt Statu Registers Read-OnlyGICH_ELRSRn Empty List Register Status Registers Read-OnlyGICH_APR Active Priorities Register Read-WriteGICH_LRn List Registers Read-WriteCarbon Design Systems, Inc. Confidential

Debug Features 1-271.5.2 Run To Debug PointThe “run to debug point” feature has been added to enhance model debugging. The Cortex-A15processor is a dual issue out of order completion machine. This means that whilethe processor is running it does not present a coherent programmer’s view state; instructionsin the pipeline may be in different execution states.This feature forces the processor into a coherent state called “run to debug point”. Whendebugging with the ARM RealView Development Suite (RVDS), the model is brought tothe debug point automatically whenever a software breakpoint is hit (including singlestepping). However, if a hardware breakpoint is reached, or the system is advanced bycycles within SoC Designer Plus, the model can get to a non-debuggable state. In thisevent, the run to debug point will advance the processor to the debug state. It does this bystalling the instruction within the decode stage and allowing all earlier instructions to complete.Once that has been accomplished, the model will cause the system to stop simulating.The run to debug point is available as a context menu item (Run to Debuggable Point) forthe component within SoC Designer Simulator. It is also available in the disassemblerview.1.5.3 Memory InformationThe Cortex-A15 processor supports the following memory spaces, which are selectableusing the Space: pulldown menu in the Memory view, and the Memory space pulldownmenu in the Disassembly view:• secure — Uses the S_TTBR0, S_TTBR1, and S_TTBCR registers to translate fromVA to PA. This space is active when (SCR.NS == 0) or (CPSR.M == MON).• nshyp — Uses the HTTBR and HTCR registers to translate from VA to PA. Thisspace is active when (SCR.NS == 1) and (CPSR.M == HYP).• normal — Uses the N_TTBR0, N_TTBR1, and N_TTBCR registers to translate fromVA to PA. This space is active when (SCR.NS == 1) and (CPSR.M != HYP) and(CPSR.M != MON).• axi_m — Main memory space.1.5.4 Disassembly ViewSoC Designer Simulator supports a disassembly view of a program running on the Cortex-A15 model. To display the disassembly view in the SoC Designer Simulator, right-click onthe Cortex-A15 model and select View Disassembly… from the context menu.All CADI windows support breakpoints – when double-clicking on the proper location ared dot will indicate that a breakpoint is currently active. To remove the breakpoints simplydouble-click on the same location again.Carbon Design Systems, Inc. Confidential

1-28 Using the Model Kit Component in SoC Designer Plus1.6 Available Profiling DataProfiling data is enabled, and can be viewed using the Profiling Manager, which is accessiblevia the Debug menu in the SoC Designer Simulator. Both hardware and softwarebased profiling are available.1.6.1 Hardware ProfilingHardware events are uniquely identified by their Event Number as defined in theCortexA15 TRM (Table 11-7 PMU events). The event names that appear in the ProfilingManager view are a concatenation of the event number and a shortened form of the eventname. If architecture mnemonics have been defined by ARM then that name has beenused; otherwise, a short form of the name has been created.Hardware profiling includes the streams and events shown in Table 1-20.Table 1-20 Cortex-A15 Profiling EventsStream Event Name CommentsInstructions 0x00_CPU_RAW_CYCLES Instruction architecturally executed(condition check pass)0x08_INST_RETIREDInstructions retired0x09_EXC_TAKENException taken0x0A_EXC_RETURNInstruction architecturally executed(condition check pass) - Exceptionreturn0x0B_CID_WRITE_RETIRED Instruction architecturally executed(condition check pass) - Write toCONTEXTIDR0x1C_TTBR_WRITE_RETIRED Instruction architecturally executed(condition check pass) - Write totranslation table base0xD5_num_FDIV/SQRTFDIV/SQRT instruction countCarbon Design Systems, Inc. Confidential

Available Profiling Data 1-29Table 1-20 Cortex-A15 Profiling Events (Continued)Stream Event Name CommentsPipeline 0x10_MIS_PRED Mispredicted or not predictedbranch speculatively executed0x12_BR_PREDPredictable branch speculativelyexecuted0x1B_INST_SPECInstruction speculatively executed0x6C_LDREX_SPECExclusive instruction speculativelyexecuted - LDREX0x6D_STREX_PASS_SPECExclusive instruction speculativelyexecuted - STREX pass0x6E_STREX_FAIL_SPECExclusive instruction speculativelyexecuted - STREX fail0x70_LD_SPEC Instruction speculatively executed -Load0x71_ST_SPEC Instruction speculatively executed -Store0x72_LDST_SPEC Instruction speculatively executed -Load or store0x73_DP_SPEC Instruction speculatively executed -Data processing0x74_ASE_SPEC Instruction speculatively executed -Advanced SIMD0x75_VFP_SPEC Instruction speculatively executed -VFP0x76_PC_WRITE_SPEC Instruction speculatively executed -Software change of the PC0x78_BR_IMMED_SPEC Branch speculatively executed -Immediate branchCarbon Design Systems, Inc. Confidential

1-30 Using the Model Kit Component in SoC Designer PlusTable 1-20 Cortex-A15 Profiling Events (Continued)Stream Event Name CommentsPipeline(continued)0x79_BR_RETURN_SPECBranch speculatively executed - Procedurereturn0x7A_BR_INDIRECT_SPEC Branch speculatively executed -Indirect branch0x7C_ISB_SPECBarrier speculatively executed - ISB0x7D_DSB_SPEC Barrier speculatively executed -DSB0x7E_DMB_SPEC Barrier speculatively executed -DMB0xC0_num_micro_predicted_branches Number of micro BTB or BTB predictedbranches0xC1_num_unpredicted_branches_not_taken0xC2_num_microt_predicted_cond_branch0xC3_num_mispredicted_micro_branches0xC4_num_poly_indirect_br_resolved0xC5_num_marked_indirect_br_withaddr_mispredict0xC6_return_BTB0xC7_return_addr_not_predicted0xD3_num_microOps_renamed0xD6_groups_count0xD9_L/S/L_restart_count0xDA_stall_issue_q_full_BX0xDB_stall_issue_q_full_CX1/CX20xDC_stall_issue_q_full_LS0xDD_stall_issue_q_full_MX0xDE_stall_issue_q_full_SPNumber of unpredicted not takenbranchesNumber of micro BTB and BTBpredicted conditional branchesNumber of directional mispredictedmicro BTB and BTB predictedbranchesNumber of polymorphic indirect(NON POP) branches rslvdNumber of marked indirect branchwith address mispredictReturn is BTB predicted or unpredictedReturn address mispredicted fromBTB or unpredictedNumber of micro operationsrenamedGroups countLoad store load restart countDispatch stall due to issue queue fullBXDispatch stall due to issue queue fullCX1 or CX2Dispatch stall due to issue queue fullLSDispatch stall due to issue queue fullMXDispatch stall due to issue queue fullSPCarbon Design Systems, Inc. Confidential

Available Profiling Data 1-31Table 1-20 Cortex-A15 Profiling Events (Continued)Stream Event Name CommentsPipeline(continued)0xDF_stall_issue_q_full_SX1/SX2Dispatch stall due to issue queue fullSX1 or SX2Bad branch flushECC flush + RAR flushNEON conditional flushRare flushesSWDW_NUKE0xE0_bad_branch_flush0xE1_ECC/RAR_flush0xE2_NEON_cond_flush0xE3_rare_flush0xE4_SWDW_NUKE0xFD_num_cycles_with_0_inst_from_fe Number of cycles with no instructionstch_qfrom the fetch queueI-Cache 0x01_L1I_CACHE_REFILL Level 1 instruction cache refill0x14_L1I_CACHELevel 1 instruction cache accessD-Cache 0x03_L1D_CACHE_REFILL Level 1 data cache refill0x04_L1D_CACHELevel 1 data cache access0x15_L1D_CACHE_WBLevel 1 data cache write-back0x40_L1D_CACHE_LDLevel 1 data cache access - Read0x41_L1D_CACHE_STLevel 1 data cache access - Write0x42_L1D_CACHE_REFILL_LD Level 1 data cache refill - Read0x43_L1D_CACHE_REFILL_ST Level 1 data cache refill - Write0x46_L1D_CACHE_WB_VICTIMback_victim0x47_L1D_CACHE_WB_CLEANback_coherency0x48_L1D_CACHE_INVALLevel 1 data cache write-back - VictimLevel 1 data cache write-back -Cleaning and coherencyLevel 1 data cache invalidateCarbon Design Systems, Inc. Confidential

1-32 Using the Model Kit Component in SoC Designer PlusTable 1-20 Cortex-A15 Profiling Events (Continued)Stream Event Name CommentsL2-Cache 0x16_L2D_CACHE Level 2 data cache access0x17_L2D_CACHE_REFILLLevel 2 data cache refill0x18_L2D_CACHE_WBLevel 2 data cache write-back0x50_L2D_CACHE_LDLevel 2 data cache access - Read0x51_L2D_CACHE_STLevel 2 data cache access - Write0x52_L2D_CACHE_REFILL_LD Level 2 data cache refill - Read0x53_L2D_CACHE_REFILL_ST Level 2 data cache refill - Write0x56_L2D_CACHE_WB_VICTIM Level 2 data cache write-back - Victim0x57_L2D_CACHE_WB_CLEAN Level 2 data cache write-back -Cleaning and coherency0x58_L2D_CACHE_INVALLevel 2 data cache invalidate0xED_L2_TBW_desc_readL2 TBW descriptor read access0xEE_L2_IPA-PA_accessL2 IPA-PA cache accesses0xEF_L2_IPA-PA_hitL2 IPA-PA cache hit0xF0_L2_S1_L2_PA_hitL2 S1 L2 PA cache hit0xF1_L2_S1_walk_hitL2 S1 walk cache hit0xF8_L2_prefetch_access_count L2 Prefetcher access count (allprefetch requests)0xF9_L2_prefetch_line_used_count L2 Prefetch line used count0xFA_L2_prefetch_drop_count L2 Prefetcher dropped count (numberof things dropped fromprefetcher queue that do not make itinto the system)0xFB_L2_load_hzdL2 Load hazards against prefetch(can be determined because of FEQhazard)0xFC_L2_stall_no_FEQL2 stalled because of no availableFEQsMemory 0x13_MEM_ACCESS Data memory access0x1A_MEMORY_ERRORLocal memory error0x66_MEM_ACCESS_LDData memory access - Read0x67_MEM_ACCESS_STData memory access - Write0x68_UNALIGNED_LD_SPEC Unaligned access - Read0x69_UNALIGNED_ST_SPEC Unaligned access - Write0x6A_UNALIGNED_LDST_SPEC Unaligned accessCarbon Design Systems, Inc. Confidential

Available Profiling Data 1-33Table 1-20 Cortex-A15 Profiling Events (Continued)Stream Event Name CommentsPTM 0xD7_count_PTM_extout_0 Count PTM EXTOUT 00xD8_count_PTM_extout_1 Count PTM EXTOUT 1Bus 0x19_BUS_ACCESS Bus access0x1D_BUS_CYCLESBus cycle0x60_BUS_ACCESS_LDBus access - Read0x61_BUS_ACCESS_STBus access - Write0x62_BUS_ACCESS_SHARED Bus access - Normal CacheableShareable0x63_BUS_ACCESS_NOT_SHARED Bus access - Not Normal CacheableShareable0x64_BUS_ACCESS_NORMAL Bus access - Normal0x65_BUS_ACCESS_PERIPH Bus access - Peripheral0xE5_BUS_TRANS_LDBus read transaction0xE6_BUS_TRANS_STBus write transaction0xE7_BUS_ACCESS_SNOOP Bus access - snoop0xE8_BUS_TRANS_PFBus transaction - prefetchesACP 0xE9_ACP_slv_port_read_trans ACP slave port read transaction0xEA_ACP_slv_port_read_data ACP slave port read data0xEB_ACP_slv_port_write_trans ACP slave port write transaction0xEC_ACP_slv_port_write_data ACP slave port write data0xFE_ACP_master_port_read_trans ACP master port read transaction0xFF_ACP_master_port_write_tran ACP master port write transactionCarbon Design Systems, Inc. Confidential

1-34 Using the Model Kit Component in SoC Designer PlusTable 1-20 Cortex-A15 Profiling Events (Continued)Stream Event Name CommentsCycle 0x11_CPU_CYCLES Cycle0xC8_cycles_single_micro_op_decoded/sequenced0xC9_cycles_when_lt_3_uOps_avail0xCA_cycles_rename_stalls_when_no_flags_avail0xCB_cycles_rename_stalls_when_no_registers_avail0xCC_cycles_rename_in_dribble0xD2_cycles_for_inst_with_no_rename_EXT/0xD4_cycles_with_FDIV/SQRT_activeIncrement every cycle when singlemicro operation is decoded/sequencedIncrement every cycle when lessthan 3 micro operations are availableto renameNumber of cycles rename stalls dueto lack of flagsNumber of cycles rename stalls dueto lack of registersNumber of cycles when rename is indribble modeNumber of cycles when no instructionthat either writes-to or readsfromEXT registers is renamedIncrement every cycle when FDIV/SQRT is activeLoop 0xCD_bad_loop_count_in_buffer Bad loop count in loop buffer0xCE_loop_buffer_locked_in_buffer Loop buffer loops locked into buffer0xCF_loop_buffer_iterationsLoop buffer iterations0xD0_uOps_from_loop_buffer Micro operations executed fromloop buffer0xD1_num_cycles_when_uOps_from_loop_bufferNumber of cycles when micro operationsare sourced from the loop bufferTLB 0x02_L1I_TLB_MISS Level 1 instruction TLB refill0x05_L1D_TLB_REFILLLevel 1 data TLB refill0x4C_L1D_TLB_REFILL_LD Level 1 data TLB refill - Read0x4D_L1D_TLB_REFILL_ST Level 1 data TLB refill - Write0xF2_L2_TLB_lookup_access L2 TLB number of accesses made tothe array during lookup0xF3_L2_TLB_hit_IF_reqL2 TLB hits on IF requests0xF4_L2_TLB_hit_LS_reqL2 TLB hits on LS requests0xF5_L2_TLB_hit_PF_reqL2 TLB hit on PF requests0xF6_L2_TLB_num_PF_access L2 TLB number of PF accesses0xF7_L2_TLB_shutdownL2 TLB shutdownsCarbon Design Systems, Inc. Confidential

Available Profiling Data 1-351.6.2 Software ProfilingSoftware-based profiling is provided by SoC Designer Plus. Profiling information is alsoavailable in the SoC Designer Profiler. See the user guide for SoC Designer Plus or SoCDesigner Profiler for more information.Carbon Design Systems, Inc. Confidential

1-36 Using the Model Kit Component in SoC Designer PlusCarbon Design Systems, Inc. Confidential

Third Party Software AcknowledgementCarbon acknowledges and thanks the respective owners for the following software that isused by our product:• ELF (Executable and Linking Format) Tool Chain ProductCopyright (c) 2006, 2008-2012 Joseph KoshyAll rights reserved.Redistribution and use in source and binary forms, with or without modification, are permittedprovided that the following conditions are met:1. Redistributions of source code must retain the above copyright notice, this list of conditionsand the following disclaimer.2. Redistributions in binary form must reproduce the above copyright notice, this list ofconditions and the following disclaimer in the documentation and/or other materialsprovided with the distribution.THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``ASIS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOTLIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FIT-NESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALLTHE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODSOR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUP-TION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER INCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTH-ERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVENIF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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