Carbon Cortex-A15 Model User Guide for SoC Designer

1-32 Using the Model Kit Component in SoC Designer PlusTable 1-20 Cortex-A15 Profiling Events (Continued)Stream Event Name CommentsL2-Cache 0x16_L2D_CACHE Level 2 data cache access0x17_L2D_CACHE_REFILLLevel 2 data cache refill0x18_L2D_CACHE_WBLevel 2 data cache write-back0x50_L2D_CACHE_LDLevel 2 data cache access - Read0x51_L2D_CACHE_STLevel 2 data cache access - Write0x52_L2D_CACHE_REFILL_LD Level 2 data cache refill - Read0x53_L2D_CACHE_REFILL_ST Level 2 data cache refill - Write0x56_L2D_CACHE_WB_VICTIM Level 2 data cache write-back - Victim0x57_L2D_CACHE_WB_CLEAN Level 2 data cache write-back -Cleaning and coherency0x58_L2D_CACHE_INVALLevel 2 data cache invalidate0xED_L2_TBW_desc_readL2 TBW descriptor read access0xEE_L2_IPA-PA_accessL2 IPA-PA cache accesses0xEF_L2_IPA-PA_hitL2 IPA-PA cache hit0xF0_L2_S1_L2_PA_hitL2 S1 L2 PA cache hit0xF1_L2_S1_walk_hitL2 S1 walk cache hit0xF8_L2_prefetch_access_count L2 Prefetcher access count (allprefetch requests)0xF9_L2_prefetch_line_used_count L2 Prefetch line used count0xFA_L2_prefetch_drop_count L2 Prefetcher dropped count (numberof things dropped fromprefetcher queue that do not make itinto the system)0xFB_L2_load_hzdL2 Load hazards against prefetch(can be determined because of FEQhazard)0xFC_L2_stall_no_FEQL2 stalled because of no availableFEQsMemory 0x13_MEM_ACCESS Data memory access0x1A_MEMORY_ERRORLocal memory error0x66_MEM_ACCESS_LDData memory access - Read0x67_MEM_ACCESS_STData memory access - Write0x68_UNALIGNED_LD_SPEC Unaligned access - Read0x69_UNALIGNED_ST_SPEC Unaligned access - Write0x6A_UNALIGNED_LDST_SPEC Unaligned accessCarbon Design Systems, Inc. Confidential