Carbon Cortex-A15 Model User Guide for SoC Designer

1-6 Using the Model Kit Component in SoC Designer Plus1.2.2 Adding the Carbon Model to the Component LibraryThe compiled Carbon Model component is provided as a configuration file (.conf). Tomake the component available in the Component Window in SoC Designer Canvas, useSoC Designer Canvas.For more information on SoC Designer Canvas, see the Carbon SoC Designer Plus UserGuide.1.2.3 Adding the Component to the SoC Designer CanvasLocate the component in the Component Window and drag it out to the Canvas. Dependingon your configuration, ports may differ from those listed in Table 1-3 (see “AvailableComponent ESL Ports” on page 1-6).1.3 Available Component ESL PortsTable 1-3 describes the ESL ports that are exposed in SoC Designer Plus. See the ARMCortex-A15 Technical Reference Manual for more information.Table 1-3 ESL Component PortsESL Port Description Direction Typeaxi_m ACE Master S2T. Output TransactorMasteracp AXI Slave T2S. Input TransactorSlaveapb_dbg APB3 Slave T2S. Input TransactorSlavefiq 1irq 1vfiq 1virq 1INTFIQ Interrupt Port. Size is 1 to 4 depending on the numberof CPUs.IRQ Interrupt Port.Size is 1 to 4 depending on the numberof CPUs.Virtual FIQ Interrupt Port. Size is 1 to 4 depending on thenumber of CPUs.Virtual IRQ Interrupt Port. Size is 1 to 4 depending on thenumber of CPUs.The ARM RTL IRQS port, which connects to the Carboninterrupt transactor. Connect to the INT port via theintVector component.INT can be any size between 0 and 224, in increments of32. The value must indicate the interrupt number[NumIRQ..0] and the *extValue must indicate whetherthe IRQ line is asserted (*extValue=1) or deasserted(*extValue=0).InputInputInputInputInputSignal SlaveSignal SlaveSignal SlaveSignal SlaveSignal SlaveCP15SDISABLE Disables write access to CP15 registers. Input Signal SlaveCFGSDISABLE Disables write access to secure IC registers. Input Signal SlaveEVENTI Event Input. Input Signal SlaveCarbon Design Systems, Inc. Confidential