Carbon Cortex-A15 Model User Guide for SoC Designer

1-24 Using the Model Kit Component in SoC Designer Plus1.5.1.12 VGIC Physical CPU Interface RegisterThis group contains General Interrupt Controller registers for the CPU interface.Table 1-16 VGIC Physical CPU Interface RegistersName Description AccessGICC_CTLR_S CPU Interface Control Register (secure) Read-WriteGICC_CTLR_S CPU Interface Control Register (secure) Read-WriteGICC_CTLR_N CPU Interface Control Register (non-secure) Read-WriteGICC_PMR Interrupt Priority Mask Registers Read-WriteGICC_BPR_S Binary Point Register (secure) Read-WriteGICC_IAR Interrupt Acknowledge Register Read-OnlyGICC_RPR Running Priority Register Read-OnlyGICC_HPPIR Highest Pending Interrupt Register Read-OnlyGICC_ABPR Aliased Binary Point Register Read-WriteGICC_AIAR Aliased Interrupt Acknowledge Register Read-OnlyGICC_AHPPIR Aliased Highest Priority Pending Interrupt Read-OnlyGICC_APRn Active Priority Registers Read-WriteGICC_NSAPRn Non Secure Active Priority Registers Read-WriteGICC_IIDR CPU Interface Identification Register Read-OnlyCarbon Design Systems, Inc. Confidential