Carbon Cortex-A15 Model User Guide for SoC Designer

1-34 Using the Model Kit Component in SoC Designer PlusTable 1-20 Cortex-A15 Profiling Events (Continued)Stream Event Name CommentsCycle 0x11_CPU_CYCLES Cycle0xC8_cycles_single_micro_op_decoded/sequenced0xC9_cycles_when_lt_3_uOps_avail0xCA_cycles_rename_stalls_when_no_flags_avail0xCB_cycles_rename_stalls_when_no_registers_avail0xCC_cycles_rename_in_dribble0xD2_cycles_for_inst_with_no_rename_EXT/0xD4_cycles_with_FDIV/SQRT_activeIncrement every cycle when singlemicro operation is decoded/sequencedIncrement every cycle when lessthan 3 micro operations are availableto renameNumber of cycles rename stalls dueto lack of flagsNumber of cycles rename stalls dueto lack of registersNumber of cycles when rename is indribble modeNumber of cycles when no instructionthat either writes-to or readsfromEXT registers is renamedIncrement every cycle when FDIV/SQRT is activeLoop 0xCD_bad_loop_count_in_buffer Bad loop count in loop buffer0xCE_loop_buffer_locked_in_buffer Loop buffer loops locked into buffer0xCF_loop_buffer_iterationsLoop buffer iterations0xD0_uOps_from_loop_buffer Micro operations executed fromloop buffer0xD1_num_cycles_when_uOps_from_loop_bufferNumber of cycles when micro operationsare sourced from the loop bufferTLB 0x02_L1I_TLB_MISS Level 1 instruction TLB refill0x05_L1D_TLB_REFILLLevel 1 data TLB refill0x4C_L1D_TLB_REFILL_LD Level 1 data TLB refill - Read0x4D_L1D_TLB_REFILL_ST Level 1 data TLB refill - Write0xF2_L2_TLB_lookup_access L2 TLB number of accesses made tothe array during lookup0xF3_L2_TLB_hit_IF_reqL2 TLB hits on IF requests0xF4_L2_TLB_hit_LS_reqL2 TLB hits on LS requests0xF5_L2_TLB_hit_PF_reqL2 TLB hit on PF requests0xF6_L2_TLB_num_PF_access L2 TLB number of PF accesses0xF7_L2_TLB_shutdownL2 TLB shutdownsCarbon Design Systems, Inc. Confidential