Carbon Cortex-A15 Model User Guide for SoC Designer

1-2 Using the Model Kit Component in SoC Designer PlusThis section provides a summary of the functionality of the model compared to that of thehardware, and the performance and accuracy of the model.• Implemented Hardware Features• Hardware Features not Implemented• Features Additional to the Hardware1.1.1 Implemented Hardware FeaturesMost hardware features have been implemented. Some functionality and register pin differencesare listed in the next section.Note that when using semihosting you must use the semihost component from Carbon.This “CarbonSemihost” component is included in the Carbon SoC Designer Plus StandardModel Library, version 3.0 or greater. The ARM RVML semihost component will notwork with the Carbon Model.See the ARM Cortex-A15 Technical Reference Manual for more information.1.1.2 Hardware Features not ImplementedThe following features of the Cortex-A15 hardware are not implemented in the Carbonizedmodel:• Debug access to virtual memory does not currently handle TLB lockdown.• Debug transactions do not fully support cache coherence. This means that the debugtransaction could read or write data without realizing that it is accessing data thatresides in the other cores’ caches. Debug transactions are needed by RVD accesses tomemory, as well as by semihosting. If you see a different memory value from RVDthan what you see by opening the Memory view in the processor and memory, thenyour design may have encountered this limitation.• Some registers are read-only. See the section “Register Information” on page 1-12 formore information.• The registers in Table 1-1 on page 1-3 are not available to be read/written via debugtransactions — for example, in the SoC Designer Plus Registers window, or byaccessing them directly from RealView Debugger.The functionality of these registers, however, does exist and can be accessed by softwarerunning on the virtual platform.Carbon Design Systems, Inc. Confidential