Carbon GIC PL390 Model User Guide for SoC Designer Plus

PrefaceixFurther readingThis section lists related publications by Carbon and by third parties.Carbon SoC Designer Plus DocumentationThe following publications provide information that relate directly to SoC Designer Plus:• Carbon SoC Designer Plus Installation Guide• Carbon SoC Designer Plus User Guide• Carbon SoC Designer Plus RTOE User Guide• Carbon SoC Designer Plus Standard Model Library Reference Manual• Carbon SoC Designer Plus AXIv2 Protocol Bundle User Guide• Carbon SoC Designer Plus AHBv2 Protocol Bundle User GuideExternal publicationsThe following publications provide reference information about ARM® products:• ARM PrimeCell Generic Interrupt Controller (PL390) Technical Reference Manual• ARM PrimeCell Generic Interrupt Controller (PL390) Implementation Guide• ARM PrimeCell Generic Interrupt Controller (PL390) Integration Manual• AMBA® Designer User Guide• AMBA Designer PrimeCell Generic Interrupt Controller User Guide Supplement• ARM Generic Interrupt Controller Architecture Specification• AMBA Specification• AMBA AXI Protocol Specification• AMBA 3 AHB-Lite Protocol Specification• ARM Architecture Reference Manual• ARM RealView Model Debugger User GuideSee http://infocenter.arm.com/help/index.jsp for access to ARM documentation.The following publications provide additional information on simulation:• IEEE 1666 SystemC Language Reference Manual, (IEEE Standards Association)• SPIRIT User Guide, Revision 1.2, SPIRIT Consortium.Carbon Design Systems, Inc. Confidential

xPrefaceGlossaryAMBAAHBAPBAXICarbon ModelCarbon ModelStudioCASICADICAPIComponentESLHDLRTLSoC DesignerSystemCTransactorAdvanced Microcontroller Bus Architecture. The ARM open standard on-chipbus specification that describes a strategy for the interconnection and managementof functional blocks that make up a System-on-Chip (SoC).Advanced High-performance Bus. A bus protocol with a fixed pipelinebetween address/control and data phases. It only supports a subset of the functionalityprovided by the AMBA AXI protocol.Advanced Peripheral Bus. A simpler bus protocol than AXI and AHB. It isdesigned for use with ancillary or general-purpose peripherals such as timers,interrupt controllers, UARTs, and I/O ports.Advanced eXtensible Interface. A bus protocol that is targeted at high performance,high clock frequency system designs and includes a number of featuresthat make it very suitable for high speed sub-micron interconnect.A software object created by the Carbon Model Studio (or Carbon compiler)from an RTL design. The Carbon Model contains a cycle- and register-accuratemodel of the hardware design.Carbon’s graphical tool for generating, validating, and executing hardwareaccuratesoftware models. It creates a Carbon Model, and it also takes a CarbonModel as input and generates a Carbon component that can be used inSoC Designer Plus, Platform Architect, or OSCI SystemC for simulation.ESL API Simulation Interface, is based on the SystemC communicationlibrary and manages the interconnection of components and communicationbetween components.ESL API Debug Interface, enables reading and writing memory and registervalues and also provides the interface to external debuggers.ESL API Profiling Interface, enables collecting historical data from a componentand displaying the results in various formats.Building blocks used to create simulated systems. Components are connectedtogether with unidirectional transaction-level or signal-level connections.Electronic System Level. A type of design and verification methodology thatmodels the behavior of an entire system using a high-level language such as Cor C++.Hardware Description Language. A language for formal description of electroniccircuits, for example, Verilog or VHDL.Register Transfer Level. A high-level hardware description language (HDL)for defining digital circuits.The full name is Carbon SoC Designer Plus. A high-performance, cycle accuratesimulation framework which is targeted at System-on-a-Chip hardwareand software debug as well as architectural exploration.SystemC is a single, unified design and verification language that enables verificationat the system level, independent of any detailed hardware and softwareimplementation, as well as enabling co-verification with RTL design.Transaction adaptors. You add transactors to your Carbon component to connectyour component directly to transaction level interface ports for your particularplatform.Carbon Design Systems, Inc. Confidential

1-2 Using the Model Kit Component in SoC Designer Plus1.1.1 Fully Functional and Accurate FeaturesThe following features of the PL390 Generic Interrupt Controller hardware are fullyimplemented in the PL390 Generic Interrupt Controller model:• Support for three interrupt types:– Software Generated Interrupt (SGI)– Private Peripheral Interrupt (PPI)– Shared Peripheral Interrupt (SPI)• Programmable interrupts that enable you to set the:– security state for an interrupt– priority level of an interrupt– enabling or disabling of an interrupt– processors that receive an interrupt• Enhanced security features, when the GIC is configured to support the SecurityExtensions.1.1.2 Features Additional to the HardwareThe following features that are implemented in the GIC PL390 model do not exist in thePL390 hardware. These features have been added to the model for enhanced usability.• The component supports positive and negative level irq and fiq signal. This is configurableusing the negLogic component parameter (see the tables in the section “SettingComponent Parameters” on page 1-8). By default, all the irq/fiq inputs and outputs areactive-HIGH.• The match_x and enable_x component parameters have been added to set the valuesof the corresponding ports: where x is either c (CPU interface) or d (Distributor).1.1.3 Hardware Features not ImplementedThe following hardware features have not been implemented in the Carbon Model:• The following registers are not available:– Distributor Configuration registers: ppi_enable_if (clear), spi_enable (clear),spi_pending (clear), sgi_pending_if (clear), ppi_pending_if (clear), spi_config,and sgi_control. For the registers with (clear), use the corresponding versions ofthose registers (for example, sgi_pending_if) to set and to clear the register.• The following registers are not available to be read / written via debug transactions —for example, in the SoC Designer Plus Registers window, or by accessing themdirectly from RealView Debugger:– Control registers: int_ack, eoi, run_priority, and hi_pending.– The Integration Test registers.The functionality of these registers, however, does exist and can be accessed by softwarerunning on the virtual platform.• AXI and AHB-Lite debug read/write to registers is not supported.Carbon Design Systems, Inc. Confidential

Adding and Configuring the SoC Designer Plus Component 1-31.2 Adding and Configuring the SoC Designer Plus ComponentThe following topics briefly describe how to use the component. See the Carbon SoCDesigner Plus User Guide for more information.• Carbon SoC Designer Plus Component Files• Adding the Carbon Model to the Component Library• Adding the Component to the SoC Designer Canvas1.2.1 Carbon SoC Designer Plus Component FilesThe component files are the final output from the Carbon Model Studio compile and arethe input to SoC Designer Plus. There are two versions of the component; an optimizedrelease version for normal operation, and a debug version.On Linux the debug version of the component is compiled without optimizations andincludes debug symbols for use with gdb. The release version is compiled without debuginformation and is optimized for performance.On Windows the debug version of the component is compiled referencing the debug runtimelibraries, so it can be linked with the debug version of SoC Designer Plus. Therelease version is compiled referencing the release runtime library. Both release and debugversions generate debug symbols for use with the Visual C++ debugger on Windows.The provided component files are listed below:Table 1-1 Carbon SoC Designer Plus Component FilesPlatform File DescriptionLinuxWindowsmaxlib.lib.conflib.mx.solib.mx_DBG.somaxlib.lib.windows.conflib.mx.dlllib.mx_DBG.dllSoC Designer Plus configuration fileSoC Designer Plus component runtimefileSoC Designer Plus component debugfileSoC Designer Plus configuration fileSoC Designer Plus component runtimefileSoC Designer Plus component debugfileAdditionally, this User Guide PDF file and a ReadMe text file are provided with the component.Carbon Design Systems, Inc. Confidential

1-4 Using the Model Kit Component in SoC Designer Plus1.2.2 Adding the Carbon Model to the Component LibraryThe compiled Carbon Model component is provided as a configuration file (.conf). Tomake the component available in the Component Window in SoC Designer Canvas, performthe following steps:1. Launch SoC Designer Canvas.2. From the File menu, select Preferences.3. Click on Component Library in the list on the left.4. Under the Additional Component Configuration Files window, click Add.5. Browse to the location where the SoC Designer Plus model is located and select thecomponent configuration file:– maxlib.lib.conf (for Linux)– maxlib.lib.windows.conf (for Windows)6. Click OK.7. To save the preferences permanently, click the OK & Save button.The component is now available from the SoC Designer Plus Component Window.Carbon Design Systems, Inc. Confidential

Adding and Configuring the SoC Designer Plus Component 1-51.2.3 Adding the Component to the SoC Designer CanvasLocate the component in the Component Window and drag it out to the Canvas. An AHB-Lite version and two AXI versions are shown in Figure 1-1.Figure 1-1 PL390 Generic Interrupt Controller Components in SoC Designer PlusThe AHB-Lite component has been created with legacy mode.The middle AXI component was created in AMBA Designer without any additional features.The last AXI component was created with four CPU interfaces, with legacy mode,with multiple PPIs, and with the security extensions.Carbon Design Systems, Inc. Confidential

1-6 Using the Model Kit Component in SoC Designer Plus1.3 Available Component ESL PortsTable 1-2 describes the PL390 ESL ports that are exposed in SoC Designer Plus when youhave defined an AHB-Lite component. See the ARM PrimeCell® Generic Interrupt Controller(PL390) Technical Reference Manual for more information.Each AHB-Lite or AXI signal uses a suffix to identify the interface; either d for Distributoror c for CPU interface.Table 1-2 AHB-Lite ESL Component PortsESL Port Description Direction Typeahb_c AHB-Lite slave for the CPU interface. Input Transaction slaveahb_d AHB-Lite slave for the distributor. Input Transaction slavegresetReset for the GIC. This signal is active HIGH Input Signal slaveby default.legacy_irq_c0 Legacy IRQ interrupt for CPU interface. Availableonly if legacy has been configured. Activehigh/low is controlled by the negLogicparameter. This signal is active HIGH bydefault.Input Signal slavespi Shared peripheral interrupt inputs. Input Signal slaveclk-in Clock slave port. Input Clock slaveirq_c0IRQ interrupt for the processor that connects tothe CPU interface. Active high/low is controlledby the negLogic parameter. This signalis active HIGH by default.Output Signal masterTable 1-3 describes the PL390 ESL ports that are exposed in SoC Designer Plus when youhave defined an AXI component. This configuration supports security extensions and cancontain up to 8 CPU interfaces. Some other ports appear only when the GIC has been configuredwith certain functionality in AMBA Designer.Table 1-3 AXI ESL Component PortsESL Port Description Direction Typeaxi_c AXI slave for the CPU interface. Input Transaction slaveaxi_d AXI slave for the distributor. Input Transaction slaveenable_c 1 Provides a mask select to access registers in aCPU interface. Available only if more thanone processor has been configured.Input Signal slaveenable_d 1gresetProvides a mask select to access banked registersin the Distributor. Available only if morethan one processor has been configured.Reset for the GIC. This signal is active HIGHby default.InputInputSignal slaveSignal slaveCarbon Design Systems, Inc. Confidential

Available Component ESL Ports 1-7legacy_fiq_c 1legacy_irq_c 1match_c 1match_d 1ppi_c 1Legacy FIQ interrupt for CPU interface .Available only if legacy and Security Extensionshave been configured. Active high/lowis controlled by the negLogic parameter.This signal is active HIGH by default.Legacy IRQ interrupt for CPU interface .Available only if legacy has been configured.Active high/low is controlled by the neg-Logic parameter. This signal is active HIGHby default.The result from the enable_c mask select iscompared with this signal. Available only ifmore than one processor has been configured.The result from the enable_d mask select iscompared with this signal. Available only ifmore than one processor has been configured.Private peripheral interrupt (PPI) inputs.Available only if more than one processor andmore than one PPI have been configured.InputInputInputInputInputSignal slaveSignal slaveSignal slaveSignal slaveSignal slavespi Shared peripheral interrupt inputs. Input Signal slaveclk-in Clock slave port. Input Clock slavefiq_c 1FIQ interrupt for the processor that connectsto CPU interface . Available only if SecurityExtensions have been configured. Activehigh/low is controlled by the negLogicparameter. This signal is active HIGH bydefault.Output Signal masterirq_c 1Table 1-3 AXI ESL Component Ports (Continued)ESL Port Description Direction TypeIRQ interrupt for the processor that connectsto the CPU interface . Active high/low iscontrolled by the negLogic parameter. Thissignal is active HIGH by default.1. represents the number of CPU interfaces, from 0 to7.OutputSignal masterAll pins that are not listed in this table have been either tied or disconnected for performancereasons.Note:Some ESL component port values can be set using a component parameter. Thisincludes the enable_c, enable_d, match_c, and match_d ports. In those cases, theparameter value will be used whenever the ESL port is not connected. If the portis connected, the connection value takes precedence over the parameter value.Carbon Design Systems, Inc. Confidential

1-8 Using the Model Kit Component in SoC Designer Plus1.4 Setting Component ParametersYou can change the settings of all the component parameters in SoC Designer Canvas, andof some of the parameters in SoC Designer Simulator. To modify the Carbon component’sparameters:1. In the Canvas, right-click on the Carbon component and select Edit Parameters....You can also double-click the component. The Edit Parameters dialog box appears.Figure 1-2 Component Parameters Dialog Box2. In the Parameters window, double-click the Value field of the parameter that youwant to modify.3. If it is a text field, type a new value in the Value field. If a menu choice is offered,select the desired option.The parameters that are available for an AHB-Lite version of the PL390 are describedin Table 1-4. The parameters that are available for an AXI version are described inTable 1-5.Table 1-4 PL390 AHB-Lite Component ParametersParameter NameDescriptionAllowedValuesDefault Value Runtime 1ahb_c Align Dataahb_c Big EndianWhether halfword and byte transactionswill align data to the transactionsize for the ahb_c port. Bydefault, data is not aligned.Whether AHB data is treated as bigendian for the ahb_c port. Bydefault, data is not sent as bigendian.true, false false Notrue, false false NoCarbon Design Systems, Inc. Confidential

Setting Component Parameters 1-9Table 1-4 PL390 AHB-Lite Component Parameters (Continued)Parameter NameDescriptionAllowedValuesDefault Value Runtime 1ahb_c Enable DebugMessagesahb_c FilterHREADYINWhen set to true, writes ahb_c debugmessages onto the SoC DesignerPlus output window.Whether the HREADYIN signal isfiltered to prevent it from reachingthe Carbon Model.true, false false Yestrue, false false Noahb_c region size 0 Region size of the ahb_c interface. 0 -0x100000000 No0xFFFFFFFFahb_c region size [1-5] Unused 0 -0x0No0xFFFFFFFFahb_c region start 0 Base address of the ahb_c interface. 0x0 - 0xffffffff 0x0 Noahb_c region start [1-5] Unused 0x0 - 0xffffffff 0x0 Noahb_c Subtract BaseAddressahb_c Subtract BaseAddress Dbgahb_d Align Dataahb_d Big Endianahb_d Enable DebugMessagesahb_d FilterHREADYINWhether the Base Address parameteris subtracted from the actual transactionaddress before being passed tothe component. By default, the transactionaddress is passed directly tothe component.Same description as for ahb_c SubtractBase Address, except this is fordebug transactions.Whether halfword and byte transactionswill align data to the transactionsize for the ahb_d port. Bydefault, data is not aligned.Whether AHB data is treated as bigendian for the ahb_d port. Bydefault, data is not sent as bigendian.When set to true, writes ahb_ddebug messages onto the SoCDesigner Plus output window.Whether the HREADYIN signal isfiltered to prevent it from reachingthe Carbon Model.true, false false Notrue, false true Notrue, false false Notrue, false false Notrue, false false Yestrue, false false Noahb_d region size 0 Region size of the ahb_d interface. 0 -0x100000000 No0xFFFFFFFFahb_d region size [1-5] Unused 0 -0x0No0xFFFFFFFFahb_d region start 0 Base address of the ahb_d interface. 0x0 - 0xffffffff 0x0 Noahb_d region start [1-5] Unused 0x0 - 0xffffffff 0x0 NoCarbon Design Systems, Inc. Confidential

1-10 Using the Model Kit Component in SoC Designer PlusTable 1-4 PL390 AHB-Lite Component Parameters (Continued)Parameter NameDescriptionAllowedValuesDefault Value Runtime 1ahb_d Subtract BaseAddressahb_d Subtract BaseAddress DbgAlign WaveformsCarbon DB PathDump WaveformsEnable DebugMessagesnegLogicWhether the Base Address parameteris subtracted from the actual transactionaddress before being passed tothe component. By default, the transactionaddress is passed directly tothe component.Same description as for ahb_d SubtractBase Address, except this is fordebug transactions.When set to true, waveformsdumped from the Carbon componentare aligned with the SoC DesignerPlus simulation time. The resetsequence, however, is not includedin the dumped data.When set to false, the reset sequenceis dumped to the waveform data,however, the Carbon componenttime is not aligned with the SoCDesigner Plus time.Sets the directory path to the Carbondatabase file.Whether SoC Designer Plus dumpswaveforms for this component.When set to true writes the debugmessages onto the SoC DesignerPlus output window.Sets IRQ/FIQ assertion to use negativelogic. Default of false means0=off and 1=on. True means 0=onand 1=off.true, false false Notrue, false true Notrue, false true NoNot used empty Notrue, false false Yestrue, false false Yestrue, false false YesWaveform File 2 Name of the waveform file. string carbon_PL390.fsdbWaveform TimescaleSets the timescale to be used in thewaveform.Many values indrop-downNo1 ns No1. Yes means the parameter can be dynamically changed during simulation, No means it can be changed onlywhen building the system, Reset means it can be changed during simulation, but its new value will be takeninto account only at the next reset.2. When enabled, SoC Designer Plus writes accumulated waveforms to the waveform file in the following situations:when the waveform buffer fills, when validation is paused and when validation finishes, and at the endof each validation run.Carbon Design Systems, Inc. Confidential

Setting Component Parameters 1-11The parameters that are available for an AXI version of the PL390 are described inTable 1-5.Table 1-5 PL390 AXI Component ParametersParameter NameDescriptionAllowedValuesDefault Value Runtime 1Align Waveformsaxi_c axi_size[0-5]axi_c axi_start[0-5]When set to true, waveformsdumped from the Carbon componentare aligned with the SoCDesigner Plus simulation time.The reset sequence, however, isnot included in the dumped data.When set to false, the resetsequence is dumped to the waveformdata, however, the Carboncomponent time is not alignedwith the SoC Designer Plus time.true, false true NoThese parameters are obsoleteand should be left at their defaultvalues. 2 n/a size0 default is0x100000000,size1-5 default is0x00x00000000NoNoaxi_c Enable DebugMessagesaxi_d axi_size[0-5]axi_d axi_start[0-5]When set to true, writes axi_cdebug messages onto the SoCDesigner Plus output window.true, false false YesThese parameters are obsoleteand should be left at their defaultvalues. 3 n/a size0 default is0x100000000,size1-5 default is0x00x00000000NoNoaxi_d Enable DebugMessagesCarbon DB PathDump WaveformsWhen set to true, writes axi_ddebug messages onto the SoCDesigner Plus output window.Sets the directory path to the Carbondatabase file.Whether SoC Designer Plusdumps waveforms for this component.true, false false YesNot used empty Notrue, false false Yesenable_c 4 Sets the enable_c value. 0x0 - 0xffffffff 0x0 Yesenable_d 3 Sets the enable_d value. 0x0 - 0xffffffff 0x0 YesEnable DebugMessagesWhen set to true writes the debugmessages onto the SoC DesignerPlus output window.true, false false YesCarbon Design Systems, Inc. Confidential

1-12 Using the Model Kit Component in SoC Designer PlusTable 1-5 PL390 AXI Component Parameters (Continued)Parameter NameDescriptionAllowedValuesDefault Value Runtime 1match_c 3 Sets the match_c value. 0x0 - 0xffffffff 0x0 Yesmatch_d 3 Sets the match_c value. 0x0 - 0xffffffff 0x0 YesnegLogicSets IRQ/FIQ assertion to usenegative logic. Default of falsemeans 0=off and 1=on. Truemeans 0=on and 1=off.true, false false YesWaveform File 5 Name of the waveform file. string carbon_PL390.fsdbWaveform TimescaleSets the timescale to be used inthe waveform.Many values indrop-downNo1 ns No1. Yes means the parameter can be dynamically changed during simulation, No means it can be changed onlywhen building the system, Reset means it can be changed during simulation, but its new value will be takeninto account only at the next reset.2. Carbon recommends using the Memory Map Editor (MME) in SoC Designer Plus, which provides centralizedviewing and management of the memory regions available to the components in a system. For informationabout migrating existing systems to use the MME, refer to Chapter 9 of the SoC Designer Plus User Guide.3. Carbon recommends using the Memory Map Editor (MME) in SoC Designer Plus, which provides centralizedviewing and management of the memory regions available to the components in a system. For informationabout migrating existing systems to use the MME, refer to Chapter 9 of the SoC Designer Plus User Guide.4. represents the number of CPU interfaces, from 0 to7.5. When enabled, SoC Designer Plus writes accumulated waveforms to the waveform file in the following situations:when the waveform buffer fills, when validation is paused and when validation finishes, and at the endof each validation run.Carbon Design Systems, Inc. Confidential

Debug Features 1-131.5 Debug FeaturesThe PL390 Generic Interrupt Controller model has a debug interface (CADI) that allowsthe user to view, manipulate and control the registers in the SoC Designer Simulator orany debugger that supports the CADI, for example, Model Debugger. A view can beaccessed in the SoC Designer Simulator or an instance of the Model Debugger can beattached by right clicking on the model and choosing the appropriate menu entry. Theviews shown in this section are for the SoC Designer Simulator.1.5.1 Register InformationFigure 1-3 shows the register view of the PL390 Generic Interrupt Controller model in theSoC Designer Simulator. Sub-fields can be accessed by clicking on the plus sign to the leftof a register name. Registers are grouped into different sets according to functional area.Figure 1-3 Registers ViewThe registers are described briefly in this section. See the ARM PrimeCell® Generic InterruptController (PL390) Technical Reference Manual and ARM Generic Interrupt ControllerArchitecture Specification for complete information.The following Register tabs are supported:• Distributor Configuration Registers• INTID Configuration Registers• Signal Status Registers• Control Registers• Implementor Registers• PrimeCell Configuration RegistersNote:All possible registers are shown on the following pages. Depending on how youconfigured the model in AMBA Designer, some of the registers may not be available.Carbon Design Systems, Inc. Confidential

1-14 Using the Model Kit Component in SoC Designer Plus1.5.1.1 Distributor Configuration RegistersTable 1-6 shows the Distributor Configuration registers. These registers are used to determinethe global configuration of the Distributor and control its operating state.Table 1-6 Distributor Configuration RegistersName Description Typeenable (Secure) Secure Interrupt Control Register (ICDICR) read-writeenable (Non-secure) Non-Secure Interrupt Control Register (ICDICR) read-writeic_type Interrupt Controller Type Register (ICDICTR) read-onlydist_identDistributor Implementor Identification Register(ICDDIIR)read-only1.5.1.2 INTID Configuration RegistersTable 1-7 shows the INTID Configuration registers. These registers provide the operatingparameters for each INTID.Table 1-7 INTID Configuration Registerssgi_security_if 1Name Description TypeInterrupt Security Register (ICDISR)1. represents the number of CPU interfaces, from 0 to7.2. represents the number of SPIs configured through AMBA Designer.read-writeppi_security_if 1 Interrupt Security Register (ICDISR) read-writespi_security 2Interrupt Security Register (ICDISR) read-writeppi_enable_if 1 Enable Set/Clear Register (ICDISER) read-writespi_enable 2 Enable Set/Clear Register (ICDISER) read-writesgi_pending_if 1 Pending Set/Clear Register (ICDISPR) read-onlyppi_pending_if 1 Pending Set/Clear Register (ICDISPR) read-onlyspi_pending 2 Pending Set/Clear Register (ICDISPR) read-onlysgi_active_if 1 Active Status Register (ICDABR) read-onlyppi_active_if 1 Active Status Register (ICDABR) read-onlyspi_active 2 Active Status Register (ICDABR) read-onlypriority_sgi__if 1 Priority Level Register (ICDIPR) read-writepriority_ppi__if 1 Priority Level Register (ICDIPR) read-writepriority_spi_ Priority Level Register (ICDIPR) read-writetargets_spi_ Target Register (ICDIPTR) read-writeCarbon Design Systems, Inc. Confidential

Debug Features 1-151.5.1.3 Signal Status RegistersTable 1-8 shows the Signal Status registers. These registers return the present logic statusof the ppi_c and spi inputs.Table 1-8 Signal Status RegistersName Description Typeppi_if 1spi 2PPI Status RegisterSPI Status Registerread-onlyread-only1. represents the number of CPU interfaces, from 0 to7.2. represents the number of SPIs configured through AMBA Designer.1.5.1.4 Control RegistersTable 1-9 shows the Control registers. Use these registers to control the operating state ofthe CPU Interface.Table 1-9 Control Registerscontrol (Secure) 1Name Description Typecontrol (Non-secure) 1Secure CPU Interface Control Register (ICCICR)Non-Secure CPU Interface Control Register(ICCICR)1. represents the number of CPU interfaces, from 0 to7.read-writeread-writepri_msk_c_ 1 Priority Mask Register (ICCIPMR) read-writebp_c (Secure) 1 Secure Binary Point Register (ICCBPR) read-writensbp_c (Non-secure) 1 Non-Secure Binary Point Register (ICCBPR) read-writealias_nsbp_c 1Aliased Binary Point Register (ICCABPR) for read-writesecure access1.5.1.5 Implementor RegistersTable 1-10 shows the Implementor registers. These registers identify the implementor, andrevision, of the CPU Interface.Table 1-10 Implementor RegistersName Description Typecpu_if_identCPU Interface Implementor Identification Register(ICCIIR)read-onlyCarbon Design Systems, Inc. Confidential

1-16 Using the Model Kit Component in SoC Designer Plus1.5.1.6 PrimeCell Configuration RegistersTable 1-11 shows the PrimeCell Configuration registers. These registers enable the identificationof system components by software.Table 1-11 PrimeCell Configuration RegistersName Description Typeperiph_id_0 Peripheral Identification Register 0 read-onlyperiph_id_1 Peripheral Identification Register 1 read-onlyperiph_id_2 Peripheral Identification Register 2 read-onlyperiph_id_3 Peripheral Identification Register 3 read-onlyperiph_id_4 Peripheral Identification Register 4 read-onlyperiph_id_5 Peripheral Identification Register 5 read-onlyperiph_id_6 Peripheral Identification Register 6 read-onlyperiph_id_7 Peripheral Identification Register 7 read-onlyperiph_id_8 (Distributor) Peripheral Identification Register 8 read-onlyperiph_id_8 (CPU Interface) Peripheral Identification Register 8 read-onlycomponent_id_ PrimeCell Identification Registers read-only1.6 Available Profiling DataThe PL390 model component has no profiling capabilities.Carbon Design Systems, Inc. Confidential