Carbon Cortex-A15 Model User Guide for SoC Designer

1-10 Using the Model Kit Component in SoC Designer PlusTable 1-4 Component Parameters (Continued)NameDescriptionAllowedValuesDefault Value Runtime 1Align Waveformsapb_dbg Base Addressapb_dbg Enable DebugMessagesapb_dbg Sizeaxi_m Enable DebugMessagesCarbon DB PathCFGENDCFGENDn 4CFGTECFGTEn 4When set to true, waveforms dumpedby the Carbon component are alignedwith the SoC Designer Plus simulationtime. The reset sequence, however,is not included in the dumpeddata.When set to false, the reset sequenceis dumped to the waveform data, however,the Carbon component time isnot aligned with SoC Designer Plustime.Start of the apb_dbg port addressregiontrue, false true NoAddress 0x0 NoEnable apb_dbg port debug true,false false YesSize of the apb_dbg port addressregionSize 0x100000000 NoEnable axi_m port debug true,false false YesSets the directory path to the Carbondatabase file.Endianess configuration. 1-bit widefor UP, 4 bits wide for MP. Automaticallykept in sync with CFGENDn.Endianess configuration. Per-corevalue of CFGEND; automaticallykept in sync with CFGEND.Default exception handling state(ARM/Thumb). 1-bit wide for UP, 4bits wide for MP. Automatically keptin sync with CFGTEn.Default exception handling state(ARM/Thumb). Per-core value ofCFGTE; automatically kept in syncwith CFGTE.Not Used empty Nointeger 0 Nobool false Nointeger 0 Nobool false NoCLUSTERID Cluster ID in MPIDR[11:8]. integer 0 NoDump Waveforms Whether SoC Designer Plus dumps bool false Yeswaveforms for this component.Enable Debug MessagesIMINLNWhether debug messages are loggedfor the component.Instr Cache minimum line size(0=32,1=64-byte)bool false Yesinteger 1 NoCarbon Design Systems, Inc. Confidential