Carbon Cortex-A15 Model User Guide for SoC Designer

1-16 Using the Model Kit Component in SoC Designer PlusTable 1-7 Control Registers (Continued)DL1DATA1 Data L1 Data1 Register Read/WriteDL1DATA2 Data L1 Data2 Register Read/WriteDL1DATA3 Data L1 Data3 Register Read/WriteL2ACTLR L2 Cache Auxiliary Control Read/WriteL2ECTLR L2 Extended Control Register Read/WriteL2PFR L2 Prefix Control Register Read/WriteCBAR Configuration Base Address Register Read/WriteVPIDR Virtualization Process ID Read/WriteVMPIDR Virtualization Multiprocessor ID Read/WriteHSCTLR Hypervisor System Control Read/WriteHCR Hypervisor Configuration Register Read/WriteHDCR Hypervisor Debug Configuration Register Read/WriteHCPTR Hypervisor Coprocessor Trap Register Read/WriteHSTR Hypervisor System Trap Register Read/WriteHTCR Virtualization Translation Control Read/WriteVTCR Virtualization Translation Control Read/WriteHADFSRHypervisor Auxiliary Data Fault Status SyndromeRead/WriteHAIFSRName Description AccessHypervisor Auxiliary Instruction Fault StatusSyndromeRead-OnlyHSR Hypervisor Syndrome Read/WriteHDFAR Hypervisor Data Fault Address Read/WriteHIFAR Hypervisor Instruction Fault Address Read/WriteHPFAR Hypervisor IPA Fault Address Read/WriteHMAIR0 Hypervisor Memory Attribute Indirection Read/WriteHMAIR1 Hypervisor Memory Attribute Indirection Read/WriteHVBAR Hypervisor Vector Base Address Read/WriteHTPIDR Hypervisor Software Thread ID Read/WriteCNTPCT Physical Count Read/WriteCNTVCT Physical Count - Virtual Offset Read/WriteCNTP_CVAL Physical Compare Value Read/WriteCNTV_CVAL Virtual Compare Value Read/WriteCNTVOFF Virtual Offset Read/WriteCNTHP_CVAL Virtual Compare Value Read/WriteCarbon Design Systems, Inc. Confidential