Carbon UART PL011 Model User Guide for SoC Designer

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1-8 Using the Model Kit Component in SoC Designer Plus1.3 Available Component ESL PortsTable 1-2 describes the ESL ports that are exposed in SoC Designer Plus Plus. See theARM PrimeCell® UART (PL011) Technical Reference Manual for more information.Table 1-2 ESL Component PortsESL Port Description Direction TypePRESETn Bus reset signal, active LOW. Input Reset controllerRXD1-bit port for receiving data from signal master Input Signal Slaveport. The data received via this port is pushedinto Rx FIFO UART.UARTCLKClock input for UART.Input Clock SlaveNote: This clock input must be connected to thesame clock that is used for clk-in. If clkinis left unconnected then this clockinput must also be unconnected.UARTRXDMACLR Receive DMA Clear Input Signal SlaveUARTTXDMACLR Transmit DMA Clear Input Signal SlaveapbAllows the user to program the memory-mappedregisters. This interface is expected to be connectedto an APB-compliant device. This interfaceis clocked by the clk-in port.Input TransactionSlavenUARTRSTclk-inTXDUART reset signal to UARTCLK clock domain,active LOW.The reset controller must use PRESETn to assertnUARTRST asynchronously but negate it synchronouslywith UARTCLK.Input clock port. This component and the APBport are clocked at the frequency of the clockconnected to this port. If the clk-in port is notconnected, clock frequency is taken from SoCDesigner Plus System Properties.Note: This clock input must be connected to thesame clock that is used for UARTCLK, or ifUARTCLK is unconnected then clk-in must alsobe unconnected.1-bit port for transmitting data to connected signalslave port. The data transmitted via this portis popped out of Tx FIFO of UART.InputInputOutputReset TransactorClock SlaveSignal MasterUARTRXDMABREQ Receive DMA Burst Request Output Signal MasterUARTRXDMASREQ Receive DMA Single Request Output Signal MasterUARTTXDMABREQ Transmit DMA Burst Request Output Signal MasterUARTTXDMASREQ Transmit DMA Single Request Output Signal MasterCarbon Design Systems, Inc. Confidential
Available Component ESL Ports 1-9Table 1-2 ESL Component Ports (Continued)ESL Port Description Direction TypeintpProvides interrupts to the interrupt controller.The value contains the interrupt number andextended value (interrupt low or high). You canspecify unique interrupt numbers for each interruptsupported via parameters – see Table 1-3on page 1-10 for more details.OutputInterrupt MasternSIROUTTransmitted Serial Data Output, active LOW. Inthe idle state, this signal remains LOW (themarking state).OutputSignal MasterWhen this signal is HIGH, an infrared light pulseis generated that represents a logic 0 (spacingstate).nUARTDTRData Terminal Ready modem status output,active LOW. The reset value is 0.OutputSignal MasternUARTRTSRequest to Send modem status output, activeLOW. The reset value is 0.OutputSignal MasternUARTOut1Out1 modem status output, active LOW. Thereset value is 0.OutputSignal MasternUARTOut2Out2 modem status output, active LOW. Thereset value is 0.OutputSignal MasterAll pins that are not listed in this table have been either tied or disconnected for performancereasons.Carbon Design Systems, Inc. Confidential
Page 1 and 2: Carbon UART PL011 ModelUser Guide f
Page 3 and 4: Technical SupportIf you have questi
Page 5 and 6: ContentsPrefaceAbout This Guide . .
Page 7: PrefaceA Carbon Model component is
Page 13 and 14: PL011 UART Model Functionality 1-31
Page 15: PL011 UART Model Functionality 1-51
Page 20 and 21: 1-10 Using the Model Kit Component
Page 22: 1-12 Using the Model Kit Component
Page 25 and 26: Debug Features 1-151.5.1.1 General
Page 27 and 28: Available Profiling Data 1-171.6 Av

Carbon UART PL011 Model User Guide for SoC Designer

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