Carbon UART PL011 Model User Guide for SoC Designer

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1-10 Using the Model Kit Component in SoC Designer Plus1.4 Setting Component ParametersYou can change the settings of all the component parameters in SoC Designer Canvas, andof some of the parameters in SoC Designer Simulator. To modify the Carbon component’sparameters:1. In the Canvas, right-click on the Carbon component and select Edit Parameters....You can also double-click the component. The Edit Parameters dialog box appears.Figure 1-2 Component Parameters Dialog Box2. In the Parameters window, double-click the Value field of the parameter that youwant to modify.3. If it is a text field, type a new value in the Value field. If a menu choice is offered,select the desired option. The parameters are described in Table 1-3.Table 1-3 Component ParametersName Description Allowed Values Default Value Runtime 1Align Waveformsapb Base AddressWhen set to true, waveforms dumpedfrom the Carbon component are alignedwith the SoC Designer Plus simulationtime. The reset sequence, however, is notincluded in the dumped data.When set to false, the reset sequence isdumped to the waveform data, however,the Carbon component time is notaligned with the SoC Designer Plustime.Base address for APB region accessedvia APB slave port of UART.true, false true No0x00000000 -0xFFFFFFFF0x0NoCarbon Design Systems, Inc. Confidential
Setting Component Parameters 1-11apb EnableDebug MessagesEnable or disable debug messages. true, false false Yesapb Size Address range size. 0x00000000 -0xFFFFFFFFCarbon DB PathClone Output toConsole?Dump WaveformsEnable DebugMessagesintp int_1 idintp int_2 idintp int_3 idintp int_4 idintp int_5 idintp int_6 idTable 1-3 Component Parameters (Continued)Name Description Allowed Values Default Value Runtime 1Sets the directory path to the Carbondatabase file.The output of TXD port or file or Socketis also displayed on SoC Designer Plusconsole window.Whether SoC Designer Plus dumpswaveforms for this component.0x10000000NoNot Used empty Notrue, false false Notrue, false false YesEnable or disable debug messages. true, false false YesThe Intr value. It is the combined interruptof Rx_int, Tx_int, Receive timeoutinterrupt, and Overflow error interrupt.Always comes on “Intp” signal masterport after the individual interrupt hascome. Both come in same simulationcycle. Associated with UARTINTR.The Rx_int number. Rx FIFO tide interruptnumber. Associated with UARTRX-INTR.The Tx_int number. Tx FIFO tide interruptnumber. Associated with UARTTX-INTR.The Receive Timeout Interrupt Number.Interrupt number for receive timeoutinterrupt. Associated with UAR-TRTINTR.The Overflow Error Interrupt Number.Interrupt number for overflow error –which could occur on Rx FIFO. Associatedwith UARTEINTR.Interrupt controller UART modem statusinterrupt. Associated with UARTM-SINTR.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.Integer within arange. 2-1 indicates interruptis disabled.1 Yes2 Yes3 Yes4 Yes5 Yes6 YesCarbon Design Systems, Inc. Confidential
Page 1 and 2: Carbon UART PL011 ModelUser Guide f
Page 3 and 4: Technical SupportIf you have questi
Page 5 and 6: ContentsPrefaceAbout This Guide . .
Page 7: PrefaceA Carbon Model component is
Page 13 and 14: PL011 UART Model Functionality 1-31
Page 15: PL011 UART Model Functionality 1-51
Page 18 and 19: 1-8 Using the Model Kit Component i
Page 22: 1-12 Using the Model Kit Component
Page 25 and 26: Debug Features 1-151.5.1.1 General
Page 27 and 28: Available Profiling Data 1-171.6 Av

Carbon UART PL011 Model User Guide for SoC Designer

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