Carbon Cortex-A9 Model User Guide for SoC Designer

Setting Component Parameters 1-9Table 1-3 Component ParametersNameDescriptionAllowedValuesDefault Value Runtime 1ACLKENS Bus clock enable. integer 1 YesAlign Waveforms When set to true, waveforms dumpedby the Carbon component are alignedwith the SoC Designer Plus simulationtime. The reset sequence, however,is not included in the dumpeddata.When set to false, the reset sequenceis dumped to the waveform data, however,the Carbon component time isnot aligned with SoC Designer Plustime.true, false true Noapb_dbg BaseAddressapb_dbg EnableDebug MessagesBase address 0x0 – 0xffffffff 0x0 NoWhether debug messages are loggedfor the APB port.apb_dbg Size Size 0x0 –0x100000000axi_m0 Enable DebugMessagesaxi_m1 Enable DebugMessagesaxi_s axi_size0axi_s axi_size[1-5]axi_s axi_start[0-5]axi_s Enable DebugMessagesCarbon DB PathWhether debug messages are loggedfor master port 0.Whether debug messages are loggedfor master port 1.These parameters are obsolete andshould be left at their default values. 2Whether debug messages are loggedfor the slave port.Sets the directory path to the Carbondatabase file.true, false false Yes0x100000000Notrue, false false Yestrue, false false Yes0x1000000000x00x00000000CFGEND Endianness configuration. 0 — 0xF forMPCore0,1 for UNICoreCFGNMFI Enables fast interrupts. 0 — 0xF forMPCore0,1 for UNICoreCLUSTERIDCP15SDISABLEValue read in Cluster ID register field,bits[11:8] of the MPIDR.Disables write access to some systemcontrol processor registers.0x1000000000x00x00000000Notrue, false false YesNot Used empty No0 NofalseNo0-15 0 No0 — 0xF forMPCore0,1 for UNICore0 YesCarbon Design Systems, Inc. Confidential