Carbon Cortex-A9 Model User Guide for SoC Designer

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1-26 Using the Model Kit Component in SoC Designer Plus1.6 Available Profiling DataProfiling data is enabled, and can be viewed using the Profiling Manager, which is accessiblevia the Debug menu in the SoC Designer Simulator. Both hardware and softwarebased profiling is available.1.6.1 Hardware ProfilingHardware profiling includes several streams per processor core. The Cortex-A9 modelsets PMCR[4] to 1 to enable Hardware Profiling. This is done at reset time.Table 1-20 shows:• The event names supported by each stream, including event numbers as specified inthe ARM TRM.• The ARM silicon version for the Cortex A9 model.Table 1-20 Cortex-A9 Profiling EventsStream Event Name VersionsI-Cache Cache Miss (0x01) r1p1, r1p2, r2p0, r2p2D-Cache Cache Miss (0x03) r1p1, r1p2, r2p0, r2p2Cache Access (0x04)Data Read (0x06)Data Write (0x07)Data Eviction (0x65)Java Java Byte Code executed (0x40) r1p1, r1p2, r2p0, r2p2Software Java Byte Code executed (0x41)Jazelle backward branch executed (0x42)Memory STREX Passed (0x63) r1p1, r1p2, r2p0, r2p2STREX Failed (0x64)TLB Instr uTLB Miss (0x02) r1p1, r1p2, r2p0, r2p2Data uTLB Miss (0x05)Stall TLB Miss Stall (0x62) r1p1, r1p2, r2p0, r2p2DCache Miss Stall (0x61)ICache Miss Stall (0x60)PLD Stall (0x80)r2p0 and newerWrite Stall (0x81)Instruction Main TLB Miss Stall (0x82)Data Main TLB Miss Stall (0x83)Instruction uTLB Miss Stall (0x84)Data uTLB Miss Stall (0x85)DMB Stall (0x86)Carbon Design Systems, Inc. Confidential
Available Profiling Data 1-27Table 1-20 Cortex-A9 Profiling Events (Continued)Stream Event Name VersionsSoftware Decoded Instructions (0x68) r1p1, r1p2, r2p0, r2p2Exceptions Taken (0x09)Exceptions Returned (0x0A)Write Context ID (0x0B)Software change of PC (0x0C)Immediate Branch (0x0D)Predictable Function Returns (0x6E)Unaligned Access (0x0F)Mispredicted Branch (0x10)Predictable Branches (0x12)Coherent Line Fill Miss (0x50)Coherent Line Fill Hit (0x50)ISB (0x90)r1p1 and newerDSB (0x91)DMB (0x92)Issue does not dispatch any instruction(0x66)Issue is empty (0x67)Main Execution Unit Pipe (0x70)Second Execution Unit Pipe (0x71)Load/Store Pipe (0x72)FPU Instructions (0x73)Neon Instructions (0x74)Misc Integer core clock disabled (0x8A) r2p0 and newerData Engine clock disabled (0x8B)External interrupt (0x93)PLE Cache Line request completed (0xA0) r2p0 and newerCache Line request skipped (0xA1)FIFO Flush (0xA2)Request completed (0xA3)FIFO Overflow (0xA4)Request programmed (0xA5)Carbon Design Systems, Inc. Confidential
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Carbon Cortex-A9 Model User Guide for SoC Designer

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