FTGPIO010 - Faraday Technology Corporation

FTGPIO010
GENERAL PURPOSE INPUT / OUTPUT
Version 1.4 | October 2006
Key Features
General Description
• Speed: 66 MHz APB clock rate
• Compliant with AMBA Specification Rev 2.0
• Up to 32 independent input, output and
output enable buses for bi-directional I/O
pins
• Each port can be programmed as a bypass
pin
• Each port can separately trigger GPIO
interrupt when INTR option is set and
programmed as an input pin
• Each port interrupt generation can be
triggered by rising edge, falling edge, rising
and falling edges, and high / low levels
when INTR option is set
Faraday’s General Purpose Input / Output (FTGPIO010) is a flexible,
configurable and programmable general-purpose I/O controller. It provides
INTR and PULL options to remove or add the interrupt sense, bouncing clock,
and pull high/low circuits. Each GPIO pin's attributes, like input/output,
bypass, interrupt sense, clock source and pull type can be programmed to fit
user specification.
When programmed to be an interrupt input controller, the GPIO supports
rising edge, falling edge, rising and falling edges, and high/low level interrupt
sense types. The interrupt sense type varies with different device
requirements. The GPIO also provides a bouncing clock for de-bounce input
usage. The bounce period can be set to fit different requirements. Each pin
can be programmed to choose bus clock or bouncing clock. Faraday’s GPIO
provides up to 32 programmable I/O ports and each port can be
independently programmed.
• Each port can be pulled high or pulled low
when PULL option is set (I/O pad
programming required)
Functional Blocks
• Each interrupt port can choose Bounce or
PCLK clock source when INTR option is set
• Output data bit can be set or cleared
separately
• All ports are set by default to input after
AMBA APB Interface
Register Block
Mode Control
In / out Control
Data Register
PinBypass [gn:0 ]
PinDir [n:0]
GpioDataOut [gn:0]
GpioDataIn [gn:0]
I/O
Mux
Bypass
Mux
gpio_bpsout [gn:0]
gpio_bpsin [gn:0]
gpio_bpsen [gn:0]
gpio_en [gn:0]
gpio_out [gn:0]
gpio_in [gn:0]
hardware reset
Interrupt
Control
Registers
Bounce
Control
Registers
BLCK
Interrupt Detection
Logic
Detect Logic
Bounce Clock Logic
gpio_intr
gpio_mis [gn:0]
Pull
Control
Registers
Pull High or Pull Down
Logic
Detect Logic
gpio_pullup [gn:0]
Gpio_pulldown [gn:0]

FTGPIO010
GENERAL PURPOSE INPUT / OUTPUT
Version 1.4 | October 2006
Block Descriptions
APB Interface
The APB interface accepts standard APB bus signals. It services read / write requirements from the APB bus. When the
psel is active, the APB interface decodes the paddr to select one register. The pwrite signal indicates read or write
operation. If the pwrite signal indicates write, the pwdata will be written to the selected register. If the pwrite signal
indicates read, then the selected register will be read out to prdata.
Register Block
The register block includes data input / output registers, GPIO control registers, interrupt detection status registers,
interrupt control registers, bounce clock period register, bounce clock control registers, pull type registers and pull control
registers. The user can read or write these registers to control GPIO, interrupt detection, pull high / low, bouncing clock
and input / output data.
Input / Output
The pin directory controls the input / output MUXs. When a pin is programmed as an output pin, the output data are muxed
out to the gpio_out pin. When a pin is programmed as an input pin, the gpio_in pin is muxed into the input data register.
Interrupt Detection
The interrupt detection block handles the interrupt detection function. When the INTR option is defined, interrupt enable
is set and the pin is programmed as an interrupt input port, this block will be active.
Faraday’s GPIO supports rising edge, falling edge, rising and falling edges, and high / low level interrupt detection. Raw
status of the interrupt detection is put in the IntrRawState registers and masked status of the interrupt detection is put in
the IntrMaskedState registers. When the interrupt detection block senses an interrupt, gpio_intr will be triggered. The
programmer can judge the interrupt source through the gpio_mis [gn : 0] ports.
Bounce Clock
The bounce clock block provides a bouncing clock for each GPIO pin. When INTR option is defined and bounce enable is
set, this block will be active
If the pin is programmed as an interrupt input sense port, the pin can choose the bouncing clock as the clock source. The
bouncing clock is used to de-bounce the interrupt source. The default period of the bouncing clock is set to 0x7CF.
.

FTGPIO010
GENERAL PURPOSE INPUT / OUTPUT
Version 1.4 | October 2006
Pull High / Low
The pull high / low block can pull the pad high or low. When PULL option is defined and pull enable is set, this block will
be active.
This function requires programming of the I/O pad.
Bypass Architecture Diagram
PinDir [0]
0
1
GpioDataOut [0]
0
PAD [0]
1
PRDATA [0]
GpioDataIn [0]
gpio_bpsen [0]
gpio_bpsin [0]
gpio_bpsout [0]
PinBypass [0]
To support the bypass mode, two MUXs and one AND gate should be added. The PinBypass register controls the bypass
mode. If PinBypass [0] is set, it means that pin [0] is in bypass mode and all PAD [0] inputs / outputs are controlled by
gpio_bpsin [0], gpio_bpsen [0] and gpio_bpsout [0]. Please refer to the above figure. When the PinBypass [0] register
is set, gpio_bpsen [0] will be muxed to PAD [0] output enable, which means that gpio_bpsen [0] can determine the pin
direction directly. Similarly, in bypass mode, gpio_bpsin [0] is directly muxed to the PAD [0] output and the PAD [0] input
is directly connected to gpio_bpsout [0].

FTGPIO010
GENERAL PURPOSE INPUT / OUTPUT
Version 1.4 | October 2006
Signal Descriptions
gpio_bpsout [gn:0]
PCLK
PRSTn
psel
penable
pwrite
paddr [6:2]
pwdata [gn:0]
prdata [gn:0]
GPIO
Module
gpio_bpsin [gn:0]
gpio_bpsen [gn:0]
gpin_en [gn:0]
gpio_out [gn:0]
gpio_in [gn:0]
gpio_pullup [gn:0]
gpio_pulldown [gn:0]
gpio_intr
gpio_mis [gn:0]
AMBA APB Signal Descriptions
Signal Name Direction Description
PCLK I AMBA APB clock, used to time all bus transfers
PRSTn I AMBA APB reset signal, active LOW
psel I GPIO select signal from the APB bus. When set to 1, this signal indicates that the slave
device is selected by the AMBA APB bridge, and that a data transfer is required.
penable I AMBA APB enable signal
pwrite I AMBA APB transfer direction signal. It indicates a write access when HIGH, and a read
access when LOW.
paddr I AMBA APB address bus
pwdata I AMBA APB write data bus
prdata O AMBA APB read data bus

FTGPIO010
GENERAL PURPOSE INPUT / OUTPUT
Version 1.4 | October 2006
FTGPIO010 Signal Descriptions
Signal Name Direction Description
gpio_in I GPIO data input pin
gpio_out O GPIO data output pin
gpio_en O GPIO data output enable pin, active HIGH
gpio_pullup O GPIO output pad pullup
gpio_pulldown O GPIO output pad pulldown
gpio_intr O GPIO interrupt. When high, this signal indicates that a valid match has occurred between
any of the interrupts.
gpio_mis O GPIO masked interrupt status. A high of the lines indicates that a valid match has
occurred between the interrupt set of registers and the signals on the corresponding pads.
gpio_bpsin I GPIO bypass input. Data bypass input signal, which controls pad output data and APB
read data.
gpio_bpsen I GPIO bypass enable. Data bypass output enable signal, which controls pad direction
when PinBypass is set.
gpio_bpsout O GPIO bypass output. Data bypass output signal, which passes data from gpio_bpsin
when PinBypass is set.

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