sn74lv245at octal bus transceiver with 3state outputs - CNC4PC

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V V CC Operation
Typical t pd of 3.5 ns at 5 V
Typical V OLP (Output Ground Bounce)
2.3 V at V CC = 5 V, T A = 25°C
Supports Mixed-Mode Voltage Operation on
All Ports
SCLS605A − DECEMBER 2004 − MARCH 2005
I off Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 1000-V Charged-Device Model (C101)
DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
DIR
B8 V
1 20
10 11
GND
CC
19
18
17
16
15
14
13
12
OE
B1
B2
B3
B4
B5
B6
B7
description/ordering information
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The
control-function implementation minimizes external timing requirements.
The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to
disable the device so that the buses are effectively isolated.
TA
ORDERING INFORMATION
PACKAGE†
ORDERABLE
PART NUMBER
QFN − RGY Tape and reel SN74LV245ATRGYR LV245A
SOIC − DW
Tube
Tape and reel
SN74LV245ATDW
SN74LV245ATDWR
TOP-SIDE
MARKING
LV245A
−40°C to 85°C SOP − NS Tape and reel SN74LV245ATNSR 74LV245A
SSOP − DB Tape and reel SN74LV245ATDBR LV245A
TSSOP − PW Tape and reel SN74LV245ATPWR LV245AT
TVSOP − DGV Tape and reel SN74LV245ATDGVR LV245A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS605A − DECEMBER 2004 − MARCH 2005
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I off . The I off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
OE
FUNCTION TABLE
(each transceiver)
INPUTS
DIR
OPERATION
L L B data to A bus
L H A data to B bus
H X Isolation
logic diagram (positive logic)
DIR
1
19
OE
A1
2
18
B1
To Seven Other Channels
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SCLS605A − DECEMBER 2004 − MARCH 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †
Supply voltage range, V CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, V O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range applied in the high or low state, V O (see Notes 1 and 2) . . . . . . −0.5 V to V CC + 0.5 V
Input clamp current, I IK (V I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, I OK (V O < 0 or V O > V CC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, I O (V O = 0 to V CC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θ JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
MIN MAX UNIT
VCC Supply voltage 4.5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 V
VI Input voltage 0 5.5 V
VO
Output voltage
High or low state 0 VCC
3-state 0 5.5
IOH High-level output current VCC = 4.5 V to 5.5 V −16 mA
IOL Low-level output current VCC = 4.5 V to 5.5 V 16 mA
∆t/∆v Input transition rise or fall rate VCC = 4.5 V to 5.5 V 20 ns/V
TA Operating free-air temperature −40 85 °C
NOTE 5:
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3

SCLS605A − DECEMBER 2004 − MARCH 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC
VOH
VOL
TA = 25°C
TA = −40°C
TO 85°C
MIN TYP MAX MIN MAX
IOH = −50 µA 4.5 V 4.4 4.5 4.4
IOH = −16 mA 4.5 V 3.8 3.8
IOL = 50 µA 4.5 V 0 0.1 0.1
IOL = 16 mA 4.5 V 0.55 0.55
II VI = 5.5 V or GND 0 to 5.5 V ±0.1 ±1 µA
IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 µA
ICC VI = VCC or GND, IO = 0 5.5 V 2 20 µA
∆ICC † One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 mA
Ioff VI or VO = 0 to 5.5 V 0 0.5 5 µA
Ci Control inputs VI = VCC or GND 5 V 3 pF
Cio A or B port VO = VCC or GND 5 V 7 pF
† This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
TO
LOAD
TA = 25°C
(INPUT)
(OUTPUT) CAPACITANCE MIN TYP MAX
A or B B or A CL = 15 pF
OE A or B CL = 15 pF
OE A or B CL = 15 pF
UNIT
V
V
MIN MAX UNIT
3.1 4.9 7.7 1 8.5
2.3 4.9 7.7 1 8.5
3.5 9.4 13.8 1 15
3.7 9.4 13.8 1 15
3.5 3.9 7.5 1 8
2.6 3.9 7.5 1 8
tPLH
4.6 5.4 8.7 1 9.5
A or B B or A CL = 50 pF
tPHL
4.7 5.4 8.7 1 9.5
ns
tPZH
4.9 9.9 14.8 1 16
OE A or B CL = 50 pF
tPZL
5.3 9.9 14.8 1 16
ns
tPHZ
4.5 10.1 15.4 1 16.5
OE A or B CL = 50 pF
tPLZ
4.1 10.1 15.4 1 16.5
ns
tsk(o) CL = 50 pF 1 1 ns
ns
ns
ns
noise characteristics, V CC = 5 V, C L = 50 pF (see Note 6)
PARAMETER
TA = 25°C
MIN TYP MAX
UNIT
VOL(P) Quiet output, maximum dynamic VOL 1.1 1.5 V
VOL(V) Quiet output, minimum dynamic VOL −1.1 −1.5 V
VOH(V) Quiet output, minimum dynamic VOH 4 V
VIH(D) High-level dynamic input voltage 2 V
VIL(D) Low-level dynamic input voltage 0.8 V
NOTE 6: Characteristics are for surface-mount packages only.
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SCLS605A − DECEMBER 2004 − MARCH 2005
operating characteristics, V CC = 5 V, T A = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance Outputs enabled CL = 50 pF, f = 10 MHz 19 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5

SCLS605A − DECEMBER 2004 − MARCH 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
Test
Point
From Output
Under Test
CL
(see Note A)
RL = 1 kΩ
S1
VCC
Open
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
S1
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
Input
tw
1.5 V 1.5 V
3 V
0 V
Timing Input
Data Input
tsu
1.5 V
th
1.5 V 1.5 V
3 V
0 V
3 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
1.5 V 1.5 V
3 V
0 V
Output
Control
1.5 V 1.5 V
3 V
0 V
In-Phase
Output
Out-of-Phase
Output
tPLH
tPHL
50% VCC
50% VCC
tPHL
VOH
50% VCC
VOL
tPLH
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
50% VCC
50% VCC
tPLZ
VOL + 0.3 V
VOL
tPHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
≈VCC
VOH
VOH − 0.3 V
≈0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265