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1 - Al Kossow's Bitsavers

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CHAPTER<br />

2<br />

PRINCIPLES OF OPERATION<br />

TABLE OF CONTENTS<br />

Section<br />

2.1<br />

2.2<br />

2.2.1<br />

2.2.1.1<br />

2.2.1.2<br />

2.2.1.3<br />

2.2.2<br />

2.2.2.1<br />

2.2.2.2<br />

2.2.2.3<br />

2.2.2.4<br />

2.2.2.5<br />

2.3<br />

2.3.1<br />

2.3.1.1<br />

2.3.1.2<br />

2.3.1.3<br />

2.3.1.4<br />

2.3.2<br />

2.3.2.1<br />

2.3.3<br />

2.3.3.1<br />

2.3.3.2<br />

2.3.3.3<br />

2.3.3.4<br />

2.3.4<br />

2.3.4.1<br />

2.3.4.2<br />

2.3.5<br />

2.3.6<br />

2.3.6.1<br />

2.3.6.2<br />

2.3.6.3<br />

2.3.6.4<br />

2.3.7<br />

2.3.7.1<br />

2.3.7.2<br />

2.3.8<br />

Title<br />

MAIN SYSTEM UNIT COMPONENTS<br />

ATRPS POWER SUPPLY UNIT .<br />

Primary Oscillation Circuit .<br />

Power Supply Circuit .<br />

Overcurrent Prevention Circuit of the MOS-FET<br />

On-Off Control Circuit .<br />

Inrush Current Prevention Circuit .<br />

Secon da ry Ci rcuit .<br />

-5V and -12V Circuit .<br />

+12V Supply Circuit .<br />

+5V Supply Circuit .<br />

Overheating Prevention Circuit .<br />

Power Good Signal Generation Circuit .<br />

ANTA MAIN CONTROL BOARD OPERATION .<br />

System Clock Generation Circuit .<br />

Select CPU Operation Speed .<br />

LED Indications .<br />

Select NPX (80287) Operation Speed .<br />

Ose; 11 ator .<br />

System Reset Signal Generation Circuit .<br />

System Reset Circuit .<br />

Internal Memory Control Circuit .<br />

RAM Chip Type ••.•...•...•..••...•.•.....••••..••..••..<br />

RAf\1 Chip Addresses ...•....•...••..••......••......••..<br />

Jumper Connector Function .<br />

Operation of ~~emory Control Circuit .•.................<br />

Byte/Word Access & 16-8 Bit Data Conversion .<br />

Data Bus Control Signal on GAATDB .<br />

Circuit Operation of Data Conversion .<br />

1/0 Device Access Circuit .<br />

OMA Contral Circuit .<br />

Page Register Setting Circuit .<br />

8-bit DNA {Internal memory -- 1/0) .<br />

8-bit DMA (Internal memory -- Internal memory) .<br />

16-bit DMA (Internal memory -- 1/0) .<br />

Ready Signal Control Circuit .<br />

Insertion flore Wait Cycle .<br />

Zero Wait Cycl e Request .<br />

Command Delay Signal Control Circuit .<br />

Page<br />

2-1<br />

2-2<br />

2-2<br />

2-2<br />

2-4<br />

2-5<br />

2-6<br />

2-6<br />

2-7<br />

2-10<br />

2-13<br />

2-13<br />

2-19<br />

2-21<br />

2-21<br />

2-21<br />

2-22<br />

2-23<br />

2-25<br />

2-26<br />

2-28<br />

2-28<br />

2-29<br />

2-29<br />

2-29<br />

2-32<br />

2-32<br />

2-33<br />

2-41<br />

2-42<br />

2-42<br />

2-43<br />

2-43<br />

2-43<br />

2-48<br />

2-49<br />

2-49<br />

2-51

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