1 - Al Kossow's Bitsavers

EPSON pe AX
TECHNICAL MANUAL
Seiko Epson Corporation
Nagano,Japan
Y12699900201

Fce eOMPLIANCE STATEMENT
This equlpment uses and generates radio trequency energy and It not installed and used properly.
that Is In strlct accordance wlth the manutacture's Instructlons, may cause Interference to radio
and television receptlon.
It has been type tested and tound to comply wlth limits tor a Class B computlng devlce In
accordance wlth Sub- part J of Part 15 of FCC Rules, whlch are designed to provlde reasonable
protectlon agalnst such Interference in aresldential installation. However, there Is no guarantee
that Interference will not occur In a partlcular Installation. It thls equlpment dose causa
Interference to radio or television receptlon, whIch can be determlned by turnlng the equlpment
on and off, the user Is encouraged to try to correct the interference by one or more of the
tollowing measures:
reorlent the receivlng antenna
relocate the computer wlth respect to the receiver
move .the computer away tram the receiver
plug the computer into a different outtet so that the computer and receiver are on
different branch clrcults
It necessary, the user should consult the dealer or an experienced radio/television technician tor
additional suggestions. The user may tind the tollowing booklet, prepared by the Federal
Communicatlons Commlssion, helptul:
"How to Identity and Resoive Radio - TV interference Problems. ''This booklet Is avaiiable trom
the U.S. Government Printlng Office. Washington. D.C., 20402, Stock No. 044 - 000 - 00345 - 4.
You can determine whether your computer Is causing interference by turning It off. It the
Interference stops, it was probably caused by the computer or Its perlpheral devlces. To further
lsolate the problem. disconnect elther the perlpheral device or its 1/0 cable.
These devices usually require shielded cable. For Epson peripheral devices, you can obtaln the
proper shlelded cable trom your dealer. For non - Epson devlces. contact the manufacturer or
dealer tor asslstance.
Seiko Epson Corporatlon,
Nagano, Japan
© 1988 by Seiko Epson Corporation
All r1ghts reserved.
Prlnted In Japan
No portion of thls document may be reproduced, stored In a retrleval system, or transmitted In
any torm or by any means, electrlc. mechanlcal, photocopylng. recordlng, or otherwlse, wlthout
the written permission of Selko Epson Corporatlon. No patent liablllty Is assumed wlth respect
to use of the Information contalned herein, nor Is any liablllty assumed tor damages resultlng
trom usa cf thls text. Whlle every precautlon has been taken In the preparatlon cf thls bock,
the publlsher assumes no lIablllty tor errors or omisslons.
EPSON ® is a reglstered trademark of Seiko Epson Corporatlon.
EPSON PC AX Is trademark of Selko Epson Corporatlon.
IBM ® is a reglstered trademark ot International Business Machlnes Corporation.

PRECAUTIONS
Precautlonary notations throughout the text are categorlzed relative to 1) personalinjury and 2)
darnage to equlpment.
DANGER
WARNING
Signals a precautlon whlch, If ignored, could result In serlous or fatal
personalinjury. Great caution should be exercised in performlng procedures
preceded by DANGER Headlngs.
Signals a precaution whlch, If ignored, could result In damage to equlpment.
The precautlonary measures Itemlzed below should always be observed when performlng repalr/
rnalntenance procedures.
DANGER
1. ALWAYS DISCONNECT THE PRODUCT FROM BOTH THE POWER
SOURCE AND PERIPHERAL DEVICES PERFORMING ANY
MAINTENANCE OR REPAIR PROCEDURE.
2. NO WORD SHOULD BE PERFORMED ON THE UNIT BY PERSONS
UNFAMILIAR WITH BASIC SAFETY MEASURES AS DICTATED
FOR ALL ELECTRONICS TECHNICIANS IN THEIR L1NE OF WORK.
3. WHEN PERFORMING TESTING AS DICTATED WITHIN THIS
MANUAL, 00 NOT CONNECT THE UNIT TO APOWER SOURCE
UNTIL INSTRUCTED TO 00 SO. WHEN THE POWER SUPPLY
CABLE MUST BE CONNECTED, USE EXTREME CAUTION IN
WORKING ON POWER SUPPLY AND OTHER ELECTRONIC COM­
PONENTS.
WARNING
1. Repalrs on Epson product should be performed only by an Epsan
certlfled repair techniclan.
2. Make certeln that the source voltage is the same as the rated
voltage, Iisted on the serial number/rating plate. If the Epson
product has a primary AC rating different from avallable power
saurce, do not connect It to the power source.
3. Always verlfy that the Epson product has been disconnected from
the power source before removlng or replaclng prlnted circult
boards and/or Individual chips.
4. In order to protect sensitive microprocessors and clrcultry, use
static discharge equlpment, such as antl- static wrist straps, when
accesslng Internal components.
5. Replace rnalfunctlonlng components only wlth those components by
the manufacture; introductlon of second - source ICs or other nonapproved
components may damage the product and vold any
applicable Epson warranty.

REVISION ISSUE DATE REVISION PAGE
REV.A December 1986 -
REV.B September 1988 1-7, 2-2, 2-6, 2-7, 2-10,
2-15, 2-25, 2-33, 2-36,
2-39, 2-40, 2-42, 2-51,
2-73
Chapter 8 added

PREFACE
Thls manual descrlbes the theory of operation of the EPSON PC AX microcomputer system, and
Includes troubleshootlng, repair, and malntenance procedures for servlng system subassemblles.
Thls text Is dlvlded into eight chapters:
CHAPTER 1.
CHAPTER 2.
CHAPTER 3.
PRODUCT DESCRIPTION ... Descrlbesthe features and speclflcatlons of
the computer, lIIustrates system components. and IIsts the loglc conflguratlon
of the prlmary clrcult board.
PRINCIPLES OF OPERATION. " Details the functional organizatlon cf the
loglc clrcultry. Thls chapter also Illustrates the gate array pln
configuratlons.
OPTIONS . " Descrlbes option card speciflcatlons and the operating prlnclpies
of the options.
CHAPTER 4.
ProvIdes Instructions for isolating computer mal­
TROUBLESHOOTING . "
functlons.
CHAPTER 5.
CHAPTER 6.
CHAPTER 7.
CHAPTER 8.
DISASSEMBLY AND ASSEMBLY . .. Descrlbes system dlsassembly for
replacement of malfunctlonlng subassemblles.
ADJUSTMENT AND MAINTENANCE ... Usts the necessary adjustments for
unlt assembly and servlclng.
DIAGRAMS AND REFERENCE MATERIALS ... Descrlbes jumper settings
and connector pln asslgnments. Thls chapter also provldes expIoded clrcult
board layout and schematlc dIagrams for use In conjunctlon wIth the text.
DIFFERENCES BETWEEN 1OMHz AND 12 MHz ... Descrlbes between the
EPSON PC AX 10MHz and the 12MHz, and includes the schematics for use In
conJunctlon with the the 12MHz.
SUbsequent product modlflcatlons will be brought to your attention via Service Bulletins;
the text as bulletins are recelved.
please revlse
Thls document Is subJect to change without notice.

TABLE OF CONTENTS
CHAPTER 1. PRODUCT DESCRIPTION. . . . . . . . . . . . . . . 1- 1
CHAPTER 2. PRINCIPLES OF OPERATION 2-1
CHAPTER 3. OPTIONS........................ 3 - 1
CHAPTER 4. TROUBLESHOOTING................. 4 - 1
CHAPTER 5. DISSEMBLY AND ASSEMBLY 5-1
CHAPTER 6. ADJUSTMENT AND MAINTENACE . . . . . . . . . 6 - 1
CHAPTER 7. DIAGRAMS AND REFERENCE MATERIALS .... 7 - 1
CHAPTER 8. DIFFERENCES BETWEEN 10MHz AND 12MHz.. 8-1

CHAPTER
1
PRODOCT DESCRIPTION
TAßLE OF CONTENTS
Section
Title
Page
1.1
1.2
1. 2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.3
1.3.1
1.3.2
FEATU RES ......••.......••........••.........•............ 1-1
SPEC I FICATIONS ..........................•.•.............. 1-3
t1ain System Unit Specifications .••......•...•......•... 1-4
Keyboard Specifications •..........••••.•.....•......... 1-4
FD1155C Floppy Disk Drive Specifications .... .... .••.... 1-4
t1D5501-61 Floppy Disk Drive Specifications ....•.•...... 1-5
D5146H Hard Disk Drive Specifications ..•........ .••. ... 1-6
Hr,1D-720 Hard Disk Drive Specifications .•.•.•.... ..•.... 1-7
HARDWARE CONFIGURATION ............•...................... 1-8
Main System Unit Components ..........•...•.••.......... 1-8
Keyboard Components ............••..................••.. 1-12
LIST OF FIGURES
Fi gure
1-1-1
1-3-1
1-3-2
1-3-3
1-3-4
1-3-5
1-3-6
1-3-7
Title
Major Components
ANTA Boa rd ..........•..•........•.••........•.•..........
ANT- Rtl Boa rd ......••••...........••.......•.•.•..........
SPFG Board ......•.•......•••••.•.......•.••.......•••..••
ATRPS Unit ..............................•.••...........••
WHDC Boa rd •...••.•.........••..•.•.•..•.....•..•.••.•.•.•
Floppy Disk Drive Component ..••.•.......•.•...........••.
Keyboard Component ........•.........•••...........•......
Page
1-1
1-8
1-9
1-10
1-11
1-11
1-12
1-12
Table
Title
LIST OF TAßLES
Page
1-3-1
1-3-2
1-3-3
1-3-4
ANTA Board Component Descripti on .......•••.........••.•.. 1-8
ANT- Rt,1 Boa rd Compon en t Descri pt ion ......•.••............. 1-9
SPFG Board Component Description •.••.•.....•.••.......... 1-10
ATRPS Un i t Outputs .........•..............•........•..••. 1-11

REV .A
PROnUCT DESCRIPTIOR
1 .1 FEATURES
The EQU1TY IlI+ / EPSON pe P\f.. computer system inc1udes two major elements; a
main system unit and a keyboard.
FIGURE 1-1-1. MAJOR. COMPORKRTS
The EQU1TY II1+ / EPSON PC P\f.. hardware configuration has Cl high degree of
compatibility with the IBM AT and the new AT.
System Performance
EQU1TY 111+ / EP SON pe P\f.. has three CPU execution speeds, these are the IBN AT
speed (6 MHz), the new AT speed (8 MHz) and a fast er speed (10 l'fiIz). Speed is
selected by setting a three-position switch easily accessed from the front.
The user can see the selected execution speed by the color of a 1ED.
Wait Cycles
EQUITY IlI+ / EPSON PC P\f.. uses several types of internal devices, such as RAM,
ROM, 16-bit extension memory, 16-bit 1/0 device, 8-bit extensi on memory anel
r,-bit 1/0 device at every CPU speed. In the case of 6 MHz or 8 MHz, the
number of wait cycles is the same as the AT or the new AT.
1-1

PRODUCT DESCRIPTION
REV.A
WX Clock
The clock input to the numerical processor extension (NPX) may be changed
according to the NPX version. The standard clock input is 8 MHz (AT uses 4
MHz and the new AT uses 5.33 MHz). Other clock-inputs, 20, 16, or 12 MHz
(divided by three in the NPX) may be selected by sett ing jumper connectors on
the system board.
Mass Memory
EQU11Y 111+ / EPSON PC AX supports 4 types of built-in mass memory.
Hass Memory Slots
EQUITY 111+ / EPSON PC AX has 5 half-height slots for FDD's and IIDD's. There
are several ways to install the drives in these slots: (1) 4 half-height
drives, (2) 3 half-height drives and a full-height drive, (3) a half-height
drive and 2 full-height drives. A maximum of four drives can be installed.
Power Supply
EQUITY 11I+ / EPSON PC AX has an IBM AT compatible power unit. Hs
specification is world wide, using 115 V /220 V, switch selected, UL/CSA and
TUV standard, and FCC/FTZ standard. The number of power cables is 4.
Multi-function Card
The multi-function carc in the EPSON proprietary slot provides the serial
communication port, parallel printer port and floppy disk controller.
Hard Disk Controller
The hard disk controller contained in the prorietary slot will control two
hard disks.
Packaging
All switches and controls are easily accessible. Switches control the
processor execution speed, and the type of the display, color or monochrome.
1t is easy to connect the keyboard, control the volume, push the reset button,
turn the power on or off, and lock or unlock the main unit. When the unit i8
locked, the system does not accept key input and ignores the reset button.
Exterior
The unit is designed in line with the EQU1TY / EPSON PC series, which visually
distinguishes it from the numerous compatibles.
1-2

REV.A
PRODUCT DESCRIPTION
1.2 SPECIFICATION
The following sections describe detail specifications by major subassembly.
POWER SUPPLY
Input
115 VAC
230 VAC
F requency .
Power Consumption .....••••.
Surge Current •......•.•....
Min. 92 V
Max. 132 V
Min. 196 V
Max. 265 V
49 - 61Hz
115 VAC:
42 A O-P
Hax.
Hax.
4 A
2.5 A
230 VAC approx. 60W
(0.5 sec. more)
INSOLATION STRKRG'l'H 115 VAC: AC 1.25 kV (l min.) (AC-FG, AC-
Secondary)
230 VAC: AC 1.25 kV (1 min.) (AC-FG)
AC 3.75 kV (1 min.) (AC-Secondary)
INSOLATION RESISTANCE
25 MOhm more (500 VDC) (AC-FG,AC-Secondary)
1 MOhm more (250 VDC) (SG-FG) (DIC short
jumper not installed)
ElNIRONMENT CONDITIONS
OPERATING
Temperature 5~ to 35~
Humidity 20% to 80%
(non-condensing)
Maximum wet bulb 29 deg.
NON-OPERATING
- 20° 'C to 60°C
10% to 90%
40 deg.
STORAGE
5% to 95%
45 deg.
Vibration
Shock (non-HDD)
Shock (HDD)
Altitude (HDD)
0.2 G
1 G (less than
10ms)
1 G (less than
25mm 0-60Hz)
o to 3000 m. ASL
1 G (non-HDD)
0.5 G (HDD)
3 G (less than
10ms)
3 G (less than
25mm 0-60Hz)
-300 to 3600 m. ASL
3 G (non-HDD)
0.5 G (FIDD)
30 G (less than
(lOms)
20 G (less than
25mm 0-60Hz)
-300 to 3600 m.
ASL
1-3

PRODUCT DESCRlP TION
REV.A
1.2.1 Main System Unit Specifications
PROCESSOR ••.•.•..•..•.••• 80286-10
CO-PROCESSOR •••••.••.••.. 80287-8
ROM •..•.•••.••••....•.••• 64KB (27256 x 2)
RAM ••..••......•.•..•.•.. 640KB is standard
MASS MEMORy 5 1/4" 1.2MB FDD is standard
MASS MEMORY SLOTS ••••.•.• 6 16-bit 1/0 expansion slots
3 8-bit 1/0 expansion slots
CPU CLüCK ••••.••..•.•...• 6 }lliz, 8 }lliz, 10 }lliz
(Switch selectable)
HAlT CYCLES ...•.•••...... Selectable
DIMENSIONS (W x D x R) ••. 498.5 x 442 x 169 mm
WEICHT ••.•.•..•.••.•..••. 14.5 Kg (Standard model - 1FDD)
1.2.2 Keyboard Specifications
LAYOUT ..••••••••....•..•• New AT compatible
CORD ..•••.••.••.••.•.•..• App rox. 2 meters
DIMENSIONS (W x D x H) .... 490 x 197.5 x 47.7 mm
lmICHT .•••.••.••.••..•... 1.8 Kg
1.2.3 FD1155C Floppy Disk Drive Specification
High Density Mode
Capacity (KBytes)
Unformatted
Formatted
Transfer Rate (K-bits/sec)
Number of Tracks
Recording Density (BPI max.)
(MFM / FM)
1670 / 830
1065 / 532 (256 byte x 26 sector)
1229 / 614 (512 byte x 15 sector)
1311 / 655 (1024 byte x 8 sector)
500 / 250
160 (80 tracks x 2 sides)
9870
1-4

REV.A
PRODUCT DESCRIPTIOH
Normal Density Mode
Capacity (KBytes) (MFM / FM)
Unformatted 1000 / 500
Formatted
655 / 328 (256 byte x 16 sector)
Transfer Rate 300 / 150
Number of Tracks
160 (80 tracks x 2 sides)
Recording Density (HPI max. ) 5922
Seek Speed (1 track)
Seek Settling Time
Head Loading Time
Disk Speed
Track Density
Recording Method
Power Consumption x 2
3 ms
15 ms
35 ms
360 RPM
96 TPI
HFtl/FM
4.8 w
1.2.4 MD5501-61 Floppy Disk Drive Specification
Normal Density Mode
High Density Mode
Capacity (KBytes)
Unformatted
Formatted (IBM
format)
Lf8 TP I
500
327.7
(8 sector)
96 TPI
1000
655.4
(16 sector)
96 TPI
1667
1065
(26 sector)
Transfer Rate (Kbits/sec.) 300
Access Time (track-track)(ms) 10
Recording Density (BPI) 5876
Number of Tracks (p.er side) 40
300
5
5922
80
500
3
9870
80
Seek Settling Time
Disk Speed
Recording Mode
Power Consumption
15 ms
360 RPH
HFN
3.0 \v
1-5

PRODUCT DFßCRIPTION
REV.A
1.2.5 D5146H Hard Disk Drive Specification
Capacity
Unformatted
per Cylinder
per Track
Formatted
per Cylinder
per Track
per Sector
Number of Cylinders
Sectors per Track
Bytes per Sector
Number of Disks
Number of Heads
51.24
83,328
10,416
40.30
65,536
8,192
256
615
32
256
lf
8
MBytes
bytes
bytes
MBytes
bytes
bytes
bytes
Transfer Rate
Access Time
Track-Track
Average Seek
Max. Seek
Disk Speed
Start Time
Stop Time
Recording Methoc1
Recording Density
Track Density
625 KB/sec
8 ms
40 ms
75 ms
3600 RPH
25 sec.
30 sec.
MFH
9000 BPI
700 '!PI
Environment Conditions
Operatin$
Temperature 5~ - 4)C
Humidity 8% - 80%
Vibration
Shock
Altitude
( 29°c)
0.2 G
2.0 G
o - 3000 m
Storage
-4dt - 6&
0.5 G (0-60Hz, less than 25 nun)
20.0 G
-300 - 3600 m
Power Consumption
3.0 w
1-6

REV.B
PRODueT DESCRIPTION
1.2.6 BMD-720 Hard Disk Drive Specification
Capacity
Unformatted
per Track
Formatted
per Track
per Sector
Number of Cylinders
Number of Tracks
Sectors per Track
Bytes per Sector
Number of Disks
Number of Heads
25.5
10,416
20.0
8,192
256
615
2460
32
256
2
4
MBytes
bytes
MBytes
bytes
bytes
Transfer Rate
Access Time
Track-Track
Average Seek
Max. Seek
Disk Speed
Recording Method
Recording Density
Track Density
Interface
5 Mbits/sec
18 ms
69 ms
150 ms
3528 RPH +/-1%
MFM
12900 BPI
910 '!PI
ST-506/412
Environment
Temperature
Humidity
Altitude
Conditions
Operatin&
5°C - 50C
8% - 80%
(26C)
3000 m
Storage
-40°C - 6.fC
8% - 85%
( 30C)
10000 m
Shock-Vibration
No Soft Errors
Vibration
Shock
No Hard Errors
Vibration
Shock
PmJer Consumption
0.4 G, 36-500 Hz
8 G, 10 os
2 G, 14-500 Hz
20 G, 10 ms
8.0 w
3 G, 12-500 Hz
40 G, 10 ms
1-7

PRODUCT DESCRlPTION
HEV.A
1.3 HARDWARE CONFIGURATION
1.3.1 Hain System Unit Components
TABLE 1-3-1. ANTA BOARD COMPONENT DESCRlPTION
NAHE MODEL Qty
CPU 80286-10 1
NPX 80287-8 1
DMAC 8237A-5 2
INTC 8259A 2
TIMER 8254-2 1
REAL TIME 146818 1
KEYBOARD I/F 8042 1
GAATAB E01085CB 1
GAATCB E01086CA 1
GAA'IDB
GAATCK
GAATRF
GAATIO
E01068CA
E01068CA
E01069BB
E01092EA
1
1
1
1
FUNCTION
16 bit CPU
Co-processor (socket only)
DMA control
Interrupt control
Support 3 clock channels
System clock t calender and CUOS RAM
Interface between 80286 and keyboard
Controls CPU address bus (A16-0) t system
addtess bus (5A16-0) and internal address
bus (XA16-0). Generates refresh address.
Control bus (1/0 write pulset 1/0 read
pu lse t memory write pulse, memory read
pulse) and 7 MSB of address bus (A23-17) and
bus high enable signal.
Control CPU bus (D15-0), system data bus
(SD1S-0) and memory data bus (}ID15-0)
Clock generator, bus controller and shut
dOvrn circuit.
Controls D-RAM refresh, DHA transfer t 16-B
data bit conversioD t and wait state
insertion.
Address decoder for 1/0 space and r/o
registers.
FIGURE 1-3-1. ANTA BOARD
1-8

HEV.A
PRODUCT DESCRIPTION
TABLE 1-3-2. ABT-RH BOARD COMPONENT DESCRIPTION
NAME
MODEL
Qty
FUNCTION
ROH
GAATH1
GAATM2
MB81256-10Z
MB81464-12P
uPD4164-12
27256
EOI090BA
E01091EA
18
4
2
2
1
1
256Kbit dynamic RAM (Parity check RAH)
64KB x 4 dynamic RAM
Parity check RAM
BIaS ROM
Address decoder for memory space and parity
checker / generator for system D-RA}I.
Generates D-RAM address (MA8-0) and D-RAM
access signals (RAS, CAS and WE)
FIGURE 1-3-2. ABT-RH BOARD
1-9

PRODUCT DESCRIPTION
HEV.A
TABU 1-3-3. SPFG BOARD COMPONENT DESCRIPTION
MODEL
Q'ty
FUNcnON
FDC
GAATSP
GAATFD
SERIAL
CONTROLLER
uPD765A
E01093BA
E01094BA
16450
1
1
Q
1
Controls FDD's.
Parallel port and address decoder for serial
port.
Controls 360KB and 1.2MB diskette drives.
Includes FDOR (Floppy digital output
register), FCR (Floppy control register) and
write precornpensation circuit.
Controls serial data transfer.
FIGURE 1-3-3. SPFG BOARD
1-10

REV.A
PRODUCT DESCRIPTION
TABLE 1-3-4. ATRPS UNIT OU1PUTS
WMINAL LOAD CURREBT LOAD CURREBT REGULATION OVERLOAD
OU1PUT [VDC] MIN. [A] HAX. [A] TOLERANCE PROTECTION [A]
+5 2.5 20 +- 4% 35
-5 0 0.3 * +-10% 3
+12 0 4.8 (7.0) +- 5% 16
-12 0 0.3 +-10% 3
* 10 sec.
FIGURE 1-3-4.
ATRP S UNIT
FIGURE 1-3-5. WHDC
BOARD
1-11

PRODUCT DESCRIPTION
REV.A
FIGURE 1-3-6.
FLOPPY DISK DRIVE COMPONENTS
Refer to Chapter 3 for the Floppy disk drive components.
1.3.2 Keyboard Components
The new IBM AT compatible keyboard (with 'horne' posHion keys F, J and 5
marked) •
FIGURE 1-3-7. KEYßOARD COMPONENT
1-12

CHAPTER
2
PRINCIPLES OF OPERATION
TABLE OF CONTENTS
Section
2.1
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.2
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
2.2.2.5
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.1.4
2.3.2
2.3.2.1
2.3.3
2.3.3.1
2.3.3.2
2.3.3.3
2.3.3.4
2.3.4
2.3.4.1
2.3.4.2
2.3.5
2.3.6
2.3.6.1
2.3.6.2
2.3.6.3
2.3.6.4
2.3.7
2.3.7.1
2.3.7.2
2.3.8
Title
MAIN SYSTEM UNIT COMPONENTS
ATRPS POWER SUPPLY UNIT .
Primary Oscillation Circuit .
Power Supply Circuit .
Overcurrent Prevention Circuit of the MOS-FET
On-Off Control Circuit .
Inrush Current Prevention Circuit .
Secon da ry Ci rcuit .
-5V and -12V Circuit .
+12V Supply Circuit .
+5V Supply Circuit .
Overheating Prevention Circuit .
Power Good Signal Generation Circuit .
ANTA MAIN CONTROL BOARD OPERATION .
System Clock Generation Circuit .
Select CPU Operation Speed .
LED Indications .
Select NPX (80287) Operation Speed .
Ose; 11 ator .
System Reset Signal Generation Circuit .
System Reset Circuit .
Internal Memory Control Circuit .
RAM Chip Type ••.•...•...•..••...•.•.....••••..••..••..
RAf\1 Chip Addresses ...•....•...••..••......••......••..
Jumper Connector Function .
Operation of ~~emory Control Circuit .•.................
Byte/Word Access & 16-8 Bit Data Conversion .
Data Bus Control Signal on GAATDB .
Circuit Operation of Data Conversion .
1/0 Device Access Circuit .
OMA Contral Circuit .
Page Register Setting Circuit .
8-bit DNA {Internal memory -- 1/0) .
8-bit DMA (Internal memory -- Internal memory) .
16-bit DMA (Internal memory -- 1/0) .
Ready Signal Control Circuit .
Insertion flore Wait Cycle .
Zero Wait Cycl e Request .
Command Delay Signal Control Circuit .
Page
2-1
2-2
2-2
2-2
2-4
2-5
2-6
2-6
2-7
2-10
2-13
2-13
2-19
2-21
2-21
2-21
2-22
2-23
2-25
2-26
2-28
2-28
2-29
2-29
2-29
2-32
2-32
2-33
2-41
2-42
2-42
2-43
2-43
2-43
2-48
2-49
2-49
2-51

2.3.9
2.3.10
2.3.10.1
2.3.11
2.3.12
2.3.13
2.3.14
2.3.14.1
2.3.14.2
2.3.14.3
2.3.14.4
2.3.14.5
2.3.14.6
2.3. 15
2.4
2.4.1
2.4.1.1
2.4.1.2
2.4.1.3
2.4.2
2.4.2.1
2.4.2.2
2.4.3
2.4.3.1
2.4.3.2
2.4.3.3
2.4.3.4
2.4.3.5
2.5
2.5.1
2.5.2
2.5.2.1
2.5.2.2
2.5.3
2.5.3.1
2.5.3.2
2.5.3.3
2.5.3.4
2.5.3.5
2.5.4
2.5.5
2.5.6
2.5.6.1
2.5.6.2
2.5.6.3
2.5.6.4
2.5.6.5
2.5.6.6
2.5.6.7
2.5.7
2.5.7.1
2.5.7.2
Interrupt Control Circuit .
RO~~ Access Circuit .
Available ROM Types .
D- RÄf'1 Refre sh Ci rcu i t .
RAM Parity Check Circuit .
Speaker Control Circuit .
Keyboard Interface Circuit &Other Circuit .
Keyboard Interface .
RAr-.1
Si ze Rea d; n9 .•••••••••••••..•.•...•.••......•...••
~1onitor Setting Reading .
Disabling Keyboard Scan Codes .
Software Reset Signal Generation .
Address A20 Signal Control .
1/0 Slot Access Signal .•...............................
MULTI-FUNCTION ADAPTER (SPFG BOARD) OPERATION .
Serial Interface .
16540 Chip Select Circuit .
Interface Signal .
Data Buffer Direction Control Signal .
Parallel Data Control Circuit .
1/0 Address Selection .
Parallel Data Control Circuit Functions .
FDD Contral Circuit .
FDD Control Register Access Circuit .
Interrupt Signal and DMA Request Signal from FDC .
FDD Con t ro1 Si gn als .
Read/Wri te Ci rcu i t .
Other Functions .
KEYBOARD ••••••••••••••.••••••.•••••••••••••••••••••••••••
Block Diagram .
Interface Signal .
AT t,1ode •......••••....••.........•.••.••.••...•.•••••.
XT Mode .............................................•.
Description of Interface Signals (AT Mode) .
Clock .
Data .
Keyboa rd Data Output (AT t1ode) ........•...............
Keyboa rd Data Input (AT t1ode) .
Data Transmission Method and Data Format .
Interface Circuit Specification .
Connector Pin Explanation .
Function Specifications ...............•................
Strake Characteristics .••...••••.•••...•..•••..••••.•.
Typematic Function .
Keyboa rd Buffer .
Power On Reset (AT ~1ode) .
Initializing (XT Mode) .....•..........................
Data Wait Function (XT Mode) .
Mode Indicator (3 LED's) Display (XT ~1ode) .
Key Scan Code .
Key Code Output (AT Mode) .
Key Code Output (XT tlode) .
2-53
2-54
2-54
2-56
2-58
2-60
2-61
2-61
2-61
2-61
2-61
2-61
2-62
2-64
2-65
2-65
2-65
2-65
2-66
2-66
2-66
2-66
2-70
2-70
2-70
2-70
2-71
2-74
2-77
2-77
2-78
2-78
2-79
2-79
2-79
2-79
2-79
2-80
2-80
2-82
2-82
2-83
2-83
2-83
2-84
2-84
2-85
2-85
2-86
2-87
2-87
2-91

2.5.8
2.5.8.1
2.5.8.2
Commands (AT t10de) 2-91
Commands From the Host Side 2-91
Commands To the Host Si de 2-96
Fi gu re
2-1-1
2-2-1
2-2-2
2-2-3
2-2-4
2-2-5
2-2-6
2-2-7
2-2-8
2-2-9
2-2-10
2-2-11
2-2-12
2-2-13
2-2-14
2-2-15
2-2-16
2-2-17
2-2-18
2-2-19
2-2-20
2-2-21
2-2-22
2-2-23
2-3-1
2-3-2
2-3-3
2-3-4
2-3-5
2-3-6
2-3-7
2-3-8
2-3-9
2-3-10
2-3-11
2-3-12
2-3-13
Title
LIST OF FIGI RES
Logic Block Diagram .
Basic Operation Circuit ...............•..................
Switching Oscillation Circuit I .
Switching Oacillation Circuit 11 ......•..................
Overcurrent Prevention Circuit I .
Overcurrent Prevention Circuit 11 .
Inrush Current Prevention Circuit .
Functions of Resistor R5 and R6 .
-5V and -12V Supply Circuit ...........•..................
+12V Supply Circuit .
+12V Stabilization Circuit .
Voltage Stabilization Circuit 11 .
Characterize of Z3 .
Fan Revolution Speed Control Circuit .
Overcurrent Prevention Circuit .
+5V Supply Circuit .
+5 V VoHage Stabil i ty Ci rcuit .
Output Current of Photocoupler .
Output Signal Waveform .
Overvoltage Prevention Circuit .........•.................
Overheating Prevention Circuit .
Power Good Signal Generation Circuit I .
Power Good Signal Generation Circuit II .
Timing Chart of Power Good Signal ...•....................
Internal Circuit Configuration .
System Clock Supply Circuit ..
Clock Speed Change Circuit .
System Reset Circuit .
Internal Memory Control Circuit .
Byte/Word Access &16-8 Bit Data Conversion .
Data Transmission to 16 Bit Device
(Byte Transmission of Even Address) .
Data Transmission to 16 Bit Device
(Byte Transmission of Odd Address) .
Data Transmission to 16 Bit Device
(Word Transmission of Even Address) .
Data Transmission to 8 Bit Device
(Byte Transmission of Even Address) .
Data Transmission to 8 Bit Device -- Read Mode
(Byte Transmission of Odd Address) .
Data Transmission to 8 Bit Device -- Write Mode
(Byte Transmission of Odd Address) .
Data Transmission to 8 Bit Device -- Read Mode
(Word Transmission of Even Address) .
Page
2-1
2-2
2-3
2-3
2-4
2-4
2-5
2-6
2-6
2-7
2-7
2-8
2-8
2-9
2-9
2-10
2-10
2-11
2-11
2-12
2-13
2-14
2-15
2-16
2-19
2-24
2-24
2-27
2-31
2-35
2-36
2-36
2-37
2-37
2-38
2-38
2-39

2-3-14
2-3-15
2-3-16
2-3-17
2-3-18
2-3-19
2-3-20
2-3-21
2-3-22
2-3-23
2-3-24
2-3-25
2-3-26
2-3-27
2-3-28
2-3-29
2-3-30
2-4-1
2-4-2
2-4-3
2-4-4
2-4-5
2-4-6
2-4-7
2-4-8
2-4-9
2-4-10
2-4-11
2-4-12
2-4-13
2-4-14
2-4-15
2-4-16
2-4-17
2-4-18
2-5-1
2-5-2
2-5-3
2-5-4
2-5-5
2-5-6
2-5-7
2-5-8
2-5-9
2-5-10
Data Transmission to 8 Bit Device -- Write Mode
(Word Transmission of Even Address) .
1/0 Device Access Circuit .
m~A Control Circuit I (Setting of Page Register) .
Dt~A Control Circuit II (Internal memory -- 1/0, 8bit) .
DMA Control Circuit 111 (Internal memory -- 1/0, 8bit) .
DMA Control Circuit IV (Internal memory -- 1/0, 16bit) .
Ready Signal Control Circuit .
Timing bet\'/een Address Signal and Read/Write Signal .
Command Delay Signal Control Circuit .
Interrupt Control Circuit .
ROr1 Access Circuit .
D-RAM Refresh Circuit .
RAt,' Parity Check Circuit (Data Write ~lode) .
RAt1 Parity Check Clrcuit (Data Read Mode) .
Speaker Control Circuit .
Keyboard Interface and Other Function Circuit .
1/0 Slot Access Signal .
16450 Chip Select Circuit .
1/0 Address Sel ecti on .
Data Output (Printer Data Register Circuit) .
Outpu t Data Rea d Ci rcuit .
Printer Control Signal Output Circuit .
Printer Control Signal Read Circuit .
Printer Status Signal Read Circuit .
Interrupt Signal Control Circuit .
FDD Control Circuit I (FDD -- CPU) .
Interrupt Signal and D~'A Request Signal from FDC .
FDD Data Write Circuit .
FDD Data Read Circuit .
VFO Window Circuit .
FDD Terminator Function .
FDD Cable Setting .
Drive Select and Motor On Signal Supply Circuit .
FDD Special Signal Cable .
Hard Disk Drive Signal Cable •••..•.••••.•..•••..•••••..•.
Keyboard Unit Block Diagram .
Keyboard Data Output (AT Mode) .
Keyboard Data Input (AT t1ode) .
Keyboard Data Output (XT Mode) .
Interface Circuit .
Keyboard Connector Pin Locations .
Stroke Characteristics .
Typernatic Function .
Basic Operation of Mode Indicator Display .
Special Functions of Mode Indicator Display .
2-40
2-41
2-44
2-45
2-46
2-47
2-50
2-51
2-52
2-53
2-55
2-57
2-58
2-59
2-60
2-63
2-64
2-65
2-66
2-67
2-67
2-67
2-68
2-68
2-68
2-70
2-70
2-71
2-72
2-73
2-74
2-74
2-75
2-75
2-76
2-77
2-80
2-81
2-81
2-82
2-82
2-83
2-83
2-86
2-86

LIST OF TABlES
Table
Title
Page
2-2-1
2-2-2
2-2-3
2-3-1
2-3-2
2-3-3
2-3-4
2-3-5
2-3-6
2-3-7
2-3-8
2-3-9
2-3-10
2-3-11
2-3-12
2-3-13
2-3-14
2-3-15
2-4-1
2-4-2
2-5-1
2-5-2
2-5-3
2-5-4
2-5-5
2-5-6
2-5-7
2-5-8
2-5-9
2-5-10
2-5-11
2-5-12
2-5-13
2-5-14
2-5-15
2-5-16
2-5-17
2-5-18
2-5-19
2-5-20
2-5-21
2-5-22
Function of Prevention Circuit ............•......•...•...
Specification of DC Max Current ......•..•.....••....•....
Power Down Signal Specification ....••...•.•............••
Memory r·1ap •••••••••••••••••••••••••••••••••••••••••••••••
LED Indications ..•.......•...•...............•....•.....•
NPX Operation Speed .........•...•....•.•.•....•........••
Oscillator Clock Signal Flow .
Reset Signal Generation Methods .....•..••......•......•..
Function of RAfl1 Chips ...•....•..........................•
Jumper Connector Function ..................•........••...
CPU Data Access Modes .•..................................
Functions of Control Signal on GAATDB ...•...........•....
Explanation of LS612 .•...•..........•....•.........•...••
Wait Cycles ..........•..................................•
Wai t Cycl eSel ecti on ...........................•........•
Condition of The CDLY Signal Output ......•...............
Ava i 1ab 1e ROt,1 Types .•...•............•.......•.....•...•.
A20 Signal Control by GAATRF ..•.........•....•....•......
Jumper J9 Setting ..•......•..•.............•....•....•...
Difference Between 1.2 MB FDD of SD-581L
and FD1155C/t1D5501 .
Interface Control ~1ode ..•...•..••........................
Data COJTlllunication r,1ode (AT t1ode) ..
Data Comnunication t10de (XT Mode) ..
Data Transmission Method and Data Format •......••..••....
Keyboard Connector Pin Function .....•.•...••....•.•.••...
Transmission Intervals •..•......•................•.....•.
Ove rrun Code s .........••..•..................••....•.....
Key Code Make Up ..•...•..•...•...•..•..••..........•....•
Condition for Setting and Releasing Numeric Lock .•....•..
Key Stroke Condition ..............•......................
Extension Left and Right Shift Codes •...•.....••....•...•
Transmission Sequence of Left and Right Codes Key ....•...
Transmitted Code of F16 (break) Key ..
Transmitted Code of F14 (Sys Rq) Key .
Keyboard Comnands (AT mode) ..
Typemati c Rate/Del ay .•.......••..••.....•....•..•.....•..
Opti on Regi ster for Keyboard .........•••..•.....••..•...•
Key Code t10de Status .......•...•............•............
Key Code t10de on Option Data .
All Key Typemati c Control ..
Commands to The Host Si de .•...•...•..•••.......•••..•..••
Key Scan Code List .........••...•.................•..•...
2-16
2-17
2-18
2-20
2-22
2-22
2-23
2-25
2-28
2-29
2-32
2-32
2-42
2-48
2-49
2-51
2-54
2-62
2-65
2-69
2-78
2-78
2-79
2-80
2-82
2-84
2-84
2-87
2-88
2-88
2-89
2-89
2-90
2-90
2-91
2-92
2-94
2-95
2-95
2-96
2-96
2-97

REV.A
PRINCIPLES OF OPERATION
2.1 HAIN SYSTEM UNIT COMPONENTS
The following diagram sho~JS a functional block diagram of the EQUITY III+ /
EPSON pe ÄX.
1\11 interface c.ircuit except key board interface should be instaIIed on a
option slot.
DMAC
8237x2
ANTA board
CPU
80286
I
ANT-RM board ANT RM board
,--_M6_E~_g_~_~_...I connecJ-t_o_r_....__c_on-t".1f1 - :~
TI~ER
8254-2
RTC
146818
KEYBOARD
controller
8042(8742)
keyboard
INTC
8259x2
+5
+12
-5
-12
ATRPS unH
Power
supply
unit
1
SPFG board
slots
AC
outlet
Monitor
adapter
CRT
Floppy Parallel Serial
disk Printer communication
interface interface interface
~ ,
FDD
PRINTER
RS-232C
HDD
WHDC
Hard disk
controller
board
FIGURE 2-1-1.
LOGIC BLOCK DIAGRAM
2-1

PRINCIPLES OF OPERATION
REV.B
2.2 ATRPS POWER SUPPLY UNIT
ATRPS Unit is available in both 115-volt supply and 230-volt supply.
Switch S1 selects either 115-volt supply or 230-v01t supply, and
simultaneously switches a fuse.
Basic Operation
ATRPS Unit uses the Forward Converter Switching Regulation way.
+
1__Ff'
MOS
FET
FIGURE 2-2-1.
BASIC OPERATION CIRCUIT
2.2.1 Primary Oscillation Circuit
The HA16654 controls the MOS-FET. By supplying power to the HA16654, current
flows in the liOS-FET.
2.2.1.1 Power supply circuit
Power supply circuit for the HA16654 is explained by the following 2 steps:
1. From power on till the transformer for switching oscillates correctly.
2. After the transformer for switching has oscillated correctly.
1. From POWER ON till the transformer for switching oscillates correctly.
The power supply circuit is shown in Figure 2-2-2.
Zenor Diode D10 and Dll works so as not to supply the HA16654 with a voltage
until the input voltage V reaches the fixed-level voltage.
2-2

REV .A
PRINCIPLES OF OPERATION
1 D10 ~
D11
~
V
1
+
Q2 7 4
VI N
HA16654
6 GND
FIGURE 2-2-2.
SWITCHING OSCILLATION CIRCUIT I
2. After the transformer for switching has oscillated correctly.
No current is present in RIl t DIO t DII t and DI9 because the voltage supplied
from DI2 and RIS is higher than the voltage supplied from Rl1 t DIO t Dl1 and
D19. This causes the increase of efficiency of the ATRPS Unit.
Tl .....
I R11
I
'D10
I
I D11
'D19
.J
t
V
+
7 4
VIN
HA16654
9 6 GND
FIGURE 2-2-3. SWITCHING OSCILLATION CIRCUIT 11
2-3

PRINCIPLES OF OPERATION
REV.A
2.2.1.2 Overcurrent Prevention Circuit of the MOS-FET On-Off Contro! Circuit
The circuit which consists of the transistor Q4 and Q5 works as foliows:
* If the input voltage is higher than the standard voltage t
the Q5 collector
current flows instead of the Q4 collector current.
R11 05 R12 et
FET
Vin
Q1
Q2
HA16654
OB
7
5
OUT
VRef

REV.A
PRINCIPLES OF OPERATION
1) If the current flowing in the MOS-FET increases, the induced voltage (e2)
increases.
2) If the voltage which is distributed at R15 and R16 is higher than the
standard voltage at R10 and R11, the Q5 collector current flows.
3) If positive voltage is applied between base and emitter of transistor Q3,
then the collector current flows.
4) If the voltage at the DB terminal in the HA16654 increases, and the pulse
width is reduced, then the current decreases.
2.2.1.3 Inrush Current Prevention Circuit
The inrush prevention circuit protects diode bridge DBI and subsequent
components from being damaged by excessive current flow in C12 and C13 at
power-up. R3 limits the current to RC1 when power is applied; when the
switching oscillator operates normally, voltage from Tl activates TRIAC CRl,
permitting current flow to RC1.
eR1
T 2 T 1
~O
R3
FIGURE 2-2-6.
INRUSH CURRENT PREVENTION CIRCUIT
2-5

PRINCIPLES OF OPERATION
REV.B
(Reference)
Resistor R5 and R6 have two following functions
1) To be equal the voltage of the resistor R5 in e12 to that of the resistor
R6 in C13.
2) To use up the electric charge as soon as the switch is turned off.
C12
RS
30K
C13
R6
30K
FIGURE 2-2-7. FUNCTIONS OF RESISTOR RS AND R6
2.2.2 Secondary circuit
2.2.2.1 -SV and -12V Circuit
When an electromotive force which is in the direction of 1 is produced in the
transformer Tl, tbe series voltage regulator 21 and 22 are supplied with the
power reference through RC2 and L4.
When an electromotive force which is in the direction of 2 was produced at the
transformer Tl, the power reference is supplied from L4.
* R17 is for capacitor discharge.
* D14 and D13 is for series voltage regulator protection.
014
)JPC7812H
or HA17812P
,..........-.,
AN 79MOS
C37
J;
630V
- S VO.3A
-sv
(2) 8
C23
2SV
100
+
~, ~~ ~l~
013 00 47
06'="C--I~"':'::'-'-4'--""'::"'=-+-"
GNO
R17 0.01
lW •
200
- 12 V0.3 A -1 2V
FIGURE 2-2-8. -SV AND -12V SUPPLY CIRCUIT
2-6

REV . B
PRINCIPLES OF OPERATION
2.2.2.2 +12V Supply Circuit
a) Basic Circuit
+12V supply circuit is shown in Figure 2-2-9. The function of the +12V supply
circuit is same as the -sv supply circuit and -12V supply circuit.
T 1
L 6
.............---.4.---0 + 12 V
28
--.....----.....-----...--4----0 G ND
FIGURE 2-2-9.
+12V SUPPLY CIRCUIT
b) Voltage stabilization circuit
b)-l. Basic Function
When a control signal Is high level, an electric power through the transformer
L5 is decreased. This function control the 12 volts voltage.
T 1
Vo ltage
stabilization
ci rcuit
Control signal
FIGURE 2-2-10.
+12V STABILIZATION CIRCUIT
b)-2. Voltage Stabilization Circuit
The 23 i8 designed so that when the voltage of reference terminal reaches
fixed level, a current flows from cathode to anode.
This function is described in figure 2-2-11.
2-7

PRINCIPLES OF OPERATION
KEV.A
L5
V I N O>-----.W
VOUT
10
Q3
2.2 K
10
100
51K
cathode
Z3
anode
RV2
470n
GND
GN 0
FIGURE 2-2-11. VOLTAGE STABILIZATION CIRCUIT 11
If the Vout voltage rises, the Vref voltage rises and then the cathode
current increases. After that the Q3 collector current increases, and the
Vout voltage decreases ---- Function 1
If the Vout voltage decrease, the Vref voltage decreases and the cathode
current decreases. After that the Q3 collector current decreases and the Vout
voltage rises -_._.- Function 2
CATHOOE
CURRENT
[A]
REFERENCE
VOLTAGE
[V]
FIGURE 2-2-12.
CHARACTERIZE OF Z3
2-8

REV.A
PRINCIPLES OF OPERATION
A voltage stabilization circuit repeats the above functions and stabilizes the
12V line.
If a stable Vout voltage is lo\/er than +12 volts, let down a RV2 resistor
value. If let down a resistor value, the Vref voltage decreases and the
cathode current decreases. After that, the Q3 collector current decreases and
the Vout voltage rises.
In the same way, if a stable Vout voltage is higher than +12 volts, let up the
resistor value of volume RV2.
c) Fan Revolution Speed Control Circuit
12V -----...----,
When temperature increases,
~ value of resistance decreases.
TH1
FAN
GN D-----....-------

PRINCIPLES OF OPERATION
REV.B
2.2.2.3 +sV Supply Circuit
a) Basic Circuit
The +sV circuit is shown in Figure 2-2-15.
The function of the +5 volts circuit is same as -SV circuit and -12V circuit.
L7
+ +
'--........---........-------------.----0 G ND
Tl
FIGURE 2-2-15.
+5V SUPPLY CIRCUIT
b) Voltage Stability Circuit
\------"4....----------0 + 5
\----+-----.-----(J GND
5
OUT
HAI6654
EI
R7
e
If
RVl
2.2 K
GND
Re
Z4
R32
910
FIGURE 2-2-16.
+5V VOLTAGE STABILITY CIRCUIT
2-10

HEV.A
PRINCIPLES OF OPERATION
Characteristics of Photo Coupler PC2
In the photo coupler, the output current (IC) increases in proportion to the
current flowing in the LED (IF).
FIGURE 2-2-17.
Characteristics of HA16654
If
OUTPUT CURRENT OF PHOTOCOUPLER
The 8th-pin error input terminal and the 5th-pin output terminal of the
HA16654 have the following relation.
* If the voltage of ERROR INPUT terminal rise, the pulse width of the output
terminal is reduced.
ERROR INPUT
DEAD BAN 0 --+-+-~~--t-~-""'~""'--
I
eT11
1 1
1 1
11
OUTPUT _
....... "-'---~
FIGURE 2-2-18.
OUTPUT SIGNAL WAVEFORM
Characteristics of 24
When the reference vo1tage of the IC24 reaches a fixed voltage, current flows
from cathode to anode shown in Figure 2-2-17.
2-11

PRINCIPLES OF OPERATION
HEV.A
Description of circuit
The voltage stabilization circuit of the +5V supply circuit utilizes above
three elements.
The vicinity of fixed voltage is applied to the
voltage of +5V line increases, current flows in
8th-pin terminal voltage of the HA16654 increases.
reference terminal. As the
Z4 increases, and then the
Then a pulse width of the
the secondary oscillation
output terminal is reduced and a output voltage of
circuit decreases.
If the voltage of +5V line decrease, the voltage of the error input terminal
of the HA16654 decreases and a pulse width of the output terminal widen.
Therefore the output voltage of the secondary oscillation circuit increases.
If the voltage of the stable +5 volts line is lower than +5 volts, enlarge the
resistor value of volume RVl. Then the terminal voltage of R32 decreases and
the current flowing in Z4 decreases. The voltage of the ERROR INPUT terminal
of the HA16654 decreases and it causes the pulse width of the output terminal
to widen and the +5V line voltage to increase.
When a voltage of the stable +5 volts line is higher than +5 volts, let dO\m
the resistor value of the volumn RVI because of the same reason as above.
* The base resistor of the photo coupler is for gaining the switching speed.
c) Overcurrent Prevention Circuit
Function of the overcurrent prevention circuit is same as +12V supply circuit.
d) Overvoltage Prevention Circuit
+ 5 Vline
R28
08
FIGURE 2-2-19.
OVERVOLTAGE PREVENTION CIRCUIT
2-12

RKV.A
PRINCIPLES OF OPERATION
2.2.2.4 Overheating Prevention Circuit
When the temperature rises to a fixed level, switch TH2 is turned on. With
switch TH2 turned on switch TH2, a comparator generates a high level signal
and it results in no pulse output of the output terminal of the HA166654.
+5V
~""---GND
7.5K
GND
82
I TH2
15Kfi
-12V
FIGURE 2-2-20.
OVERHEATING PREVENTION CIRCUIT
2.2.2.5 Power Good Signal Generation Circuit
The pOvler good signal generation circuit monitors the +5V line, +12V line,­
12V line and -5V line of the secondary oscillation circuit.
If there is an abnormality (low voltage) in these lines, the power good signal
changes to low level signal.
Also, it monitors a primary voltage proportion circuit. If there is an
abnormality (low voltage) in the input AC adapter, power good signal changes
to low level signal.
The primary voltage proportion circuit is equipped with the CR circuit. The
CR circuit controls timing of the power good signal.
2-13

PRINCIPLES OF OPERATION
REV.A
+,~
T1
R38
lOOK
+
017
,-------,
I R34 I
R36
27
R35
26
I , I
L
...J
FIGURE 2-2-21. POWER GOOD SIGNAL GENERATION CIRCUIT I
(Primary voltage proportion circuit)
2-14

REV.B
PRINCIPLES OF OPERATION
+12
+5
line
-12V
line
+12
line
R38
R39
R40
A~-"'"
09
010
R 41
R 42
FIGURE 2-2-22. POWER GOOD SIGNAL GENERATION CIRCUIT 11
2-15

PRINCIPLES OF OPERATION
REV.A
AC
OC
P.G.
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Power ON
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Power
OFF
20 msec more
(When ACl00V)
'\1msec
more
FIGURE 2-2-23. TIMING CHART OF POWER GOOD SIGNAL
TABLE 2-2-1.
FUNCTION OF PREVENTION CIRCUIT
Detecting voltage or
Detecting current
Condition after
detecting
Overvoltage
detector
+ SV
+12V
-12V
- SV
5.5 volts - 7.0 volts Cut all output off.
To recuperate
condition, turn off
AC, then on after
30 seconds.
Overcurrent
prevention
circuit
+ SV
+12V
-12V
- SV
3sA
16A
3A
3A
Cut all output off.
To recuperate
condition, turn off
AC, then on after 30
seconds.
2-16

REV.A
PRINCIPLES OF OPERATION
TABLE 2-2-2 SPECIFICATION OF DC MAX CURRENT
+5V +12V -12V -5V
Output current 20A 4.8A * O.3A O.3A
Max (Min) (2.5A) (OA) (OA) (OA)
* 7A within
10 seconds
after power
on.
Current
consurnption
ANTA BOARD 1.23A OA
(effective
value)
ANT-RM BOAHD O.50A OA
(effective
value)
SPFG BOARD O.54A OA
(effective
value)
WHDC BOARD O.53A OA
(effective
value)
HRS-MO BOARD O.27A OA
(effective
value)
MRS-CR BOARD
O.50A
(effective
value)
FD1l55C O.46A O.21A (TYP)
O.39A (po~ler
on)
MD5501 o.1lA (TYP) o.24A (TYP)
1.66A (peak)
HMD-720 O.2A (TYP) 2.0A (power on)
O.58A (TYP)
D5146 (40M HDD) l.OA (MAX) 3.0A (power on)
2.0A (seek)
1.2A ( read/write)
2-17

PRINCIPLES OF OPERATION REV .A
TAßLE 2-2-3. POWER DOWN SIGNAL SPECIFICATION
Power down signal
11\
11SV MODE
7SV
,I, /1\
75 80
...
, AC
Power down signal
I
230V MODE
lSOV
" 1\
150 160
...
,
AC
2-18

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2 .3 ARTA MAHl CONTROL BOARD OP ERATIONS
This section describes the principles of the ANTA board operation by using the diagrams
which shows an internal circuit of the EQUITY 111+/ EPSON PC AX computer system. There
are several blocks in the diagram for each circuit operations.
ARTA BOARD ART-RM BOARD
< > < >
GAATCK
n
GAATRF
! , I I
GAATMI
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I MB81256
0'
equivalent
~PD4164
0'
eCluivaient
CPU
~
MB81256
0'
equivalent
jJPD4164
0'
eQuivalenl
GAATJO
GAATM2
GAATDB
FIGURE 2-3-1. 1NTERlIAL C1RCU1T CONFIGURATION
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Table 2-3-1 shows the memory map for the EQUITY lll+/EPSON pe AX computer system.
TABLE 2-3-1. MEMORY KAP
ADDRESS
NAME FUNCnOB
000000 to 09FFFF
OAOOOO to OBFFFF
OCOOOO to ODFFFF
OEOOOO to OEFFFF
OFOOOO to üFFFFF
100000 to FDFFFF
FEOOOO to FEFFFF
FFOOOO to FFFFFF
640 KB system memory
128 KB video RAM
128 KB r/o EXPANSION ROM
64 KB reserved on system
64 KB ROM on system board
Maximum memory 15 MB
64 KB reserved on system
64 KB ROM on system board
System memory
Reserved for graphics display buffer.
Reserved for ROM on 1/0 adapters.
Duplicated code assignment at address
FEOOOO.
Duplicated code assignment at address
FFOOOO.
1/0 channel memory - memory expansion
option.
Duplicated code assignment at address
OEOOOO.
Duplicated code assignment at address
OFOOOO.
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2.3.1 System Clock Generation Circuit
All clock signals are supplied from the gate array (GAATCK) except the RTC (146818)
clock signal. The GAATCK generates the following clocks.
1) CPU clock (12 MHz, 16MHz, 20MHz)
2) NPX c10ck (mfilz)
3) DMA clock (3MHz, 4~frlz, 5~rnz)
4) Timer counter c10ck (1.19MHz)
5) Keyboard controller clock (6~rnz)
6) OSC clock (for option slot: 14.31818Mllz)
7) SCLK signal (System clock for option slot: 6}filz, 8MHz, 10}lHz)
< REKARK >
Please be careful with difference between 'clock speed' and 'operation speed'.
The CPU and the NPX divide an input clock signal by one's internal circuit. (NPX
does not divide the input clock signal in 8}filz mode. Please refer to Section 2­
2-3.) This means there are some cases that the input clock speed is not
identical with the operation speed. This manual defines these words as below.
Clock speed -------- Input or output clock signal speed
Operation speed ---- Internal clock speed
2.3.1.1 Select CPU Operation Speed
The EQUITY III+/EPSON PC AX has three kinds of CPU operation speeds. One is 6MHz, the
same as IBM AT, 8MHz is the same as IBM NEW AT, and 1Ot1Hz is faster operation speed
than IBM AT or NEW AT.
We can select these CPU operation speeds by slide switch (SW2) ..Also, the GAATCK
includes clock speed select circuit.
2.3.1.2 LED Indications
There are two LEDs on the clock speed change circuit. These LEDs indicate the CPU
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operation speed.
TADLE 2-3-2. LED IRDICATIONS
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< REKARK >
LED INDICATIONS CPD OPERATION SPEED
RED
ORANGE
GREEN
6HHz
SHHz
10MHz
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Jumper connector J1 is inhibitted to change setting. (Always connect betvJeen A to C )
2.3.1.3 Select NPX (80287) Operation Speed
The EQUITY III+i EPSON PC AX has two kinds of NPX operation speed modes.
TADLE 2-3-3. NPX OPERATION SPEED
NPX OPERATION SPEED MODES OPERATION SPEED
(CPU OPERATION SPEED)
1) CPU CLOCK MODE (~nlz)
( SHHz)
( 1000mz)
2) 8MHz MODE (6NHz, SMHz, 1OHHz)
4HHz
5.3HHz
6. lNHz
8MHz
A selection is performed by setting of jumper connector Jl and J2 on the ANTA board
(Main circuit board). Jumper connector setting of Jl and J2 are listed in CHAPTER 7.
< REKARK >
NPX ~.>
divides the CPU clock into three in the CPU clock mode.
In CPU CLOCK MODE, the NPX divides the CPU clock into three. But 8}1Hz mode, the
NPX does not divide SMHz clock.

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2.3.1.4 Oscillator
There are three oscillators on the ANTA board. The GAATCK inputs these signals
and produces the following clock signals.
TABLE 2-3-4. OSCILLA'l'OR CLOCK SIGNAL FLOW
OSC CLOCK SPEED GAATCK DIVIDE
'l'BE CLOCK IN'l'O;
GAATCK OU1PUTS; CONNECT 'l'O;
(MAJOR CHIP)
48lvlliz
20MHz
14 .31818MHz
1/3
1/4
1/6
1/8
1/1
1/1
1/12
16MHz
12MHz
8MHz
6MHz
20HHz
14.31818MHz
1.19l-1Hz
CPU
CPU
NPX
KEYBOARD CONTROLLER
CPU
OPTION SLOT
TIMER COUNTER
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L~~~~L~:I-----i-t---'1 CSPD'
1S01\ ~ ~ 1SOn
J 1
CN3
GAATCK
Red ftGreen
er
FIGURE 2-3-2. SYSTEM CWCK SllPPLY CIRCUIT FIGURE 2-3-3. CLOCK SPEED CBAI«;E CIRCUIT
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2.3.2 System Reset Signal Generator Circuit
There are three kinds of reset signal on the EQUITY III+/EPSON PC AX computer system
below. The gate array GAATCK generates these signals.
1) CPU RESET SIGNAL
2) INTERNAL CIRCUIT RESET SIGNAL
3) OPTION SLOT RESET SIGNAL
To generate the above reset signals> there are the following methods.
TABLE 2-3-5. RESET SIGNAL GENERATION METHODS
RESET SIGNAL
METHODS
CPU RESET SIGNAL
INTERNAL CIRCUIT RESET SIGNAL
OPTION SLOT REST SIGNAL
1) PWGD signal goes low.
2) Reset switch is pushed.
3) Re signal goes active.(Software reset)
4) Shut down cycle is executed.
Reset switch is pushed.
Reset switch is pushed.
< REMARK >
The software reset command (RC goes active) resets only the CPU.
When gate array GAATCK receives the RC signal, it generates the RSCPU signal.
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2.3.2.1
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System Reset Circuit
1) PWGD signal
The power supply unit (ATRPS unit) generates a signal.
unit has some problems, the PWGD signal becomes low.
keeps high level.
When the gate array GAATCK receives the PWGD signal,
signal, a RSDN signal and a RSCPU signal.
When the power supply
Normally, this signal
it generates a RSN
2) Reset switch (SW3)
When the reset switch SW3 is pushed, the GAATCK generates a RSN signal, a
RSDN signal and a RSCPU signal. This computer system can disable the reset
switch signal by locking the key cylinder on the front panel. When the key
cylinder is locked, the key cylinder switch becomes on. When the key
cylinder switch is on, the GAATCK does not output any reset signals.
3) RC signal
A RC signal is sent from P20 pin of the keyboard controller (8042) which can
be controlled by software.
A RSCPU signal becomes active by the active RC signal.
(Refer to the remark in section 2-4.)
4) Shut down cycle
A Shut down cycle is a kind of CPU execution cycle. When the CPU executes
this cycle, it means that the CPU detects a fatal software error with which
the CPU can not continue its current operation. CPU indicates this cycle with
SO, S1, M/lO, COD/lNTA signals.
The shut down circuit of the GAATCK is searching for the shut down cycle
whenever power is on and if it detects the shut down cycle, it generates an
active RSCPU signal.
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~Hls~
CN3~--·"'-"
(j flJ5:rol---rol:l;;!.....-Ol ---..../K.y Cyliod. r ,....... _
~:et----d ~Sw1tch I I
GAATAB ,------: GAATRF GAATlo41
DMAl
8237A-5
~ RESET
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~= ~ SWON
llheo the res.t SW 1$
PIlshed. thls .19011
_.low.
10 cu. of k.ylockl09.
thl. s19011 ls 11.lys
h19h _.r the
res.t SII ls PUShed.
J;.R 5 T 0 I--­
~II , r
GAATCB
RSTNi
=
L+j RESET
10 the fo11owl"9 eondltlon.
thls slgnel _. leth••
(1) PIIGO sl9O.l _. 10w
(2) ReHt SW ls pushed
(3) RC .19011 _s leth.
(4) Shut down eycl.
GAATIO GAATM2
i i
BltO. 1. 2 Ind 31
Ire el..red
~RST_
!ill!:! 8042 GAATDB
Illml-
Ṉ
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RESETI-
PRSI-
P201---
DMA2
8237A-5
L..,..jRESET
I
FIGDRE 2-3-4. SYSTEM RESET CIRCUIT
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2.3.3 Internal Memory Control Circuit
All system memory chips are integrated on the ANT-RM board. If the EQUITY
III+/EPSON pe AX computer system has problem that system does not boot up, you
should better to replace the ANT-RM board first because you can determine if the
problem is caused by RAM chips or the other circuit.
2.3.3.1 RAH Chip type
On the ANT-P~ board, there are three kinds of RAM chips. (Refer to Table 2-3-6)
TABLE 2-3-6. FUNCTION OF RAH CHIPS
RAH CHIP TYPE Q'TY FUNCTION
256K-word by 1bit 16 System memory (512KB)
64K-word by 4bit 4 System memory (128KB)
256K-word by 1bit 2 Parity check
64 K-vlOrd by 1bit 2 Parity check
2.3.3.2. RAH Chip addresses
The system memory RAM chips are located in the following address.
09FFFF ------------------------------------------
080000 64K-word by 4bit RAM chips
07FFFF
256K-word by 1bit RAM chips
000000 -------------------------------------------
RAH CHIP ADDRESSES OF SYSTEM MEMORY
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2.3.3.3 Jumper Connector Function
We can disable the system memory by setting of the jumper connectors J1,J2 and J3.
TABLE 2-3-7. JUMPER CONNEC'IDR FUNCTION
J3 J1 J2
DESCRIP TION
A-C A-C A-C
AV AILABLE AREA 09FFFF TO 000000 (640KB)
B-C A-C
AVAILABLE AREA 07FFFF TO 000000 (512KB)
B-C B-C
AVAILABLE AREA 03FFFF TO 000000 (256KB)
B-C AV AILABLE AREA NONE ( OKB)
2.3.3.4 Operations of Memory Contro! Circuit
1) ADDRESS SIGNAL
The CPU outputs address signal (AO to A23). Next, the GAATM2 (Memory
control gate array 2 ) receives from Al signal to A18 signal to make RM1
chip address signal. Also, the GAATM1 (Memory control gate array 1 )
receives from A17 signal to A23 signal and AO signal to make a RAS signal,
a CAS signal and etc.
< REKARK 1 >
The GAATRF controls A20 signal.
< REKARK 2 >
SAO signal on the GAATAB is not used by memory control circuit in RAM read/
write mode. But it will used in the D-RAM refresh mode.
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2) DATA SIGNAL
GAATDB controls data bus by its internal data bus buffer.
3) READ/WRITE CONTROL SIGNAL
CPU outputs SO, SI, M/lO signals. GAATCK receives these signals and makes
MEMRN and MEMWN signals. GAATM2 receives MEMR and MEMW signals to control
RAS and CAS signals. Also, GAATM2 receives XMWN (MEMWN) signal which has
flowed through GAATCB to make WE signal of the RAM chips. GAATMI receives
XMRN (MEMRN) signal which has flowed through GMTCB to make RAS, CAS
signals.
4) RAM CHIP CONTROL SIGNALS
All D-PJlli control signals are sent from GMTM2.
5) D-RAM REFRESH CONTROL ClRCUlT
Refer to Section 2.3.11.
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RA""
RA""
CHIP
CHIP
FIGURE 2-3-5. INTERNAL MEMORY COBTROL CIRCUIT
GAATAB GAATRF
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Used for address sel.ct1ng
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2.3.4 Byte/Word Access & 16-8 Bit Data Conversion
The CPU has the following data access modes.
16-8 bit data conversion means word transmission of even address (8 bit device).
TABLE 2-3-8. CPU DATA ACCESS MODES
ID. MODE DATA TRANSMISSION 1'0; REFERENCE
1) BYTE TRANSHISSION OF EVEN ADDRESS 16-BIT DEVICE Figure 2-3-7
2) BYTE TRANSMISSION OF ODD ADDRESS 16-BIT DEVICE Figure 2-3-8
3) WORD TRANSMISSION OF EVEN ADDRESS 16-BIT DEVICE Figure 2-3-9
4) WORD TRANSMISSION OF ODn ADDRESS 16-BIT DEVICE
5) BYTE TRANSHISSION OF EVEN ADDRESS 8-BIT DEVICE Figure 2-3-10
6) BYTE TRANSMISSION OF ODD ADDRESS 8-BIT DEVICE Figure 2-3-11
7) WORD TRANSMISSION OF EVEN ADDRESS 8-BIT DEVICE 16-8 BIT DATA CONVERSION
8) WORD TRANSMISSION OF ODD ADDRESS 8-BIT DEVICE Figure 2-3-12
2.3.4.1 Data Bus Control Signal on GAA'IDB
The GAATDB includes five 8-bit buffers. This buffer needs a gate control signal and
a direction control signal. The following table describes gate control signals and
direction signals.
TABLE 2-3-9. FUNCTIONS OF CONTROL SIGNAL ON GAA'IDB.
SIGNAL NAME
DESCRIP TION
D245, G245
GHDHN, GMDLN, DHD
GDHN, GDLN, DD
CBA, SBA
Controls data bus conversion (High byte --> low byte)
(Low byte --> High byte)
Controls Memory data (Disabling, Direction control)
Controls CPU data (Disabling, Direction control)
Controls data latching (With 16-8 bit data conversion)
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2.3.4.2 Circuit Operation of Data Conversion
1) BYTE TRANSMISSION OF EVEN ADDRESS (16-BIT DEVICE)
Figure 2-3-7 shows the GAATDB internal circuit operation.
2) BYTE TRA1\JSMISSION OF ODD ADDRESS (1G-BIT DEVICE)
Figure 2-3-8 shows the GAATDB internal circuit operation.
3) WORD TRAT\fSHISSION OF EVEN ADDRESS (1(";-BIT DEVICE)
Figure 2-3-9 shows the GMTDB internal circuit opera.tion.
4) WORD TRANSHISSION OF ODD ADDRESS (16-BIT DEVICE)
The CPU operatrs as folIows. First, the CPU executes the
ODD ADDRESS (16-BIT DEVICE). Next, the CPU executes the
EVEN ADDRESS (16-BIT DEVICE). When a software programrner
do the WORD 'fRANSMISSION OF ODD ADDRESS (16-BIT DEVICE),
instruction 'vith the above steps automatically.
BYTE TRANSHISSION OF
BYTE TRANS~lISSION OF
instructs t,he CPU to
the CPU executes the
5) BYTE TR;\;\JSMISSION OF EVEN ADDRESS (8-BIT DEVICE)
Figure 2-3-10 shows the GAATIlB internal circuit operat,ion.
6) BllE TR~NSHISSION OF ODD ADDRESS (8-BIT DFYICE)
Figure 2-3-11 and Figure 2-3-12 show the GA~TDB internal c rcuit operations.
(Read mode --- Figure 2-3-11, Write mode --- Figure 2-3-12
7) WORD TR~\jSM1SSION OF EVCN ADDRESS (8-B1T DEV1CE) : 16-8 bit data conversion
Figure 2-3-13 and Figure 2-3-14 show the GAATDB internal circuit operations.
(Read mode --- Figure 2-3-13, Hrite mode --- Figure 2-3-14).
In this section, there are two important signals. One is a COFF signal, the
other is a XAO signal.
COFF SIGNAL
The GAATRF outputs this signal. The GA.ATCK receives this signal to make two
8-bit device read/write signals. Also, the GAATDB receives this signal to
catch a low byte data by the internal buffer LS646.
* Hhile the GAATCK req'.ives an active COFF signal, a read/write signal of the
Q~TCK will be inactive.
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The GAL\TRF outputs this signal. In the 16-8 bit data conversion mode, the
GAJ\TI~F does not use a CPU AO signal to make a LSAO signal. (This means, the
internal circuit of the GAATRF generates the LSAO signal but not in the
conversion mode, the GAL\TRF uses the CPU AO signal to make LSAO signal.) The
internal buffer LS646 of the GAATDB inputs this signal (XAO signal) to send the
catched data to t,he CPU. Also, the 8-bit device receive this signal to
determine address. 'Ifuile a 16-8 bit data conversion, this signal changes
status as low to high.
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To int......l
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GAATCK _r"O,...._ ..
MENR. MEMW. OR .nd IOW
~"'~' "~""1
GAATAB
I>AAHIF GAATMI
tt'"
lSAO ~
be_n 16 .nd 8bitJ
IAO clrcult
1fF.'~~'"'l]' lAO
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~~"';~1~ AO ~ C:~''''10n
..-- D245 }liiise signals oro ,J
tput by decordlng
signals beeane disabled. ~ G24SN XAll.nd XIIllE slgn.ls
C~~:ill
r-- CDFF ...
[~ GAATCK ree:oiv.s an aeUv. ClFF signal. .1
the road/write signal of GAATCK goss inecUve.
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DU A GDlN
CPU GAATCB
~ signals are, r--- DMD
.... output by
:;.E.. '''~i:.1l.,l Si~ decoding OTR
l5AO .nd IM
.....-
51'7'815.
IHE BHE
GAATIO GAATMZ
TC
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CPU
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GAATDB
)'i] : LI.... :
D245r-
~~ G245
k~ ~ GMDHNr-
2
•s
~ GMDlNr-
III 024S Equl••l.nt DMD
024s. Inte.....1
-
Circult GDHN
-
GDlN
TD OPTION SLOT
---------- 8 bit D.t. bus
"UJ210
FIGURE 2-3-6.
BYTE/WORD ACCESS &
16-8 BIT DATA CONVKRSION
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S8A lAD) l
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CPU
rA
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01- 00
t ••• REAO
00 lOIA) H ...IIRIIE
GOlN l,H
~~~~~~~~~~~ GOHN CU I COFF) l l
I I i SBA (AO) H
{
BkA
2
B 4 A
5
DIA
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I 0245
G245N H
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14015
2
'"'08
Bk A
2
B 4 A
5
~ 0245 l
i: G245N l
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f-------- ~~gr~ I :~~) r
G,",OHN I 8HEIl
, G,",OlN (AO) ,H
1================= 0'"'0
S01", SOO 5015"" S08
OPTION SlOT OPTION SlOT
FIGURE 2-3-7. DATA TRANSMISSION 1'0 16 BIT DEVICE
(BYTE TRANSMISSION OF EVEN ADDRESS)
FIGURE 2-3-8. DATA TRANAMISSION 1'0 16 BIT DEVICE
(BYTE TRANSMISSION OF ODD ADDRESS)
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Bk I.
B'
2
I.
5
DIR
C
Operotes OS 0 buffer. At the
}~:tBgt~rI:' '~~~h~:~' dote
When the SM goes hIgh, th.
doto latched by th. eR" s Igno'
Is output.
I DUS
GUSN H
1
'Only .hen reedtng t:-'" internal
"""""ry thls slgno' goes hIgh.
DMD'
1-------- GMDHN (BHE I l
!--------GMDlN (1001 l
!
a
~
~
OO
(OIRI{~
GDHN H
GDlN l
CU l
SBIo (1001 l
READ
WRlrE
I. t B
S
2
I. , 8
5
C DIR
8 kI.
8'
2
I.
5
DIR
C
I DUS
GZASN H
0
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MOG
OPTION SlOr
SOlS"" SOl 507'" 500 507'" 500
FIGDRE 2-3-9. DATA TRANSMISSION TO 16 BIT DEVICE
(WORD TRANSMISSION OF EVEN ADDRESS)
W '-l
I. AB
Io~B
5
C DIR
I
DMD
--------------~=gr~I:~~' r
11 blt
FIGDRE 2-3-10. DATA TRANSMISSION TO 8 BIT DEVICE
(BYTE TRANSMISSION OF EVEN ADDRESS)
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~~~~~~~~~~~GDHN l
I, , ~::N(~OI H
­At B
s
2
A , B
5
II
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Dlet I
I 0245 H
G24SN l
~
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At B
S 2
A , B
r;
DIA
5
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OMO
1------- g~gr~ : :~il ~
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Shit DEVlC[
FIGURE 2-3-11. DATA TRANSMISSION TO 8 BIT DEVICE
READ MODE
(BYTE TRANSMISSION OF OnD ADDRESS)
r
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CPU
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11
-
....--.-- A ~ S ,I Al~2'5Ai .11 i Cii~S6': ~ ~I
, 8 8
-
. 8 888
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A , B 2
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* The 8 bit device reads Data 1.
* The 8 bit device reads Data 2.
015-0'
CPU
01- 00
, ~ ~ " G~~al!
i i 'i
i , heft .ddren date
~
OO N
GONN l
GOlN l
C.. l
se... l
I ..rc/I OUS
~h----I G'''5N H
I OMO
GMDHN l
GMOlN l
cl
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1
• 4 •
5
~ 01.
CPU
. ,",li.ß1. if::~
·i·
• 4 •
5
0'.l:
I OIU
GUSN H
1:===== ,: :::HN GMDlN
cl
4--
-. t"
5 1
• 4 •
l:
01.
5
015- 01
CPU
II 'I I' II ,."I
0'Ġ'
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GDHH l
GDlN ce- H
H
S8" H
I blU l
GUSN l
GM""" l
I~====== , DMO GMb... " ..
8Mt o[Vla "hit DUltl
Ilbtl Ill:YIC(
FIGURE 2-3-14. DATA TRANSMISSION TO 8 BIT DEVICE
(WORD TRANSMISSION OF EVEN ADDRESS)
16-8 BIT DATA CONVERSION
-- WRITE MODE
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2.3.5 "C
1/0 Device Access Circuit
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The GAATrO makes r/o device chip select signals by decording address signal.
An ALS245 is used in the data transmission between the CPU and the r/o device.
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GAATCK
GAATAB
GAATAF 4237A-5 80287
l,SA.\... I LSAO I ..,....~ eMOO
::~:::~ ~~ eMD!
••4.1.3.3
~
NIIWrl
NP51
NPS2
110 deV1C' L-'
DIA}
I[
825"-2
$~~. I
GAAICB
10 GAATRF
0'"
~Io- IO~A
~
8254-2 146818
GAATIO
.,..
rff
110''''
DOWN
A/Vi
"'OS
AS
cso..c POWER
015
CSDIII
~r-SUPPLY
SIGNAl.
CI.t.
(
eS'lII
DO
CS"'''
GAATOB
",d
IlCSN
CSUN
T. 8blt 1/0 devlce
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FIGURE 2-3-15.
1/0 DEV1CE ACCESS C1RCUIT
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2.3.6 DMA Contral Circuit
There are two DM controller on the main board (ANTA BOARD). A DMA1 (Ioeation: 2F)
eontrols an 8-bit data transmission. A DMA2 (loeation: 2E) eontrols a 16-bit data
transmission. It requires a page register to output address signal from A16 to A23.
The page register is ineluded in the GAATIO.
This seetion deseribes the following items.
1) Page register setting eireuit
2) 8-bit DMA (Internal memory -- 1/0)
3) 8-bit DMA (Internal memory -- Internal memory)
4) 16-bit D}1A (Internal memory -- 1/0)
2.3.6.1 Page Register Setting Circuit
The GAATIO ineludes a page register. The funetion of the page register is identieal
with T1L IC LS612. Table 2-3-10 deseribes about the function of LS612.
TABLE 2-3-10. EXPLANATION OF LS612
PIN NA!'lE
HJ\fCTIONAL DESCR1PTION
DO thru Dll
RSO thru RS3
R/-w
-STROBE
-es
!'lAO thru !'lA3
MAO thru HO11
-HE
1/0 connections to data and control bus used for reading from and hTiting
to the map register seleeted by RSO-RS3 \vhen -es i s 10w. ~lode eontrolled
by R/-W.
Register seleet inputs for 1/0 operations.
Read 01' \vrite eontrol used in 1/0 operations to seleet the eondition of
the data bus. \~hen high, the data bus outputs are active for reading the
register. w'hen lOH, the data bus is used to write into the register.
Strobe input used to enter data into the selected map regist.er during 1/0
operations.
Chip seleet input. A loh' input level selects the memory mapper (assuming
more than on used) for an 1/0 operation.
!'lap address inputs to select one of 16 map registers h'hen in map mode.
!'1ap outputs. Present. the map register cont.ents tu the system memeory
address bus in the map mode.
In tbe pass mode, these outputs provide the map address data on NOS-HOll
and low levels on 0'100-0'107.
!'lap enable for the map outputs. A low level allows the outputs to be
aetive while a high input level puts the outputs at high impedanee.
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The LS612 has sixteen 12-bit registers. The R/\~ signal and the STB signal is used
as a read/write signal with pair. The RSO to the RS3 is used as a select signal of
registers when data setting. The MAü to the NA3 is used as a select signal of
registers when output data written. When setting mode, data is sent or received
from "DO TO D7" pin. w'hen output mode, data is sent from "HDO to HD7" pin.
When the ME signal is active, data written will be sent from "HDO to MD7" pin.
2.3.6.2 8-bit DMA (Interna! Memory - 1/0)
Figure 2-3-17 shows the 8-bit DMA (Internal memory -- 1/0 ) operation.
In the DMA mode, a MEMRN, a MEMWN, a IORN and an IOWN signal are output signals.
(When CPU control mode, these signals are input signals.)
2.3.6.3 8-bit DMA (Interna! Memory - Interna! Memory)
Figure 2-3-18 shows the 8-bit DMA (Internal memory -- Internal memory) operation.
First, the DMA controller stores memory data. Next, the DMA cont roller changes
address signal and writes the stored data to the memory.
2.3.6.4 16-bit DMA (Interna! Memory - 1/0)
Figure 2-3-19 shows the 16-bit DMA (Internal memory -- 1/0) operation.
A DMA2 controls the 16-bit DMA. In this mode, the GAATRF outputs AO signal and
BHE signal. Both AO and BHE signal statuses are always low.
The DMA2' s AO signal is not connected to address bus bit O. Because the AO
signal is output from the GAATRF.
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G.... TCK G....UB G.... TRF
• Refer to the-,eetlon
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0
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:~~e;~O e~~~jt
x13_ I I
~H 0iZl
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to:l
• Refer to the seetl0.
for 110 de.lce
aeee.. elrcult
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G.... rOB
XIORN
I I I l M:~~ J: 11_Thl' '19na1 _s low
when the 1/0 addre..
80H through 9FH are
,eleetad.
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I I
for 1/0 de.l.e
leeess circutt
I 11-~I'--
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FIGURE 2-3-16. DHA CONTROL CIRCUIT I
(SETnNG OF PAGE REGISTER)
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GAATCK
10 GAATM21
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ino
OMA 1llOd. XAD ';9no1
;s usec! fo, on 1nputr;::::===============~
t .....1n.l ......---/,....1_ I
~ i I
GAATRF
OMAI
8237A -5
AEN
AOSTS OR03
Tölf )
TöYi OROO
·~·::~~) ..I y I~~e~ OACK3
WII
EOP I \
lAO AO OACKO OACKO
\
~" )
ORIOO OPT!rn
OACK3 T
H~OAt-
HRQ
-_.. _._ .. ,
11 I I I I I
CPU
OMA2
I 8237AD~:0~
HRQ~
HLOA I--
DACKOI--
I ~
L.....ft---t-IHRO
~H~DA In 0OMAI llMA2 1nh1b1ts ope"t10n
output IIOdI'j
s 1gools I.elpt HRO
0;9nol.
GAATOB
OPTJON SlOT To
1nter-nl1
RA'"
o
AODRESS
A8
S
A15
® GAA1Ml
o
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FIGURE 2-3-17. DHA CONTROL CIRCUIT II
(INTERNAL MEMORY (-)
-- 8 BIT DHA
I/O)
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GAATCK GAATAB C":l
GAATRF 8237A-5
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GAATDB
507
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500
... L5245
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To lnternal llAM
FIGURE 2-3-18. DHA CONTROL CIRCUIT 111
(IRTERNAL MEMORY (-) IRTERNAL MEMORY)
- 8 BIT DHA
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GAATCK
{
CPU
GAATM'
@
GAATAB
SAO ~".
\ :~ ,
SAI611 dll!"&9aMiad. ,..,
• exc.pt D-lIAM'
; ,refresh lIOde.
GAATCB
\.-1&0
lAI
\
AI' .... SAn'
.... =00: i WIe
@
GAATRF
GAATM'
• In o~~ to output .y.n add~ess to
_ry tha addNSS "AO" 119ft.1
1I kapt o.
AEN
I IADSTB
DMA'
8237A5
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2.3.7 Ready Signal Control Circuit
The GAi\TRF controls a wai t cycle insertion. The ,,,ait cycle is executed to allow
adeguate timing margin for internal chips and external chips. Ta reguest. wait
cycle, the GAi\TRF sends an ARDYN (Ready) signal and an AREN-.N (R.eady enable) signal.
The number of wait cycles is fixed except for a 16-bit ROH and a 16-1:üt 1/0 channcl
device. You ean select wait cyeles for the 16-bit RUri and the 16-bit, 1/0 channel
device by using jumper connectors ,]4, ,]5 and J6. But t.he seleetion is available
onJ y for lOt-lHz use.
TABLE 2-3-11. WAIT CYCLES
DEVICE 'ID BE ACCESSED WAIT CYCLES ['IDTAL CYCLES]
6MHzI 8MHz lOMHz
16-bit memory (16-bit bus operation)
DRAM (System memory)
(00000 to 9FFFF)
1 [3]
1 [3]
N
~M
(OEOOOO to OFFFFF &
FEOOOO to FFFFFF)
1 [3]
1 or 2 [3 or 4]
* NOTE 1
r/o channel
(Other range)
1 [3]
1, 2, 3 or 4
[3, 4, 5 or 6]
* NOTE 1
8-bit memory on r/o channel
(8-bit bus operation)
4 [6]
8 [10]
8-bit memory on r/o channel
(16-bit bus operation)
10 [12]
18 [20]
16-bit r/o on r/o channel
(16-bit bus operation)
1 [3]
3 [5]
8-bit r/o on r/o channel
(8-bit bus operation)
4 [6]
8 [10]
8-bit r/o on r/o channel
10 [12]
18 [20]
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(16-bit bus operation)
* NOTE1: A jumper connector can select wait cycles. Please refer to Table 2-3-12.
TABLE 2-3-12. WAIT CYCLE SELECTION
JUMPER NOMBER
6 5 4
NUMBER OF WAIT CYCLES
EPROM 16-BIT EX'I'ERNAL DEVICE
B-C
* *
A-C
B-C B-C B-C A-C A-C B-C A-C A-C
*
* --- Ignored
1
*
2
*1
* ***
2
3
4
2.3.7.1 Insertion More Wait Cycle
\~hen you want to insert more wait cycles, Please control the IOCHRDY (1/0 channel
Ready) signal. When the IOCHRDY signal is high, a wait cycle will be inserted.
2.3.7.2 Zero Wait Cycle Request
To insf'rt no wait cycle, a OWS signal is provided on the option slot. This signal is
low when active.
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GAATAB
GAATCB
GAATDB
FIGDRE 2-3-20.
GAATRF
GAATMl
GAATIO
GAATM 2
• lilien the low aethe OlIS .1911a1 1. ~t f ..... tho OpUon .lot. tho .alt
eycll 1S not ln,"rtod. (No .alt eycll)
READY SIGNAL CONTROL CIRCUIT
OPT ION)
, 0 OWS SLOT
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2.3.8 Command Delay Signal Control Circuit
Some devices can not allow the standard following time (T) because it is tao
short. The command delay signal control circuit makes adequate timing margin for
these devices.
To execute command delay function, it is necessary to send a CDLY (Command
delay) signal to the GAATCK. The GAATRF outputs a CDLY signal when it detects
the following mode listed in Table 2-3-13 automaticaly.
FIGURE 2-3-21. TIMING BETWEKN ADDRESS SIGNAL AND READ/WRITE SIGNAL
ADDRESS ------v'.
SIGNAL ~
READ/WRITE
SIGNAL
\/
w.
TABLE 2-3-13. CONDITION OF TRE CDLY SIGNAL OU"JPUT
CONDITION OF TRE CDLY SIGNAL OU"JPUT
1
2
3
1NTA mode
1/0 read Iwrite mode
8-bit memory read/write
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50
IoI/11l
CPU
GAATAB
(R.f n••)
Dlff n•• bet_n READY slgn.1 .nd COItlAND DELAY
slgn.1
Thes. slgn.15.re
.ontroll.d by COLY
slgn.1 .nd output
.ft.~ 1 O~ 2 • lock
d.1.y fo~ tIIe CPIJ
Input clock "CLK".
Stltus .nd {
Control
slgn.ls
READY
i
mrcßY~
(1) INTA _.
(2) IID ....d. lID Wl"lte
(16 bit o~ e bit __)
(3) .......,. ....d I .......,. Wl"lte
(Onlye bit d••l••)
READY \
CXlItWlD \ 1,-----
GAATCB
~
CXlItWlD DELAY slgn.1
GAATIO GAATM 2
TS TC TC Ts
Sl.50~
(~Bdl
ISulp~~(
CIoIDLY ~""_--1,...... _
READy~.r----
GAATDB
FIGDRE 2-3-22. COMKAND DELAY SIGNAL CONTROL CIRCUIT
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INT..H
CAS2
CASI ~/rN
CASO
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GAATIO
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NE'"' \
Al.S245
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If the data is s.t to tha outout
date bus buffe. registe. of the
IRl4 (1/0 slot )
IRl5 ( .. )
IRJ TRJ ( 110 slot )
IRO 8254 OUTO
IRI 8042 (8742) P24
IR2I-
IR4 IR4 ( H )
IR5 IR5 ( .. )
IR6 ~ IR6 (
H
, H: MASTER IClDE
1119 (1/0 slot )
IRIO ( H )
IRll ( H )
IRl2 ( H )
" L: SLAVE IClDE
2.3.9 Interrupt Control Circuit
This circuit includes two interrupt controllers to support 15 level interrupts.
Two INTCs are connected by a cascade mode.
Figure 2-3-23 shows interrupt control circuit operation.
@4 Yli/JA 0'
Most"r l8042(8742). thls signal go..
8259 A-2 act1ve
INTA IR' IR' ( .. )
I .. lINTA ~/!Ii
GAATC ~ I I "'U
l ~IR
@" v»)))J
InteM"Vllt ••etor
f..... the I..er 7b1ts
of the date bus.
G.... TDB
146818 IRQ
.0217 EAItO't
002" lIUSf
IHLOA•••H ~ SDO
MSTR...H I
others•••L
When the IHTA s1gnal 1s aeth.,
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FIGDRE 2-3-23. INTERRUPT CONTROL CIRCUIT
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2.3.10 ROM Access Circuit
There are two pairs of ROM sockets. One is used by BIOS ROM. The others are free
sockets for user. We can select ROM socket and ROM size by setting of the jumper
connectors J4, JS, J6 and J7. Functional description of each jumper connector is
explained in CHAPTER 7.
2.3.10.1 Available ROM Types
You can install the following type of ROM chips.
TABLE 2-3-14. AVAILABLE ROM TYPES
ROM TYPE RECOMKENDED ACCESS SPEED JUMP ER. SEl'TIRGS
J4 J5
27128, 2764
200ns or more higher
A-C A-C
27256
200ns or more higher
B-C B-C
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TOGur...B
... 10
50-N
5J-N
5'
50
..."m
... 16
...,
ROYN
CPU
READY
015
00
CP
...)' ?f~i~
AI6 OXA
GAATAB
GAATRF
GAATMI
GATE
LA~CIl
XAI
~
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... REYN
READY
CONTIlOL
eIRCUlT
GAATCB
._. ••••••••••. ,dd es eSFN Ind CSEN 5la.ll lethe
eSFN CSEN
XAJ-XA16 OFoooo - OFFFFF OEoooo - OEFFFF
FFoooo - FFFFFF FEoooo - FEFFFF
OF8OOO - OFFFFF OFoooo - OF7FFF
XAJ-XA15 FF8000 - FFFFFF FFoooo - FF7FFF
OE8OOO - OEFFFF OEoooo - OE7FFF
FE8000 - FEFFFF FEoooo - FE7FFF
GAATDB
o
FIGDRE 2-3-24.
ROM ACCESS CIRCUIT
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2.3.11 D-RAM Refresh Circuit
A timer counter (8254-2) controls refresh interval time. The refresh address is
sent from a 8-bit binary counter in GAATAB. During D-RAM refresh, the CPU
executes a bus hold cycle.
The RFNO (Refresh output) signal is an important signal. From this signal, the
GAATM1 makes a RAD and a RA1 signal (RAS signal). The GAATM2 controls the
refresh address by using this RFNO signal. And more, this signal is used by the
8-bit binary counten as a count-up signal.
Figure 2-3-25 shows the D-RAM refresh control circuit operation.
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GAATCK
GAATAB
GAATRF
l5590
abil bln.~
RSN I=-=v=:;. 1115_ Counter
$"~Q G GWONI.. I I I
\ CD< C"O
,... 110<
®
GAAT"'2
C PU
GAA TCB
~:::N
HRQ
HLDA
L"'E"'RN
GAA T10
GAATOB
1/
Por +2 B
±:AlN
1/0 reg1St.r
61H bit'
Ifmlrnj
10PTlON SLOT)
.....
FIGURE 2-3-25.
D-RAM REFRESH CIRCUIT
GAAT""
WE
These signals always
kept low.
AAM Chip
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2.3.12 RAH Parity Check Circuit
In a D-RAM write mode, the GAATM1 generates a parity data. When in D-RAM read
mode, the GAATM1 calculates the memory read data and the parity read data. If a
parity error has occurred, the GAATM1 outputs a PCKN signal. The GAATIO receives
a PCKN signal and makes a NMI (Non maskable interrupt) signal.
Figure 2-3-26 and Figure 2-3-27 show the RAM parity check circuit operation.
~ ~
GAATRF
GAATMI
MPll
MS81256
0'
I'qui'#Glent
01
"P04164
equivaient .'
CPU
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MB81256
.,
equivalent
01
"P04164
equivQ'.nt .'
llillQ GAATM2
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FIGURE 2-3-26. RAH PARlTY CHECK ClRCUIT
(DATA WRlTE MODE)
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- _.... -- - ~
AATRF GAATMI J
I .....
r--
~CKN ~ 00
L 00
• • ""811256 J'P04164
0' 0'
equivOlent eQUivolent
~ ,,~
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~~~1Sr
...21-
~ko'r 01
~ 00 L 00
'rni..~ bo
03
0 1 0
FIGURE 2-3-27.
RAH P ARITY CHECK CIRCUIT
(DATA READ KODE)
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""'11256 }IP04164
0' 0'
eQuivalet ~uivQlftlt
NMl ~
'---
GUTtO GAA TM2
lc.
N""I !'Cu
@
""811256 ""811464
or la @ or .2
eQu;volent ..qui vo'e"t )
03
r f-
I
IN'.- 00 - 00
GAATDB 110 Raoi,te' I
n
""811256
""811464
.,
.2
or
®
or
eQuivolent
t eQuivolent ~

N
2.3.13 Speaker Control Circult
o
The timer counter controls the speaker.
circuit operaton.
GAATCK GAATAB GAATRF
I
0\
Figure 2-3-28 shows the speaker control
8254-2
i _!GATEZ
C~KZ
EH;]
i IOUTZ
CPU GAA TCB
* ~,&ede~c;":cg::lg~~:rt.
8ltO 01 l/O aeldreSl 61H
(Ti.... "g.UZ" OIlIOFF
contraI blt)
GAATDB
8ltl 01 1/0 addreSl 61H
(Speake~/OFF contraI bl t
O•••OFF 1•••0Il
Speike,
FIGURE 2-3-28. SPEAKER CONTROL CIRCUIT
~
~
~
~
~
CI)
o
'z:l
o
~
t:r.i
~
~
!2:
~
5>

N
~,...
2.3.14 Keyboard Interface Circuit & Other Circuit
A Keyboard controller (8042 or 8742) includes the following functions.
1) Keyboard interface
2) RAM size reading
3) Monitor setting reading
4) Disabling keyboard scan codes
5) Software reset signal generation
6) Address A20 signal control
2.3.14.1 Keyboard Interface
When receiving keyboard data, the 8042 receives keyboard data from test 1 pin.
~en sending a keyboard control command, the 8042 sends command data from P27
p1n.
When the 8042 receives keyboard data, it sends an interrupt request signal from
P24 pin. P26 pin of 8042 outputs control signal of keyboard data transmission.
In detail, (Refer to section 2.2)
2.3.14.2 RAM Size Reading
The 8042 reads the condition of jumper connector J2 on the ANT-RM board.
2.3.14.3 Monitor Setting Reading
The 8042 reads the condition of slide switch SW1 on the ANTA board.
2.3.14.4 Disabling Keyboard Scan Codes
The P17 pin of 8042 inputs the condition of the key cylinder switch. When P17
pin is low, keyboard scan code will be disabled by the 8042 internal circuit.
2.3.14.5 Software Reset Signal Generation
The 8042 outputs software reset signal from P20 p1n.
~.>
"tl
~
~
~
~
o"d
o
"tl
E i

N
~
2.3.14.6 Address A20 Signal Control
N
The 8042 outputs A20 control signal (gate) signal to GAATRF.
GAATRF controls A20 signal as below.
TABLE 2-3-15. A20 SIGNAL CONTROL BY GAATRF
~O A20G A20
* ---- DON'! CARE
010
111
* 0 0
'"d
~
1-1
~
~
o
"Zj
~
~ i
~
>

N
~
IJ,)
KID CLK
KID DATA
GAATCK GAATAB
GAATRF
GAATMI
"" ........ ,...
..... AZO
RC
f1
CAZO_ :;
~ AZOG_ r~ AMT-RM bCICI'cl
JZ
0
-=
AZO_- AZO
CPU GAATCB o-r- JRAL
~
GAATlO GAATMZ
.-- YQ~
r- Y I
r
SWI
PI'
~ PI'
8042(8742)
~!y~!y PU f-
PZ& I+-+-
TESTO PZ'
TESTl
I--~
P'Zl I+-Iro:::tJi
~ Pl1
PZO I+-
GAATOB
Key Cylinde. Swltch
l
FIGURE 2-3-29. KEYBOARD INTERFACE AND O'l'1lER FUNCTION CIRCUIT
~.>
"tl
~
~
~
o"":l
o
i
"tl

N
I
C7I
~
2.3.15 1/0 Slot Access Signal
Figure 2-3-30 shows the r/o slot access signals.
GAATCK w
cer
SROYN
AEN
HLOA
PWGO
GAATAB
GAATRF ~
1 1
I
SAO~ WSON~ ows;
IROY OMACl &ALE
~
aALEl-
SAI& 10CHROY;
OACKy. r--
AEN;
MSTR
~l .
3
i RESET ORW:
OSC;
RSON ORQO
,. ORQO.1.2.3.S.5.7
OSC
T/C
IOWN.IORN
2'
- EOP J' - OACKO.1.2.3.5.5,7
SCLKI-- lOR
MEMRN
~IOW
MEMWN ~
CLK
OMAC2
~SAO-19
lOl&N I+-
OACK 5, :-. a SOO-15
Ml&N f-ol
CPU GAATCB ORQS, ~
L
~. IRQ J.4,5.5 .7.9 .10,11.12.14.15
-MEMR
~-MEMW
~ lORN,lOWN SA17
~
-IOCS1&
}
-MEMCSI5
\ EOP
©--+oLAI7-Z3
SA" -MASTER
,--.0 saHE
GAATIO ,-POWER GOOO
LAI7
t.....
l-@ IHTC SMEMW
I IR3 ,
SMEHR
LA23 7,
MEMRN 9
MEMWN 12
cgNOl1
::
~ GAATOB
RTC(145818l )
SOlSr
SOO
1/:
I
NOIZ 15'
NOQ
saHEN
I .... .... I....
.... .... .... es
FIGDRE 2-3-30. 1/0 SLOT ACCESS SIGNAL
'"Cl
e:1
~
~
tn
~
o
"z:l
~
tz.l
S
~z
~ •>

REV.A
PRINCIPLES OF OPERATION
2.4 MULTI-FUBCTION ADAPTER (SPFG BOARD) OPERATION
2.4.1 Serial Interface
A 16450 is used as aserial data controller. The XTAL1 terminal receives
1.8432 llilz clock generated by the OSC terminal in the gate array GAATSP.
2.4.1.1 16450 Chip Select Circuit
Chip select signal CS2 for activating the 16450 is applied from the gate array
GAATSP (SCSN signal). There are two kinds of 1/0 addresses which SCSN signal
activates. They are selected by jumper pin J5 and J6. Setting of J5 and J6
are listed in CHAPTER 7.
SCSN
Ir-------I-~es 2
8
SIFO~--oQ_
B
SIF 1t---

PRINCIPLES OF OPERATION
REV.A
2.4.1.3 Data Buffer Direction Control Signal
While the serial or parallel port is read, the DDIR signal generated by the
gate array GAATSP DDIR terminal is kept low.
2.4.2 Parallel Data Control Circuit
The gate array GAATSP
controls parallel data.
2.4.2.1 1/0 Address Selection
There are two kinds of 1/0 addresses on the parallel Data control circuit.
They are selected by jumper pin J3 and J4. Setting of J3 and J4 are listed in
CHAPTER 7.
GAATSP
PIFO
PIFl
C A J4
9
FIGURE 2-4-2.
1/0 ADDRESS SKLECTION
2.4.2.2 Parallel Data Control Circuit Functions
Parallel Data control circuit has the following six functions.
1. Data output circuit
2. Output data read circuit
3. Printer control signal output circuit
4. Printer control signal read circuit
5. Printer status read circuit
6. Interrupt signal control circuit
2-66

HEV.A
PRINCIPLES OF OPERATION
Data Output Circuit
Direetion of data is only from CPlJ to Printer beeause the DIR of ALS245 is
fixed at low level.
GAATSP ALS 245
SD7 SD7 OD7 B A DATA7
) )
r
CI
M-
n
=r
) ~
SDO SDO CLK ODO DATAO
DIR
FIGURE 2-4-3. DATA OUTPUT (PRINTER DATA REGISTER WRITE)
Output Data Read Circuit
The output data for printer ean be read via LS244
S07
\
I
0 0
OLO
soo f-
~:
OS 8 r- .-
o~~ f- r- ~
...........
I-- f- ........
-
~ OE
r"_
f- y Af-
~ Y L Af--
-y S Ar--
-y 2 Af--
-y 4 Af---
=~4~~
-y A
~L
I
I~oo: J
FIGURE 2-4-4.
GAATSP
Printer Control Signal Output Circuit
loeated in the GMTSP.
1 007
f- ~ 000
OU1PUT DATA READ CIRCUIT
~
GAAT5P
bil"
507 507 OIRE
.-- 0511 5LCT IN
'"

PRINCIPLES OF OPERATION
REV.A
Printer Control Signal Read Circuit
----------------------------------,----_.".._-
GAAT5P
50 4 ().-----i504 ...----,
cr-----i50 3
cr----!502
().----!50 1
500 C>----I500
OIRE
05L1
5LCTlN
OINT
INIT
OATF
05 TB ~t-1I--4P------o AU T0 FOx T
~t-1t-1I--4.-----O 5 TROBE
5LN
INI
ATF..-----'
5 TB!4-----'
FIGURE 2-4-6.
PRINTER CONTROL SIGNAL READ CIRCUIT
Printer Status Read Circuit
GAATSP
S07
\
S03
S07 - l t-BSY
BUSV
S
S06 - 2 I- ACK - ACK
4
SOS - 4 I- EOP.
PE
S04 - t-Sl P
SlCT
S03 - G
t- ERR
•
I ADORESS
lJECOOER
I
ERROR
FIGURE 2-4-7. PRINTER
STATUS READ CIRCUIT
Interrupt Signal Control Circuit
-------------~---~.-.~.
JRS
JR7
... ....--
- B
J10
-
C
- ___ A
>'
OJRE
I",I RE')
bit"
ACK
GAATSP
FIGURE 2-4-8.
IlITERRUPT SIGNAL CONTROL CIRCUIT
2-68

REV.A
PRINCIPLES OF OPERATION
1.2 MB PDD
EQUITY II / EPSON PC+' s 1.2MB FDD (SD-581L) can not be installed on EQUITY
111+ / EPSON PC AX. Because FDD control signals are different between EQUITY
II / EPSON PC+'s 1.2MB FDD and EQUITY III+ / EPSON pe AX's 1.2MB FDD.
(Refer to Table 2-4-2)
TABLE 2-4-2. DIFFERENCE BETWEEN 1.2MB PDD OF SD-581L AN» FDl155C/MD5501
PIN NO.
2
4
6
8
10
12
14
16
18
20
22 (*3)
24
26
28
30 (*3)
32
34
OTHER PIN
SD-58lL(*1)
MODE SELECT
DISK CHANGE
DRIVE SELECT 3
INDEX
DRIVE SELECT 0
DRIVE SELECT 1
DRIVE SELECT 2
MOTOR ON
DIRECTION
STEP
WRITE DATA
WRITE GATE
TRACK 00
WRITE PROTECT
READ DATA
SIDE SELECT
READY
GND
FDl155C/MD5501(*2)
MODE SELECT
(NOT USED)
DRIVE SELECT 3
INDEX
DRIVE SELECT 0
DRIVE SELECT 1
DRIVE SELECT 2
MOTOR ON
DIRECTION
STEP
WRITE DATA
WRITE GATE
TRACK 00
WRITE PROTECT
READ DATA
SIDE SELECT
DISK CHANGE
GND
NOTE (*1)
(*2)
(*3)
SD-581L is used in the EQUITY II/EPSON PC+.
FD1l55C and MD5501 are used in the EQUITY III+/EPSON PC AX.
The difference of read/write data between SD-581L and FD1155C/
MD5501 are shown in below.
U1J
I... T '>~. 1. 5T
U
+~2_T~
L
(NORMAL DENSITY MODE)
SD-581L ....•..... T 4 us
FD1155C/MD5501 ... T 3.33 us
(HIGH DENSITY MODE)
SD-581L T 2 us
FDl155C/MD5501 T 2 us
2-69

PRINCIPLES OF OPERATION REV .A
2.4.3 FDD Control Circuit
FDe
GAATFD
B
Cl
°S7
FO 11
~
00 0 A
..... FOIO
es
3F4,3FS
FCSN
(3T/4.375)
WR
AOORESS
RO
OECOOER
H
rq
C
A J 2
ALS245
DIR
IOW IOR
BOIR
FIGDRE 2-4-9. FDD CONTROL CIRCUIT I (FDD (-) CPU)
2.4.3.1 FDD Control Register Access Circuit
There are three kinds of r/o addresses on the FDD control register access
circuit. They are selected by jumper pins J2 and J1. Setting of J2 and J1 are
listed in CHAPTER 7.
2.4.3.2 Interrupt Signal and DHA Request Signal from FDC
,--------------
IRQ'
IH1
FOC (765)
ORQ
"'OfF
OQ.OY
VQ
I bit] I
0ACii I+- CIJICU[T ,~ .,
,-- ORa
ORGZ
T
'CAH-a-
~ CAKH CR!!H
GM1FO
CA( KZ
---,------,------------------------------
FIGURE 2-4-10. INTERRlPT SIGNAL AND DHA REQUEST SIGNAL FROH FDC
2.4.3.3 FDD Control Signals
MFM/FM signal of FDC is not used. MFM/FM is se1ected by a software command.
Disk Change Signal
\V"hen 1/0 address 3F7H or 377H is accessed, low level signal output i8
generated from the 3X7N terminal in the gate array GAATFD, and the disk change
signal from FDD 18 applied to SD7 signal.
2-70

REV.A
PRINCIPLES OF OPERATION
2.4.3.4 Read/Write Circuit
Write circuit
Figure 2-4-11 shows the FDD
data write circuit.
FDC(765)
ClK
ClK
a..OCK
WClK WClK CIRCUIT
AODRESS
ClK DECODER FOl1 00
J 2
WOATA FWO
wo
WRT
PS1
PS1
OATA
(FOO )
PSO
PSO
WE
WE
GAATFD
FIGURE 2-4-11.
FDD DATA WRITE CIRCUIT
* FDD register of the SPFG board can select PC/AX mode and PC/AT mode by
jumper switch (J2).
In case of the pe/XT mode, CLK and WCLK output generated in the gate array
GAATFD is fixed.
Note: When jumper connectors J1 and J2 are set to 0,0, it is impossible
to access the FDD register.
2-71

PRINCIPLES OF OPERATION
REV.A
Read circuit
The VFO
circuit has the following modes.
Data transmission speed
1. SOOK bps mode
2. 300K bps mode
3. 2S0K bps mode
These modes are selected by AO~ DO~ D1~ WR and 3XVN signals.
FDC(765)
VFO
WINOOW WINOOW RAW RO
-
RO OATA - RO
SYNC
. SYNC
C{=:
AO
00
~---. 01
----. WR 3XVN WClK
I'
REAO
OATA
3XVN
WClK
GAATFD
FIGDRE 2-4-12.
FOD DATA READ CIRCUIT
2-72

REV.B
PRINCIPLES OF OPERATION
VFO
circuit
The VFO circuit inputs a RAWRD signal and generates a WINDOW signal which
synchronizes a REWRD signal.
When FDD is not in read operation, VFO circuit synchronizes a WCLK signal.
The VFO circuit will synchronize, whether a weLK signal or RAWRD signal is
selected by SYNC signal.
(Whether the VFO circuit is synchronized \vith lJCLK signal or RAWTD signal is
selected by SYNC signal.)
. When 500Kbps
or 250Kbps,
this signal
becomes active•
VCO
IC
WINOOW o-_f-1 1/2
. EI
f -,
IIIlen JOO

PRINCIPLES OF OPERATION
REV.A
2.4.3.5 Other Functions
Terminator
terminator.
1S attached for all FDDs. There is no need to disassemble a
Because EPSON FDD uses 1K ohm terminator.
(PSON
'OD
HOST ... sv OItIVE A
DRIVE 8
FIGURE 2-4-14.
FDD TERMINATOR FUNCTION
FDD
Special Signal Cable
When changing setting of floppy disk drive number (A or B), it lS not
necessary to change floppy disk drive jumper setting.
You can change the setting of floppy disk drive number by modification of the
connections on the floppy disk drive signal cable.
SPFG BOARD
~--{i$
SPFG BOARD
( ~
DRIVE A
~
DRIVE B
FIGURE 2-4-15.
FDD CABLE SETTING
2-74

REV.A
PRINCIPLES OF OPERATION
If DS1 signal output is generated at the host side, drive A is selected. If
MT1 signal output is generated, motor in drive A is turned on.
If DS2 signal output is generated at the host side, drive B is selected. If
MT2 signal output is generated, motor in drive B is turned on.
FIGDRE 2-4-16.
DRIVE SELECT AND MOTOR ON SIGNAL SlPPLY CIRCUIT
* Always set the drive select jumper switch to DS1 (Drive Select 1).
OJGNO
GNOep
CHANGE
I
GNOm
DSO 10
GNO 11
DSl 1
GNO 13
DS2 14
GNO
MOTOR ON 15
'--------'-'-:....;..,;:...;.;,...-;:..;.'-116
GND~
I
I
I
I
DISK CHANGE ~
IORlv'1
FIGURE 2-4-17.
FDD SPECIAL SIGNAL CABLE
2-75

PRINCIPLES OF OPERATION
REV.A
Hard Disk Drive Signal Cable
Hard disk drive signal cable lS identical to the floppy disk drive signal
cable. So, when changing the setting of the hard disk drive number (C or D),
it is not necessary to change the hard disk drive jumper setting.
You can change the setting of the hard disk drive number by modifying the
connections of the hard disk drive signal cable.
Remark
Concerning hard disk drive's terminator, they are not identical to the floppy
disk drive. When you install the second hard disk drive, you must remove one
terminator from drive number D.
HOST
DRIVE C
+5V
t ~ 220 ohm
L..c---e-
TERMINATOR SW 330 ohm
ON 7,7
+5V
t>o
1'20~
TE"'INATOR~ 330 ~
OFF
DRIVE D
I
FIGURE 2-4-18.
HARD DI8K DRIVE SIGNAL CABLE
2-76

REV .A
PRINCIPLES OF OPERATION
2.5 KEYBOARD
The keyboard unit has two operation modes. One 1S AT mode, the other 1S XT
mode.
In the AT mode, there are three kinds of key code output mode.
Mode selection is performed by software.
Key code output mode (a)
AT mode ~ Key code output mode (b)
Keyboard unit<
Key code output mode (c)
XT mode
The EQUITY 111+ / EPSON pe AX system uses the key code output mode of the AT
mode.
2.5.1 Block Diagram
The following diagrarn shows keyboard unit block diagram.
<
<
:> CLOCK
:> DATA
-,
DRIVER LED
CPU
,
KEY MATRIX
/
....
MULTIPLEXIER
FIGURE 2-5-1.
KEYBOARD UNlT BlOCK DIAGKAM
2-77

PRINCIPLES OF OPERATION
REV.A
2.5.2. Interface Signal
2.5.2.1 AT mode
The Keyboard data (sent from keyboard) or the keyboard control data (sent from
Host side) are communicatedby using the clock pin and the data signa].
There are two modes in the keyboard interface circuit. One is interface
control mode, the other is data communication mode.
In the interface cont rol mode, the host controls operation mode of the
keyboard to the host or from the host to the keyboard. At this mode, the
keyboard sends clock signal to synchronize between the keyboard operation 2nd
the host side operation.
TABLE 2-5-1.
INTERFACE CORTROL MODE
CLOCK DATA FURcnON
II
L
L
H
H
H
L
L
Keyboard can send Data to Host side
Keyboard can't send Data to Host side
Keyboard prepares receiving Data
Keyboard starts inputting Data
KEYBOARD
CLOCK ...-
DATA
.....
.....
HaST SIDE
CLOCK
DATA
TABLE 2-5-2. DATA COMMUNICAnON MODE (AT MODE)
CLOCK
DATA
Keyboard sends clock signal to synchronize between
keyboard operation and Host side operation.
(1) Keyboard sends Data.
(2) Host sends Data.
KEYBOARD
HaST SIDE
CLOCK
CLOCK
J ,
DATA .... .. DATA
..
2-78

REV.A
PRINCIPLES OF OPERATION
2.5.2.2 XT mode
TABLE 2-5-3. DATA COMKUNICATION MODE (XT MODE)
XT
DATA
Keyboard initializing signal (low active)
Clock signal
Keyboard Data wait signal (low active)
Data signal from keyboard.
2.5.3 Description of Interface Signals (AT mode)
2.5.3.1 Clock
* Synchronous clock for transmitting and receiving keyboard data.
* The clock is generated from the keyboard.
* The transmission of data cannot take place even if the keyboard is ready
to transmit when there is a low level signal (data wait) in the clock
line. (data will be saved in the keyboard buffer)
The keyboard checks the clock line during transmission of data and will
stop transmission when it detects there is a 10w level signal.
2.5.3.2 Data
* Keyboard transmission (keyboard scan code, command code), reception code
(command code) data.
* This is also the transmission request signal from the host.
level signal is detected in the data line, the keyboard is
reception.
Once a 10w
ready for
2.5.3.3 Keyboard Data Output (AT mode)
When the keyboard is ready to transmit data, it checks the c10ck and data
lines for data wait or transmission request. If there are high level signals
in both the clock and data lines, the keyboard determines that transmission is
possib1e and starts transmitting. It checks the c10ck 1ine during
transmission and stops data transmission as soon as it detects a low level
signal.
2-79

PRINCIPLES OF OPERATION
REV.A
2.5.3.4 Keyboard Data Input (AT mode)
When the keyboard detects a low level signal 1n the data line it becomes ready
to receive.
Then the signal in the host clock line drops to a low level below 60 us, which
will stop keyboard transmission.
When the keyboard detects a high level in the clock line, data reception is
performed (counts off each group of 11 bits). After receiving the 10th bit,
the keyboard changes the signal in the data line to low level and receives one
more bit (the stop bit). The low level signal of the 11th bit teIls the host
that the data has been received.
2.5.3.5 Data Transmission Method and Data Format
TADLE 2-5-4.
DATA TRANSMISSION ME'l1IOD AND DATA FORMAT
(1) Transmission method Synchronous serial Synchronous serial
transmission transmission
(2) Transmission rate 9600 BPS '=. 9600 BPS
( 3) Start bit 1 1
( 4) Stop bit 1 1
(5) Data length 8 bit 8 bit
( 6) Parity Odd parity None
CLOCK
OATAI
START
I 00 01 0 Op STOP
~~
Tl 104 us +20%
T2 20 us Min
T3 20 us Min
T4 35 us +20%
FIGURE 2-5-2. KEYBOARD DATA OU'IPUT - AT MODE
2-80

REV .A
PRINCIPLES OF OPERATION
T6
~ ~
CLOCK
c T5 ~
1 OATA ----,...... .&..-__.....
L START 00 01
T5 60 us Min ( Host data output ready time)
T6 5 us Min
FIGURE 2-5-3. KEYßOARD DATA IWUT - AT MODE
CLOCK
T2
...
T4
~
DATA
f....] START 1__D_0 0_l_......._0_2_
Tl
T2
T3
T4
100 - 250 us
104 us +20%
10 us Min
10 us Min
(Oata output possibility
check time)
FIGURE 2-5-4. KEYBOARD DATA OU'JPUT - XT MODE
2-81

PRINCIPLES OF OPERATION
HEV.A
2.5.4 Interface Circuit Specification
sv
2.2K
-----< t-------4..------+-----DATA(CLOCK)
74LS125
equ;valent
~S6P
FIGURH 2-5-5.
IRTERFACE CIRCUIT
2.5.5 Connector P in Explanation
DIN connector
FIGURH 2-5-6. KEYBORAD CORRKCTOR PIK LOCATIOKS
TABLE 2-5-5.
PIK NOMBER.
1
2
3
4
5
KEYBOARD CONNECTOR P IN FUNCTION
SIGNAL NAME
Clock
Data
N.C.
Ground
+5V DC
Ground
2-82

REV .A
PRINCIPLES OF OPERATION
2.5.6 Function Specifications
2.5.6.1 Strake Characteristics
At N key rollover (with diode)
ON
OFF
Keyl--r----------,----------
Key2-------....
Key3-----------...
Data---48}o---e---G--< 30ffX20ff)--
FIGURE 2-5-7.
STROKE CHARACTERISTlCS
2.5.6.2 Typematic Function
A key scan code i8 transmitted as long as a key is depressed. (Transmission
intervals for all keys except the F16 (P ause) key depend on the typematic
rate/delay (command assignment). When any of the other keys are pressed, it
enters a new typematic cycle.
Keyl---
Key2--------------
Data --0(
<
Tl > < T2 '> <
Tl
FIGURE 2-5-8.
TYPEMATlC FUHCTlON
2-83

PRINCIPLES OF OPERATION
REV.A
TABLE 2-5-6.
AT MODE
TRANSMISSION INTERVALS
XT MODE
Tl
TZ
250 - 1000 ms (default)
1/2 - 1/3 sec (default)
500 ms
92 ms
The typematic function will be disabled when a clock line is low level.
2.5.6.3 Keyboard Buffer
When a key is pressed (released) before the code of a key pressed earlier has
been transmitted during tbe key data out phase t
the code of the no
transmitted key is saved in this buffer until it is transmitted.
The buffer can save codes for 16 keys (16 make or break data).
The 17th code will be substituted by an overrun code.
However t no substitution will take place if there ts an overrun code in the
buffer.
Break codes and make codes when a key is depressed will not be lost even
during an overrun.
Hmlever t they will be cancelled by a buffer clear command.
The overrun code is different between mode and mode below.
TABLE 2-5-7.
KEY CODE OU1PUT MODE
AT mode
XT mode
OVERRUN CODES
(a) (b) (c)
FF 00 00
FF
2.5.6.4 Power On Reset (AT mode)
When the power is tUl~ed
on the keyboard logie performs a power on reset.
(1) Following the power on reset t a self-test program is performed.
ROM check sum
. RAH check
self-test program
self-test program
(2) After the test t the keyboard turns off the mode indicator display (3
LED's) and transmits the end code of the self-test program.
"AAR"
"FeH"
operated correctly
operated abnormally (scanning is stopped after
transmission of the end code.)
(3) When the operation normal end code (.AAH) has been transrnitted and
the keyboard detects a low level signal longer than 10 us in the
data line 5 us after from following edge of the stop bit t the
keyboard enters the XT mode.
2-84

REV.A
PRINCIPLES OF OPERATION
(4)
In AT mode, the typematic rate/delay time and key code output mode
will be set according to mode (b).
Rate
Delay
10 .9 CP S (92 ms)
500 ms
Default
Default
2.5.6.5. Initializing (XT mode)
The clock Une is checked in 10 ms cyc1es by keyboard and initializing is
performed as soon as a low level signal is detected.
(1) Key scan memory clear
(2) Buffer (FIFO) clear
(3) Self-test program performed
. ROM sum check
. RAM check
self-test program
self-test program
(4) Transmission of self-test program end code
" A.AlI"
"FeH"
Operated correctly
Operated abnormally (scanning is stopped after
transmission of the end code.)
2.5.6.6 Data Wait Function (XT mode)
When the start bit is set, the data line is checked by the keyboard and if a
low level signal (longer than 250 us) is detected in the data 1ine, data
transmission will not take place.
2-85

PRINCIPLES OF OPERATION
REV.A
2.5.6.7 Mode Indicator (3 LEnis) Display (XT mode)
Basic Operation
(1) By pressing the Scroll Lock, Numeric Lock and Gaps Lock keys each
indicator are displayed alternatively (performed after the end of
key code transmission).
(2) All displays are turned off during power on reset and initializing.
(3) The alternative operation does not take place when the control
(Gtrl) key is pressed.
Lock Key
(Data Out)
ONI
Typematic Out
:·°1 ~
I
I
I
I
I
I
. ." .....
I I
Ctrl Key ------------
Indication.J ON ~-----O-N------I ...__
FIGURE 2-5-9. BASIC OPERATION OF MODE IlIDICA'l'OR DISPLAY
Special Operations (For Germany and French)
By pressing the Gaps key, Gaps Lock indicator becomes on (light). By pressing
the shift key, Gaps Lock indicator becomes off (Not light).
Caps Key
Shift Key
Ctrl Key
Typematic Out
· .
,.... ]
· .
: :
.... ..-- ---
-------_I
Caps indication ~
ON ON L
L
FIGURE 2-5-10'. SPECIAL FURCTIONS OF MODE
IlIDICA'l'OR DISPLAY
2-86

HEV.A
PRINCIPLES OF OPERATION
2.5.7
2.5.7.1
Key Scan Code
key Code Output (AT Mode)
In AT mode,
there are three output modes
(a),(b) and (c)
Key code output in mode (a) and (b)
(1) Key code make up
The table below shows the codes allocatted to each key.
TABLE 2-5-8.
KEY CODE KAKE lJP
TITLE KEY POSITION MAKE CODE (*1)
MODE (h) MODE (a)
BREAK CODE (*2)
MODE (h) MODE (a)
General Other x x
Keys A09,B20,AI2 EO + x EO + x
Extension A,D,EI4 - E16 EO + x EO + x
Key -1 BI5
Extension E18 EO + x EO + x
Key -2
Extension Fl4 EO + x EO + x
Key -3
Shift BOO ,Bll x x
Key
Make code
is
substituted
by "FO + x"
"80" is added
to make code
"x" (OR)
Special FI6(Pause) 8 bytes 6 bytes
Key
No key code output
M>TE (*1)
(*2)
Note 1
Note 2
Make code (When key is depressed)
Break code (When key is released)
The "x" code indicates scan code data. (Refer to Table 2­
5-22)
The F14 and 16 keys can generate other codes if used in
combination with other keys. (Refer to section 2.5.7.1)
2-87

PRINCIPLES OF OPERATION
REV.A
(2) Shift function
a) Numeric lock
The table below shows the conditions for setting and releasing
the numeric lock.
TABLE 2-5-9. CONDITION FOR SETTING AND
RELEASING NUMERIC LOCK
Setting When the E17 (Num lock) is pressed and the make code
has been transmitted or when the NUM Lock LED been
lit by a host command while the numeric lock is in
released status .
. Released When the E17 key (Num lock) is pressed and the make
code has been transmitted or when the Num Lock LED
has been turned off by a host command while the
numeric lock is in set status.
Note 1 When the AOO or the A12 key (Ctrl) are pressed, it is not
possible to perform setting or releasing with the Numlock
key. (Setting and releasing cannot be performed even if
the Ctrl key is released first.)
b) Extension Left and Right shift key code transmission
i) The table below shows the key stroke conditions for
transmission of extension left and right shift codes.
TABLE 2-5-10.
KEY STROKE CONDITION
N-LOCK
NOT N.LOCK
N.LOCK
EXTENSION SHIFT SETTING
Extension shift off code is
transmitted when extension key-l
(or extension key-2) is pressed
after the shift key has been
pressed.
In case of pressing extension
key-2, same operation is
performed even though N.LOCK
mode.
Extension Left shift on code is
transmitted when extension key-l
(or extension key-3) is pressed
after the shift key has been
pressed.
In case of pressing extension
key-3, same operation is
performed even though NOT
N.LOCK mode.
EXTENSION SHIFT RELEASE
(1) Extension shift on code
is transmited when extension
key-l (or extension key-2)
is released.
(2) Extension shift on code
is transmitted when other
keys are pressed.
(1) Extension Left shift
off code is transmitted
when extension key-l (or
extension key-3) is released
(2) Extension Left shift
off code is transmitted
when other keys are
pressed.
2-88

REV.A
PRINCIPLES OF OPERATION
ii) Extension left and right shift codes are as folIows.
TABLE 2-5-11. EXTENSION LEFT ABO RIGBT SBIFT CODES
TYPE MODE (b) MODE (a)
Extension Left EO + 12 EO + 2A
Shift on code
Extension Left Eü + FO + 12 EO + AA
Shift off code
Extension Right EO + 59 EO + 36
Shift on code
Extension Right Eü + Fü + 59 Eü + B6
Shift off code
iii) Transmission sequence of left and right codes are as
folIows.
TABLE 2-5-12. TRANSMISSION SEQUENCE OF LEFT ABO RIGBT CODES KEY
CONDITION
Extension Shift Setting
TRANSMISSION SEQUENCE
EXS ----) x
Extension
Shift
Release
Hhen extension
Shift setting
key is OFF
When other keys
are ON
x
----) EXS
EXS ----) x
Note
"x"
"EXS" :
Key data
Extension Left and right shift codes
2-89

PRINCIPLES OF OPERATION
HEV.A
(3) Special operations generated by a combination of keys
a) The codes shown in the table below are transmitted when the F16
(Break) key is pressed while either the Aaa (left Ctrl) or the
A12 (right Ctrl) key is also pressed.
TABLE 2-5-13. TRANSMITTED CODE OF F16(BREAK) KEY
MODE
MODE
(b)
(a)
EO + 7E + EO + FO + 7E
EO + 46 + EO + C6
Note
No code below are transmitted when the F14 (Sys Rq) key is
pressed ~lhile the [A01 (left Alt) ~ the A09 (right Alt)]
and the [AOa (left Ctrl)~ A12 (right Ctrl)] key or the BOO
(Left shift) and BII (right shift) keys.
(4) Key code output during typernatic operation
All keys except the F16 (pause) key are typematic keys whose make
codes are transmitted at specified intervals.
TABLE 2-5-14. TRANSMITTED CODE OF F14(Sys Rq) KEY
MODE
WIIEN AOO, A12 KEY OR
WIIEN A01, A09 KEYS ARE
BOO, Bll KEYS ARE DEPRKSSED DEPRKSSES
HAKE BREAK HAKE BREAK
(b) EO + 7C EO + FO + 7C 84 FO + 84
(a) EO + 37 EO + B7 54 D4
2-90

REV.A
PRINCIPLES OF OPERATION
Key Code Output in Mode (c)
(1) Transmission of make codes (when keys are pressed)
A one byte make code is transmitted when a key is pressed (refer to
scan code table).
(2) Transmission of break codes (when keys are released)
The AOO (left Ctrl), the AOI (left Alt), the BOO (1eft shift), the
Bll (right shift) and the COO (Caps) keys transmit break codes when
a key is released. The break code is "FO + make code".
(3) Key code output during typematic operation
The A04, A14-A16, BOI-BIO, BIS, COl-C12, DOO-D14, EOO-E13, D20,E13',
C12', Bll', BOO' and D20' keys are typematic keys whose make codes
are transmitted at specified intervals when pressed repeatedly.
(4) The break code transmission keys in (2) and the typematic keys in
(3) above are set during default and all keys can be set with the
commands described below.
2.5.7.2 Key Code Output (XT Mode)
The Key code outputs are performed according to the same conditions that
prevail in key code mode (a) during AT mode (inc1uding shift function).
2.5.8 COMMANDS (AT mode)
2.5.8.1 Commands From the Rost Side
These are commands received by the keyboard which it responds to within 20 ms.
TABLE 2-5-15. KEYBOARD COMMANDS (AT MODE)
COMMAND DATA (HEX) BUFFER CLR LID SET
RESET FF 0
RESEND
FE
TYPEMATIC KEY RESET 1,2 FC,FD 0
TYPEMATIC KEY SET FB 0
ALL KEY TYPEMATIC CONTROL FA-F7 0
SET DEFAULT F6 0
DEFAULT DISABLE FS 0
ENABLE F4 0
SET TYPEMATIC RATE/DELAY F3
READ KEYBOARD ID F2
SET/READ KEY CODE MODE FO 0
ECHO
EE
SET/RESET MODE INDICATORS ED 0
2-91

PRINCIPLES OF OPERATION
REV.A
(1) Reset
The keyboard reeognizes this eornmand with the aeknowledge (ACK)
eommand. When reeeption of the ACK command has been eon f i rmed
(eonfirmation is mode when both the eloek and data line signals
exeeed 500 us high) a reeset operation indentieal with the pmler on
reset is performed. (Exeept for XT mode switching operation)
(2) Resend
The keyboard repeats the transmission of end data transmitted when
reeives aresend eommand.
(3) Set default
The keyboard responds with an ACK eommand and eontinues seanning
after the output buffer has been cleared and the default condition
has been set.
(4) Default disable
The keyboaed stops seanning and exeept that it waits for a eommand
it behaves as during a set default command.
(5) Enable
The keyboard aeknowledges to the host side with and ACK
clears the output buffer. Then starts seanning.
eommand and
(6) Set typematic Rate/Delay
This command is made up of a 2-byte command and parameter.
The keyboard responds to the ACK command, stops scanning and waits
for the parameter. Then the keyboard responds to the parameter with
an ACK command, sets the rate and delay shown in the figure below
and starts scanning (when proceeded as an Enable). If a cornmand is
received instead of a parameter, the eurrent rate remains unchanged
and keyboard stops this command operation, then the new eommand is
performed and scanning starts.
MSB
TABLE 2-5-16.
TYPEKATIC RATE/DKLAY
LSB
RATE
DELAY
2-92

REV.A
PRINCIPLES OF OPERATION
1) DELAY
BIT
DELAY
6 5 (ms)
0 0 250
0 1 500
1 0 750
1 1 1000
2) RATE
BIT RATE BIT RATE
4 3 2 1 0 (cps) 4 3 2 1 0 (cps)
0 0 0 0 0 30.0 1 0 0 0 0 7.5
0 0 0 0 1 26.7 1 0 0 0 1 6.7
0 0 0 1 0 24.0 1 0 0 1 0 6.0
0 0 0 1 1 21.8 1 0 0 1 1 5.5
0 0 1 0 0 20.0 1 0 1 C 0 5.0
0 0 1 0 1 18.5 1 0 1 0 1 4.6
0 0 1 1 0 17.1 1 0 1 1 0 4.3
0 0 1 1 1 16.0 1 0 1 1 1 4.0
0 1 0 0 0 15.0 1 1 0 0 0 3.7
0 1 0 0 1 13.3 1 1 0 0 1 3.3
0 1 0 1 0 12.0 1 1 0 1 0 3.0
0 1 0 1 1 10.9 1 1 0 1 1 2.7
0 1 1 0 0 10.0 1 1 1 0 0 2.5
0 1 1 0 1 9.2 1 1 1 0 1 2.3
0 1 1 1 0 8.6 1 1 1 1 0 2.1
0 1 1 1 1 8.0 1 1 1 1 1 2.0
2-93

PRINCIPLES OF OPERATION
HEV.A
(7) Echo
The keyboard transmits a code "EE" response and continues scanning
(when preceeded as an Enable).
(8) Set/Reset mode indicators
This command is made up of a 2-byte cornmand and an option. The
keyboard responds to the host side with and ACK command and waits
for sending of the option. Then keyboard responds to the option,
sets the indicator and starts scanning (when proceeded as an
Enable). If it receives another command instead of the option, the
indicator condition remains unchanged and the keyboard stops, this
command operation. Then proceeds the new command and starts
scanning.
TABLE 2-5-17.
OPTION REGISTER FüR KEYBOARD
MSB
LSB
SCROLL LOCK
INDICATOR
NUMERIC LOCK
INDICATOR
CAPS LOCK
INDICATOR
(9) Read Keyboard ID
The keyboard responds with the ACK cornmand, transmits a 2-byte data
; "AB" + "83"
2-94

REV .A
PRINCIPLES OF OPERATION
(10) Set/Read key code mode
This command is made up of a 2-byte command an option. The keyboard
responds to the host side with an ACK command stops scanning and
waits for the option. When keyboard inputs option, it responds to
the host side with an ACK command, starts scanning after setting key
code mode or transmission status. (When proceeded as an Enable.)
If it receives another command instead of the option, processing of
this command is cancelled, the new command is proceeded and scanning
starts.
i) Read key code mode starts (option data "00")
The keyboard transmits the current keycode mode status. (1
byte)
K.EY
CODE MODE
(a)
(b)
(c)
TABLE 2-5-18. K.EY
CODE MODE STATUS
TRANSMITTING DATA
01
02
03
ii) Set key code mode (option data : "01"-"03")
The keyboard is set to specified key code mode depending on
the option data.
TABLE 2-5-19. K.EY CODE MODE ON OPTION DATA
OP TION DATA K.EY CODE MODE
01 (a)
02 (b)
03 (c)
(11) Typematic key set
This command is made up of a eommand and an option (Max 4 or 5
bytes). The keyboard responds to this command with an ACK command,
stops scanning and responds to the option with an ACK command. In
the key code mode (c), this command sets the typematic function and
cancels break code transmission for keys waiting for the key scan
codes that correspond to the option data. When the command has been
proceeded, scanning stops and remains in that condition.
(12) Typematic key reset 1 ("FC")
This command releases the typematic function and sets transmission
of the break code for keys waiting for key scan codes corresponding
to option data. Other details are the same as described in the ease
of typematic key set above.
2-95

PRINCIPLES OF OPERATION
REV.A
(13) Typematic key reset 2 ("FD")
This command releases the typematic function and cancels
transmission of the break code for keys waiting for key scan codes
corresponding to the option data. Other details are the same as
described in the case of Typematic key set above.
(14) All key typematic control
The keyboard responds to this command with an ACK command cancels 01'
sets the typematic function and break code transmission and
continues scanning (when proceeded as an Enable.)
TABLE 2-5-20.
ALL KEY TYPEMATIC CONTROL
COMMAND DATA
TYPEMATIC FURCTION
BREAK CODE TRANSMISSION
REMARKS
FA
F9
F8
F7
Setting
Cancel
Cancel
Setting
Setting
Cancel
Setting
Cancel
Applied for
only key
code mode
(c) •
2.5.8.2 Commands To Host Side
These are commands transmitted to the host side by the keyboard.
TABLE 2-5-21. COMMANDS
COMMAND
Resend
ACK
Overrun
Break Code Prefix
BAT Completion
Echo Response
Read Keyboard ID
Read Key Code Hode
1'0 'l'HE BOST SIDE
DATA (HEX)
FE
FA
** FO
AA
EE
AB + 83
Hode (a) + 01
Hode (b) + 02
Hode (c) + 03
** Key Code Hode (a) •...•• FF
Key Code Hode (b),(c) .. 00
(1) Resend
The keyboard generates aresend command when it receives an invalid
input 01' invalid parity input.
(2) ACK
The keyboard outputs an ACK response for valid inputs that do not
generate echo 01' resend commands. If an interrupt is issued to the
keyboard when an ACK command is being transmitted, transmission i8
terminated and the ne~l command is responded to.
2-96

REV.A
PRINCIPLES OF OPERATION
(3) Break code prefix
This cornmand announces that a key has been released and sends the
first byte of a 2-byte message. (Corresponds to key code mode (b)
and (c).)
(4) Overrun
The overrun character is in the 17th position of the keyboard buffer
and when the buffer becomes full, the character is stacked on the
last code. When this code comes first in the buffer it is output as
an overrun error.
(5) Bat completion code
When BAT is completed normally, the keyboard outputs an "M"
response. "FC" or other code indicates that the keyboard
microprocessor is malfunctioning.
(6) Echo response
This command is transmitted in response to an echo command from the
host side.
(7) Read keyboard ID
This command is transmitted in response to an equipment ID data read
cornmand from the host side.
(8) Read key code mode
This command transmits current keycode mode status in response to a
key code mode read cornmand from the host side.
TABLE 2-5-22.
KEY SCAN CODE LIST
KEYNO. MODE(a) MODE(b) MODE(c) KEY NO. MODE(a) MODE(b) MODE(c)
FOO 01 76 08 EI3(*2) 7D 6A 5D
F02 3B 05 07 E14 EO,52 EO,70 67
F03 34 06 OF E15 EO,47 EO,6C 6E
F04 3D 04 17 E16 EO,49 EO,7D 6F
F05 3E OC IF E17 45 77 76
F06 3F 03 27 E18 EO,35 EO,4A 77
F07 40 OB 2F E19 37 7C 7E
F08 41 83 37 E20 4A 7B 84
F09 42 OA 3F DOO OF OD OD
FI0 43 01 47 DOl 10 15 15
F11 44 09 4F D02 11 ID ID
F12 57 78 56 D03 12 24 24
F13 58 07 5E D04 13 2D 2D
F14 EO,37 EO,7C 57 D05 14 2C 2C
F15 46 7E 5F D06 15 35 35
F16 ** ** 62 D07 16 3C 3C
EOO 29 OE OE D08 17 43 43
EOI 02 16 16 D09 18 44 44
E02 03 lE lE DI0 19 4D 4D
E03 04 26 26 DU lA 54 54
E04 05 25 25 D12 IB 5R 5B
2-97

PRINCIPLES OF OPERATION
REV.A
E05 06 2E 2E Dl3(*3) 2B 5D 5C
E06 07 36 36 D14 EO,53 EO,71 64
E07 08 3D 3D DIS EO,4F EO,69 65
E08 09 3E 3E D16 EO,51 EO,7A 6D
E09 OA 46 46 D17 47 6C 6C
EIO OB 45 45 D18 48 75 75
Ell OC 4E 4E D19 49 7D 7D
E12 OD 55 55 D20 4E 79 7C
El3 OE 66 66 D20' 7E 6D 7B
COO 3A 58 14 B06 31 31 31
C01 1E 1C 1C B07 32 3A 3A
C02 IF 1B 1B B08 33 41 41
C03 20 23 23 B09 34 49 49
C04 21 2B 2B B10 35 4A 4A
C05 22 34 34 Bll 36 59 59
C06 23 33 33 Bll'(*2) 73 51 51
C07 24 3B 3B B15 EO,48 EO,75 63
C08 25 42 42 B17 4F 69 69
C09 26 4B 4B B18 50 72 72
C10 27 4C 4C B19 51 7A 7A
Cll 28 52 52 B20 EO,lC EO,5A 79
C12 IC 5A 5A B20' (*2) 78 63 78
C12' (*1) 2B 5D 53 AOO 1D 14 II
C17 4B 6B 6B A01 38 II 19
C18 4C 73 73 A05 39 29 29
C19 4D 74 74 A09 EO,38 EO,ll 39
BOO 2A 12 12 A12 BO ,1D EO ,14 58
BOO' (*1) 56 61 13 A14 EO,4B EO,6B 61
BOl 2C 1A 1A A15 EO,50 EO.72 60
B02 2D 22 22 A16 EO,4D EO,74 6A
B03 2E 21 21 A17 52 70 70
B04 2F 2A 2A A17' (*2) 7e 68 68
B05 30 32 32 A19 53 71 71
** F16key code mode (a) ; E1,lD,45,E1,9D,C5
mode (b) ; E1,14,77,E1,FO,14,FO,77
For U.S.1\.
For Europe
(*1) keys and (*2) keys are not installIed.
(*2) keys and (*3) key are not installed.
2-98

CHAPTER
3
OPTIONS
TAßlE OF CONTENTS
Section
Title
Page

CHAPTER
4
TROUBLESHOOTING
TABLE OF CONTENTS
Section
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.4
Title
SERVICE TOOLS ............................................
TROUBLESHOOTING 4-2
How to use the POD (Power On Diagnostics) 4-2
How to use the MFG Board 4-2
RESPONSE AND INFOR~1ATION FOR ERRORS 4-5
Outl ine e.. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 4-5
POD Funct ion s 4-5
Explanation of POD Functions 4-5
Specific Pattern in 34H to 3DH 4-6
Response and Information of Errors 4-6
Page
4-1
LIST OF FIGURES
Fi gu re Title Page
4-1-1 Connection of Service Tools 4-1
LIST OF TABLES
Table
4-1-1
4-3-1
Title
Service Tool Listing 4-1
Responses and Information for Errors 4-7
Page

REV.A
TROUBLESHOOTIBG
4.1 Service Tools
Recornmended service tools are listed in Table 4-1-1 with corresponding EP SON
part numbers; these are also cornmercially available.
BOARD ATRPS UNIT
FIGURE 4-1-1. CONNECTION OF SERVICE TOOLS
TAßLE 4-1-1.
SERVICE TOOL LISTING
TOOLS NO. P ART NO. DESCRIP TrON
ANT-MAC BOARD B778601601 Expansion board for the main control board.
MFG BOARD B77860170I Bus status check board.
CABLE IIE207 B77860I80I Expansion for CN3 of the ATRPS unit •
CABLE IIE208 B77860200I Expansion for CN4 of the ATRPS unit.
CABLE IIE2I0 B77860200I Expansion for DCI of the ATRPS unit.
CABLE IIE2II B778602I0I Expansion for DC2 of the ATRPS unit.
CABLE IIE2I2 B778602201 Expansion for CN3 of the ANTA board.
4-1

TROUBLESBOOTIBG
REV.A
4.2 TROUBLESHOOTING
The BIOS ROMs in the EQUITY 111+ / EPSON PC AX computer system are including a
diagnostic program which will perform the check for internal computer system
automatically.
We call the test program "POD" (Power On Diagnostics).
The POD will output ERROR MESSAGE to the CRT screen or eight LEDs on the MFG
Board if error is occurred in the EQUITY 111+ / EPSON PC AX computer system.
The error message will be useful at repair because we can determine the
probable cause by using this error message.
4.2.1 How to Use the pon (Power on diagnostics)
1. Connect a monitor and a MFG Board to the EQUITY 111+ / EPSON PC AX computer
system.
2. Turn the power switch of the EQUITY 111+ / EPSON PC AX. The POD will start
automatically and check internal circuits step by step automatically.
3. When error is occurred, the error message will appair on the monitor screen
or LEDs of the MFG board.
(The POD does not show good message when no error)
4. Search the 'RESPONSE AND INFORMATION FOR ERRORS' and find the corresponding
probable cause yourself.
4.2.2 How to Use the MFG Board
1. Function of the MFG board.
The MFG board is a service tool which can display data status (data bus
bit 0 to bit 7) on the eight LEDs.
This board can display data status of 1/0 address OOO(H) to FFF(H).
We can select the 1/0 address by using DIP switch.
2. How to set the DIP switch
Each switches of the DIP switch are corresponding to address bus AO to
All as follows.
DIP
SWITCH 8 7 6
SW2
5 4 3 2 1 4
SW1
3 2 1
CORRESPONDING
ADDRESS All A10 A9 A8 A7 A6 A5 A4 A3 A2 Al AO
* When setting the DIP switch, please use following instance.
4-2

RKV.A
TROUBLESHOOTING
INSTANCE 1
In case of setting the DIP switch to 1/0 address 80H.
DIP
SWITCH 8 7
SW2
6 5 4 3 2 1 4
SWl
3 2 1
CORRESPONDING
ADDRESS
SETTING OF
THE DIP SW
All A10 A9 A8 A7 A6 A5 A4
ON ON ON ON OFF ON ON ON
A3 A2 Al AO
ON ON ON ON
VALUE OF
ADDRESS BUS o 000
( 0)
1 0 0 0
(8)
o 0 0 0
(0) =080H
INSTANCE 2 In case of setting the DIP switch to 1/0 address l77H.
DIP
SWITCH 8 7
SW2
6 5 4 3 2 1 4
SWl
3 2 1
CORRESPONDING
ADDRESS All A10 A9 A8 A7 A6 A5 A4 A3 A2 Al AO
SETTING OF
THE DIP SW ON ON ON OFF ON OFF OFF OFF ON OFF OFF OFF
VALUE OF
ADDRESS BUS 000
(1)
1 o 1 1
(7)
1 o 1 1
(7)
1
=l77H
4-3

TROUBLESBOOn}l;
REV.A
3. How to use the MFG board
Instail the MFG board to an option slot connector of the computer
system.
4. Meaning of the LEDs
* When the LED Iight t corresponding data bus is high status.
MFG
BOARD
LED NO. MEANING
LED 1 DATA BUS BIT 7
LED 2 DATA BUS BIT 6
LED 3 DATA BUS BIT 5
LED 4 DATA BUS BIT 4
LED 5 DATA BUS BIT 3
LED 6 DATA BUS BIT 2
LED 7 DATA BUS BIT 1
LED 8 DATA BUS BIT 0
4-4

REV.A
TROUBLESHOOTIBG
4.3 RESPONSE AND INFORMATION FOR ERRORS
4.3.1 Outline
The power on diagnostics (called POD) of EQUITY 111+ / EPSON PC AX ROM BIOS
diagnoses the system status held when EQUITY 111+ / EPSON PC AX is initiated
and takes action according to the status.
4.3.2 POD Functions
POD
has the following four functions:
1; POD halts the system to disable initiation if POD detects a serious error
while checking system hardware.
2; If POD detects an error that is not fatal to the system, POD displays the
error message on the CRT screen and 1/0 address 80H. Then makes the system
wait for initiation until a specific key is pressed.
3; If a serious error occurs (refer to function 1), POD displays an error
message on the CRT screen in addition to 1/0 address 80H.
4; In reference to a non fatal error (function 2), POD skips the specific key
input wait status.
4.3.3 Explanation of the POD Functions
1; Checking system hardware (serious error)
See the table 4-2. (Responses and information for errors)
2; Checking system hardware (not fatal)
See the table 4-2. (Responses and information for errors)
The specific key is the F1 key.
3; Displaying an error message on the CRT screen and 1/0 address 80H.
See the table 4-2.
(Responses and information for errors)
4; Skipping specific key input wait status
The key input wait request for an error specified in CMOS RAM 3EH and 3FH is
skipped if a specific pattern is defined in CMOS RAM 34H to 3DH.
4-5

TROUBLESBOOTING
HEV.A
4.3.4 Specific Pattern in 34H to 3DH
Pattern
Specification in 3EH and 3FH
Each bit has the meaning listed below. Input-wait operation is skipped if a
bit is O. Input-wait operation is allowed if a bit is 1.
- Meaning of each bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
RAM check error
CPU VIRTUAL test error (not occur in BIOS ROM Ver.1.02)
RTC error (corresponds to an error other than '163-time and date not
set')
RTC time error (corresponds to '163-time and date not set')
CRT DIP switch setting error or controller error
Keyboard error
FDD error
HDD error
- CMOS 3FH
Bit 0: X287 setting error (corresponds to '162-time system options not set')
Bit 1 : Key locked status
Others : Reserved (set to 1)
4.3.4 Response and Information of Errors
The table shows response and information related to errors detected by POD.
An unfixed value is stored at 1/0 address 80H if continue is indicated for
operation.
4-6

t
PORT
80
01H
04H
05H
06H
07H
or
08H
PROBABLE
CAUSE
CPU
BIOS ROM
GAATIO
146818
(RTC)
8254
(Timer
counter)
TABLE 4-3-1. RESPONSE MilD INFORMATION FOR ERRORS
SOLUTION
EXPLANATION
Remove then reinsert
or replace
CPU
Remove then reinsert
or replace
BIOS ROM
Replace GAATIO
Replace RTC
Replace 8254
* CPU CHECK
The protection enable (PF) bit in
the CPU machine status
ward (MSW) was 1 instead of o.
(MSW should be 0)
* BIOS ROM CHECK
An error occurred in BIOS ROM
check sum
* DMA PAGE REGISTER CHECK
An error occurred during DMa page
register check operation.
* RTC REGISTER CHECK (Changing from
protect mode to real mode check)
An error occurred during RTC C-MOS
RAM area OFH check operation.
Checking is performed by setting
and verifying each bit
sequentially.
* RTC C-MOS RAM OF(H):
Shut down status byte
* TIMER COUNTER CHECK (Refresh
function)
An error occurred during timer
counter 1.
-For 07H
(1 is written in each bit for of
the count register and counting
is started)
An error occurred when checking
that the all upper four bits of
the down counter become zero.
ERROR MESSAGE
OUTPUT TO CRT
None
None
None
None
None
NEXT
OPERATION
HALT
HALT
HALT
HALT
HALT
~
>
I§

t
-For 08H
(0 is written in each bit of the
count register and counting is
started)
An error occurred when checking
that the upper four bits of the
down counter become 1.
----------------------------------------------------------------------------------------------------------
09H
or
OAR
OBH
or
OCH
GAATrO
8237A5
(DMAC)
Replace GAATI0
Replace 8237 A5
* REFRESH DEFECT BIT (r/o PORT)
CHECK
-For 09H
1/0 port 61H bit4 could not be
set to O.
-For OAR
r/o port 61H bit4 could not be
set to 1.
* r/o port 61H:
Refresh detect bit (Half of the
refresh signal frequency is
indicated by this bit)
* DMA REGrSTER CHECK
-For OBH
An error occurred during
checking the DMA controller 1
register.
-For OCH
An error occurred during
checking the DMA controller 2
register.
None
None
HALT
HALT
11H RAM
and
error
bit
pattern
Replace RAM * RAM (Base 64KB) CHECK
An error occurred during checking
the base 64K-byte RAM.
LED indicates the following data
repeatedly.
000000 xxxx 201 HALT
Error bit pattern
(1) 11h(1 second)
(2) Error bit pattern (1 second)
(Upper byte)
~
~
~
~
~
g
>

t
(3) Error bit pattern (1 second)
(lower byte)
* DETEMING THE FAULTY RAM LOCATION.
The RAM corresponding to the bit
of which LED is on is faulty.
(Example)
When Upper byte 00000000
Lower byte 00001000,
RAM corresponding to bit3 at
location ISA is faulty (When
ANT-RM circuit board unit number
Y12620300000 is used.)
If no error is detected during RAM
check but an error is detected
during parity check, LED indicated
error message as folIows:
(1) llR (1 second)
(2) OOR (1 second)
(3) OOR (1 second)
In this case, the error bit
pattern is not indicated.
(Note)
An error message is also
displayed on the CRT screen. The
faulty RAM is detemined as folIows:
000000 xxxx 201
Error bit pattern
;
• >
~
~
~
§
~

~
I
~
0
~ (Example)
When the error bit pattern is ADCE:
A B C D Cf)
1010 1101 1100 1110
~
RAMs corresponding to bits 1, 2, ~
3,6,7,8,10, ll, 13 and 15 are ~
faulty.
16H
8042
(8742)
Replace 8042 (8742)* KEYBOARD CONTROLLER REGISTER CHECK
The IBF bit in the 8042 (8742)
status register was not cleared
even after a fixed time elapsed.
* If the IBF bit is on, the 8042
(8742) data bus buffer contains
data. This IBF bit is automatically
cleared by the 8042 (8742)
internal probram.
None
HALT
17H
8042
(8742)
Replace8042 (8742)* KEYBOARD CONTROLLER SELF-CHECK
The normal termination code (55H)
was not returned when the keyboard
controller seIftest program was
executed.
(Note)
The keyboard controller seIftest
differs from the keyboard unit
seIftest.
None
HALT
18H
8042
(8742)
Replace 8042 (8742) * DATA TRANSMISSION CHECK BETWEEN
KEYBOARD CONOROLLER AND CPU
The IBF bit in the 8042 (8742)
status register was not cleared
even though a fixed time elapsed
after a command was sent to the
8042 (8742) data bus buffer.
* The IBF bit in the 8042 (8742)
status register is on when the
None
HALT
~.>

tt-'
t-'
22H
23H
25H
II
GAATIO
8259
Replace GAATIO
Rep lace 8259
data bus buffer contains command
or data. The IBF bit is
automatically cleared by the 8042
(8742) internal program.
* DMA PAGE REGISTOR CHECK
An error was detected while
checking the access to DMA page
register (83, 84H)
Folling two check operations are
performed:
(1) 55AAH is written as data in
above port.(83,84H) The data is
read by and the written data with
read data.
(2) 55AAH is written in avobe (83,84H)
port byte mode.
Then written data is read, and the
written data is compared with the
read data.
This error is indicated if the
written data was not equal to the
read data.
106-System
board error
* INTERRUP CONTROLLER AND INTERRUP T
MASKING CHECK
For 23H:
An error was detected in the
interrupt mask register of the
master interrupt controller.
Checking is done writing and
verifying 00 and FF in the
interrupt mask register.
For 24H:
An error was detected in the
interrupt mask register of the
slave interrupt controller.
Checking is the same as the
explained for 23H.
101-System
board error
HALT
HALT
m
5>
~
~
~
~
i

~
I
~
N
26H
or
27H
28H
8254-2
8259A-2
8254-2
8259A-2
Rep1ace 8254-2 or
8259A-2
Rep1ace 8254-2 or
8259A-2
For 25H:
An interrupt occurred even though
all bits in the interupt mask
register were on.
Checking is done in the fo110wing
order:
-FFH is set in the interrupt
mask registers of the master and
slave interrupt controllers.
-Whether an interrupt is
ckecked by software STI command.
* TlMER SPEED CHECK
An error was detected in timer
controller counter O.
For 26H:
It is set so that interrupt
occurs after 60usec from the
start of counter.
This error is indicated if an
interrupt does not occur during
the 90usec from the start of
counter.
For 27H:
It is set so that an interrupt
occurs after 200usec from the
start of counter.
This error is indicated if an
interrupt occurs during the 150
usec from the start of counter.
* TIMER COUNTER INTERRUPT CHECK
This error is indicated if a
counter 0 interrupt set by the
operation exp1ained for 27H does
not occur at 200usec or after
200usec.
102-System
board error
103-System
board error
HALT
HALT
~
~
~
~
~
&.

2AH
2BH
8254-2
RAM,
GAATIO
option
board
Replace 8254
Replace the RAM,
GAATIO, or option
board
* TIMER COUNTER 2 CHECK
55AAH is written in timer
controller counter 2, the counter
is read, and the written data is
compared with the read data.
This error is indicated if the
written data is not equal to the
read data.
* NMI CIRCUIT CHECK
This error is indicated if an NMI
occurs during the next 400us after
NMI is allowed.
During the 400usec, CPU does not
access to RAM. So, if this error
is occured NMI circuit has problem.
(Ref) NMI occurs under one of the
following conditions:
(1) A RAM parity check error occurs.
(2) An 1/0 channel error occurs.
108-System
board error
lOS-System
board error
HALT
HALT
2CH 8042
(8742)
Replace 8042 (8742) * KEYBOARD CONTOLLER STATUS
REGISTER CHECK
The IBF bit in the 8042 (8742)
status register was not cleared
even after a fixed time elapsed.
* Checking is done in the same way
as l6H.
lOS-System HALT
board error
----------------------------------------------------------------------------------------------------------
2EH, CPU Remove them reinsert
or replace The protection enable (PE) bit in
* ADDRESS LINE (A19 TO A23) CHECK
None HALT
36H,
OR
CPU
THE CPU MACHlNE STATUS WARD (MSW)
3BH
REGISTER WAS TURNED ON BUT THE BIT
WAS OFF WHEN VERIFIED.
----------------------------------------------------------------------------------------------------------
w
t
'"'"
;
• >
~
G §
~

....
I
~
~
31H
or
32H
( 38H)
Unfixed
value
GAATM1
GAATM2
REPLACE GAATM1 OR
GAATM2
* ADDRESS LINE (A19 TO A23) CHECK
An error occurred while checking
address lines 19 to 23.
*Checking address lines method.
(1) FFFFH is written in address
000000
(2) OOOOH is written in the
following addresses:
080000
100000
200000
400000
800000
(3) When the data stored in None
address 000000 is FFFFH, address
lines A19 to A23 are detemined as
normal.
If value of address 000000 is not FFFFH,
address line (A19 to A20) has problem.
RAM Replace RAM * RAM SIZE CHECK
One of the following errors was
detected during the checking of
the RAM size:
(1) Bad RAM
(2) A parity error
* An error address and error bit
pattern are displayed on the CRT
screen.
(1) If a bad RAM is detected:
An error address and an
error bit pattern are displayed
on the CRT screen as folIows:
xxxxxx **** 202-Memory address error
xxxxxx Error address
202-Momory
address error
HALT
CONTINUE
~
~ §
~
~.>

t~
I.n
(3AH)
Unfixed
value
(Address)
If an address from OOOOOOH to
07FFFFH is indicated, there is an
error in the 256K-bit RAM on the
ANT-RM circuit board.
If an address from 080000H to
09FFFFH is indicated, there is an
error in the 64K-bit RAM on the
ANT-RM circuit board.
If an address from 100000H to
FDFFFFH is indicated, there is an
error in the RAM on the option
slot.
(Pattern)
This is same as the one
explained for 11H.
Please see "Note" in the item 11H.
(2) For a parity error
Data is indicated on the CRT
screen as foliows:
xxxxxx 0000 202-Memory address error
--- Parity check 1 or 2
1: RAM parity error (Internal circuit)
2: 1/0 channel parity error
(Extension Memory card)
xxxxxx ---- Error address
0000 ---- All zeros are displayed
* ADDRESS LINE (A16 TO A23) CHECK
One of the folowing errors was
detected during checking the
address line:
(1) Address line (A16 to A23) error
(2) Parity error
203-Memory
address error
CONTINUE
~.>
~
~
~
§
~

tI-'
0'1
(3EH) Keyboard
Unfixed unit or
value 8042
(8742)
Replace the
keyboard unit or
8042 (8742)
(3FH) Keyboard Replace the
unit, Keyboard,
8042(8742),8042(8742), or
or ANTA ANTA circuit board
circuit
board
* Checking address lines
a) Check data is written in the RAM
specified at the start address of
block (64K bytes) as shown in the
above figure.
b) The written data is verified
after the data is written in all
of the blocks.
c) This error is indicated if an
error is detected during
verfication explained in b.
* An error address and read data are
displayed on the CRT screen.
* Error message explantion
(1) Address line error
xxxxxx **** 203-Memory address error
xxxxxx ---- Error address
**** ---- Read data (Not accordant data)
xxxxxx **** 203-Memory address error
-- Parity check 1 or 2
1: RAM parity error (Internal circuit)
2: 1/0 channel parity error (Extension
Memory card)
* KEYBOARD CLOCK CHECK
The TO bit (indicating the clock
sent from the keyboard) of the
test input port in 8042 (8742) was
not turned low.
304-keyboard
or System
Unit error
* KEYBOARD INTERFACE CIRCUIT CHECK 30 I-KEYBOARD
Before this check, the POD execute error
keyboard unit self-test. Next, the
POD execute keyboard interface circuit
check. When keyboard interface circuit
has no error, this error will indicate.
CONTINUE
CONTINUE
!
~
§~
!
s.>

,...
I
.....
.t:'­
(3FH)
Unfixed
value
8042
(8742)
(42H) DJP
Unfixed switch
value setting
Rep lace 8042
(8742)
Set the DIP
switch correctly.
SOt when this error message is indicated.
In this case t the code output repeatedly
is displayed on the CRT screen.
This error is also indicated if a
code is output repeatedly from the
keyboard.
* KEYBOARD INTERFACE CIRCUIT CHECK
This error is indicated if a
response to the interface line
test command output during keyboard
interface circuit check (explained in
the previous section) is not returned
or the response indicates an error.
* CRT SLIDE SWITCH SETTING CHECK
The slide for setting the monitor
did not match with the mounted
video card.
If 40l-CRT error is displayed on
the CRT screen t the monochrome
monitor was set by the switch but
the video card indicated the color
monitor.
If SOl-CRT error is displayed on
the CRT screen t the color monitor
was set by the switch but the
video card indicated the
monochrome monitor.
303-CRT error
or System unit
error
40l-CRT error
or
SOl-CRT error
CONTINUE
CONTINUE
~
>
~
~
I
~

ṭ
00
...
(42H) Lithium
Unfixed battery
value
(42H) RTC
Unfixed (146818)
value setting
error
(42H) Setting
Unfixed error
value
(42H) RTC
Unfixed (146818)
value
(43H) FDD,
Unfixed SPFG
value circuit
board,
or WHDC
circuit
board
Replace the
lithium battery
and perform
'set-up'
Replace or
correctly set RTC
(146818)
and perform 'set-up'
P reform sett ing
correctly
Replace RTC
(146818)
1) Replace FDD
2) Mount one or
both of the SPFG
and WHDC circuit
boards if it was
not mounted.
3) Replace the
SPFG or WHDC
circuit board
and perform 'setup'
* RTC POWER FAlLURE CHECK
RTC power failure was detected.
This error is indicated if the VRT
bit in RTC (146818) control
register D is O.
* RTC SETTING CHECK AND RTC CHECK-SUM
An error occurred in RTC check sum
or the RTC contents did not match
with the mounted hardware.
* RAM SIZE CHECK
This error is indicated if the
value in the mounted RAM differs
from RTC setting.
* TIME AND DATE CHECK
This error is indicated if the RTC
control register was read but
processing did not enter update in
progress status, or updqte in
progress status could not be
cleared.
* FDD CHECK
(1) An error was returned when FDC
was reset (INT 13H reset
function).
(2) FDD was normally reset (as a
result of the above checking) but
an error was returned during head
seek test (only drive A was
checked).
(3) A card equivalent to IBM COMBO
card did not install(the error
occurs if SPFG or WHDC circuit
board is missing).
101-System CONTlNUE
161-System CONTlNUE
options not set
CHECK
162-System
options not set
CONTINUE
164-Memory
size error
CONTINUE
163-Time & Data CONTlNUE
not set
601-Diskette
error
CONTINUE
~
~ §
~
;
>

ol:l­
I
t­
\C
(45H) WHDC
Unfixed circuit
value board
(45H) HDD or
Unfixed WHDC
value circuit
board
Rep lace the WHDC
circuit board
Replace the HDD
or WHDC circuit
board
This error is indicated under one
of the above conditions.
* HDC SELF TEST CHECK
An abnormal code was returned
during hard disk controller
selftest.
* HDD CHECK
The hard disk could not be recalibated.
* lf 1780-disk 0 failure is
displayed on the CRT screen, the
CMOS data in RTC is rewritten and
IPL from HDD is disabled.45H
1782-disk
controller
failure
1780-Disk 0
failure
1781-Disk 1
failure
CONRINUE
CONTINUE
----------------------------------------------------------------------------------------------------------
CONTINUE
(45 H) Setting
Unfixed error
value
Perform sett ing
correctly
* MAX CYLINDER, MAX HEAD, MAX SECTOR 1790-Disk 0
READ CHECK error
This error is indicated if the POD 1791-Disk 1
can not read the Max. sector of the error
Max.track which is determined by CMOS.
----------------------------------------------------------------------------------------------------------
CONTINUE
( 48H) ROM CHIP
Unfixed on 1/0
value slot
Rep lace ROM chip * 1/0 ROM CHECK xxxxO ROM
When the POD detect a 1/0 ROM ID, error
the POD execute check-sum for the
1/0 ROM.
This error message will be indicated
on the screen of the CRT.

~
I
N
o
----------------------------------------------------------------------------------------------------------
(49H) RTC
Unfixed (146818)
value
Replace RTC
(146818)
* TIME AND DATE CHECK
A range over error occurred when
hour, minutes, and seconds are
read even though RTC was normal:
1) Power failure was not detected
2) No error in RTC check sumo
3) RTC could enter update in
progress status.
4) RTC could be cleared from
update in progress status
This error is indicated if a range
over error occurs in hours,
minutes, or seconds as folIows:
Hours 23
Minutes 59
seconds > 59
~
~
~
~
(4CH)
Unfixed
value
The lock
was in
locked
status
Unlock the key * LOCK STATUS CHECK
The lock was in locked status.
302-System CONTINUE
unit keylock
is locked
None * P ARITY ERROR CHECK
When a parity error was detedted, Parity check 1 HALT
Entire memory is parity-checked again. or
The address of memory where the Parity check 2
parity error was detected is
indicated with a 5-digit
hexadecimal number. At this time,
a parity error cannot be found,
????? is indicated.
All error message will be indicated
on screen of CRT.
(Example)
If a parity error occurs in
addresses 512 to 576KB, the
following data is displayed on the
CRT screen: ~.>

.p­
I
N
""'"
Parity check 1
80000 (S)
(S) Segment
A parity error occurred in the
segment placed at address 80000
or later.
;
&.
~
~
~
§
~

CHAPTER
5
DISASSEMBLY AHD
ASSEMBLY
TAßLE OF CONTENTS
Section
5.1
5.1.1
5.1. 2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.1.8
5.1.9
5.1.10
5.1.11
5.1. 12
5.1.13
5.1. 14
5.1. 15
5.1.16
5.1.17
5.1.18
5.1. 19
5.1. 20
Title
~1AIN UNIT DIASSEt1BLY AND ASSH1BLY
Upper Case Removal ................•....................
Upper Case Rep 1acement •••••••••••••••••••••••••••••••••
Front Panel Removal ••••••••••••••••••••••••••••••••••••
Front Panel Replacement ..
Power Supply Unit (ATRPS Unit) Removal •••••••••••••••••
Power Supply Unit (ATRPS Unit) Replacement .
Optional Circuit Board Removal •••••••••••••••••••••••••
Optional Circuit Board Replacement •••••••••••••••••••••
Disk Drive (HDD or FDD) Removal ••••••••••••••••••••••••
Disk Drive (HDD or FDD) Replacement ••••••••••••••••••••
ANT-~1 Circuit Board Removal •••••••••••••••••••••••••••
ANT-RM Circuit Board Repl acement ..
~1ain (ANTA) Circuit Board Removal .
t1ain (ANTA) Circuit Board Replacement ••••••••••••••••••
ANT-tn Circuit Board Removal ..
ANT-HT Circuit Board Replacement ..
ANT-LS Circuit Board Removal •••••••••••••••••••••••••••
ANT-LS Circuit Board Replacement ..
Speaker Removal .
Speaker Replacement ••••••••••••••••••••••••••••••••••••
Page
5-1
5-1
5-1
5-2
5-2
5-3
5-3
5-4
5-4
5-5
5-5
5-6
5-6
5-7
5-7
5-8
5-8
5-9
5-9
5-10
5-10
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
KEYBOARD UNIT DISASSD1BLY AND ASSEMBLY ••••••••••••••••••• 5-11
Key Cyl inder Unit Removal 5-11
Key Cylinder Unit Replacement •••••••••••••••••••••••••• 5-11
POWER SUPPLY UNIT (ATRPS) DISASSEt1BLY AND ASSn1BLY ....... 5-12
Secondary-side Circuit Board Removal ••••••••••••••••••• 5-12
Secondary-side Circuit Board Replacement ••••••••••••••• 5-13
Fan Unit Removal 5-14
Fan Unit Replacement ••••••••••••••••••••••••••••••••••• 5-14
Primary-side Circuit Board Removal ••••••••••••••••••••• 5-15
Primary-side Circuit Board Replacement ••••••••••••••••• 5-15

Fi gure
5-1-1
5-1-2
5-1-3
5-1-4
5-1-5
5-1-6
5-1-7
5-1-8
5-1-9
5-1-10
5-2-1
5-3-1
5-3-2
5-3-3
Title
LIST OF FIGURES
Page
Upper Case Rernoval/Replacement 5-1
Front Panel Removal/Replacement 5-2
Power Supply Unit Removal /Repl acement 5-3
Optional Circuit Board Removal/Replacement 5-4
Disk Drive Removal/Replacement 5-5
ANT-ro1 Circuit Board Removal/Replacement 5-6
ANTA Circuit Board Removal/Replacement 5-7
ANT-t1T Circuit Board Removal/Replacement 5-8
ANT-LS Circuit Board Removal/Replacement 5-9
Speaker Removal/Replacement ..........•................... 5-10
Key Cylinder Unit Removal/Replacement 5-11
Secondary-side Circuit Board Removal/Replacement 5-12
Fan Unit Removal/Replacement 5-14
Primary-side Circuit Board Removal/Replacement 5-15

RHV .A
DIASSEHBLY AHn ASSEHBLY
5.1 MAn, URIT DISASSEMBLY Alm ASSEMBLY
5.1.1 Upper Case Removal
1. Unlock the key (B) to remove the upper case (A).
2. Remove the four screws (C) from the rear.
3. Slide the upper case forward.
4. Remove the upper case by opening the side section (1) in the direction
indicated by the arrows.
(B)
(A)
-)
FIGURE 5-1-1.
lPPER CASE Rml>VALlREPLACEMENT
5.1.2 Upper Case Replacement
1. Fit the upper case over the Iower case.
2. Slide the upper case to the rear.
3. Replace the four screws (C) at the back.
5. Lock the upper case if required.
5-1

DIASSEMBLY AND
ASSEMBLY
HEV.A
5.1.3 Front Panel Removal
1. Remove the upper case.
2. Remove the four screws (A) to remove the front panel.
(Al
(B)
FIGURE 5-1-2.
FRORT PAREL REMOVAL/RFPLACEMERT
5.1.4 Front Panel Replacement
1. Replace the front panel by attaching the four screws (A).
2. Replace the upper case.
5-2

RKV .A
DIASSEMBLY AND ASSEMBLY
5.1.5 Power Supply Unlt (ATRPS UBIT) Removal
1. Remove the upper ease.
2. Remove the two ANT-MT Board eonneetors (B), and the FDD and HDD power
suppIy eonneetors.
4. Remove the four serews (C) from the rear.
5. Slide the power suppIy unit (D) about 6 em towards the front to elear the
hold-down tabs and remove the unit.
FIGDRE 5-1-3.
POWER ·SUPPLY UBIT REtIlVAL/REPLACEMEBT
5.1.6 Power Supply Unit (ATRPS UBIT) Replacement
1. RepIaee the power suppIy unit by sliding it toward the rear over the holddown
tabs on the Iower ease.
2. Fasten the power suppIy unit with the four sere~lS (C).
3. Replaee the two ANT-MT Board conneetors (B), and the FDD and HDD power
suppIy eonneetors.
4. Replaee the upper ease.
5-3

DIASSEMBLY AND
ASSEMBLY
REV.A
5.1.7 Optiona! Circuit Board Remova!
1. Remove the upper case.
2. Disconnect the cab1es attached to the optional circuit board, if required.
3. Remove screw (A) which holds the board to the Iower case.
4. Remove the board by firmIy grasping the edge at both ends and pulling
directIy upwards.
(Al
F'IGURE 5-1-4.
OP TIONAL CIRCUIT BOARD REMOVALlREPLACEMENT
5.1.8 Optiona! Circuit Board Rep!acement
1. Insert the optional circuit board into the ANT-MT Board connector slot (B).
2. Fasten the board with screw (A).
3. Replace the cable connections.
4. Replace the upper ease.
5-4

REV .A
DIASSEKBLY AND ASSEKBLY
5.1.9 Disk Drive (HOD or FOD) Removal
1. Remove the upper case.
2. Disconnect the signal and power supply cables on the rear of the unit.
3. Remove the two side screws (A) fastening the drive.
4. Remove the drive unit by sliding it carefully out the front of the lower
case.
(A
(B)
FIGDRE 5-1-5.
DISK DRIVE REMOVAL/REPLACEMERT
5.1.10 DISK DRIVE (HOD or FOD) Replacement
1. Place the slider (B) at the left (to mount the drive horizontally) or at
the bottom (to mount the drive vertically) and attach the drive to the
lower case.
2. Fasten the drive with the two screws (A).
3. Connect the signal and power supply cables to the drive.
4. Replace the upper case.
(Note 1)
Arrange the signal and power supply cables, then fasten the
cables with the clamp attached to the po\'ler supply unH.
5-5

DIASSKMBLY AN» ASSKMBLY
HEV.A
5.1.11 ART-RH Circuit Board Removal
1. Remove the upper ease.
2. Remove the serew (B) fastening the ANT-RH board (A) to the Iower ease.
3. Remove the ANT-R}[ board by grasping the edge at both sides and pulling
direetIy upwards.
A
B
FIGURE 5-1-6. ART-RH CIRCUIT BOARD REHOVALlREPLACEMENT
5.1.12 ART-RH Circuit Board Replacement
1. Insert the ANT-RM board in the ANTA board eonnector slot (C).
2. Fasten the ANT-R}! board to the IO\ler ease w,ith the sereu (B).
3. Replaee the upper ease.
5-6

REV .A
DIASSEMBLY AND ASSEHBLY
5.1.13 Hain (ARTA.) Cireuit Board Removal
1. Remove the upper case.
2. Remove the ANT-ml circuit board.
3. Remove the foul' screws (D) fastening the ANTA board (C) to the lower case.
4. Disconnect the ANTA board connector (F).
5. Open the tabs (E) of the ANTA board towards the sides and slide the ANTA
board out 7 01' 8 cm towards the front.
6. Disconnectg the ANTA board connector (G).
7. Pull the ANTA board out all the way to remove it.
(F)
(B)
(H)
-- (El
FIGURE 5-1-7.
-
ANTA CIRCUIT BOARD REt«>VALlREPLACEMENT
5 .1.14 Hain (ANTA) Cireuit Board Replacement
1. Hold the ANTA circuit board (C) level and slide it horizontally toward the
real' until about 8 cm of clearance remains.
2. Replace the connector (G) on th~ ANTA board.
3. Slide the ANTA board horizontally to firmly seat it into the ANT-l1T board
connector (H).
Note: Make sure that no cables are held between the ANTA and AJ1T-MT boards.
4. Replace the ANTA board connector (F).
5. Replace the ANT-m: board.
7. Replace the upper case.
5-7

DISASSEMBLY AND
ASSEMBLY
REV.A
5.1.15 ART-MT Circuit Board Removal
1. Remove the upper ease.
2. Remove all optional eireuit boards.
3. Remove the ANT-mt board.
4. Remove the ANTA board.
5. Diseonneet the two eonneetors (A).
6. Remove the five serews (C) fastening the ANT-MT board (B) to the lower ease
and remove the ANT-MT board.
(C)
(B
FIGURE 5-1-8. ART-MT CIRCUIT BOARD REKOVALlREPLACEMENT
5.1.16 ART-MT Circuit Board Replacement
1. Replaee the ANT-MT board and fasten with the five serews (C).
2. Connect the two eonnectors (A).
3. Replaee the ANTA board.
4. Replaee the ANT-r~ board.
5. Replaee the optional eireuit boards.
6. Replaee the upper ease.
5-8

REV .A
DISASSEMBLY AHn ASSEMBLY
5.1.17 ANT-LS (LKD) Circuit Board Removal
1. Remove the upper case.
2. Disconnect connector CN6 on the WHDC circuit board.
3. Remove the ANT-HM board and disconnect the connector (A) from the ANTA
circuit board.
4. Disconnect the connector (B) from the speaker cable.
s. Disconnect the connector (D) from the case lock switch cable (C).
6. Remove the screws (F) fastening the ANT-LS circuit board (E).
7. Remove the ANT-LS board.
(G)
(D)
(F)
(Al
(El
(C)
(B)
FIGURE 5-1-9.
ANT-LS CIRCUIT BOARD REMOVAL/REPLACEMENT
5.1.18 ANT-LS Circuit Board Replacement
1. Replace the ANT-LS board (E) and fasten with the screws (F).
2. Pass the cable for the connector (A) through the hole (G) toward the main
circuit board.
3. Connect the connector (A).
4. Connect the connectors (B) and (D).
S. Replace the ANTA and ANT-IDI boards.
6. Connect connector CN6 of the WHDC circuit board.
7. Replace the upper case.
5-9

DISASSEKBLY ABO ASSEKBLY
REV.A
5.1.19 Speaker Removal
1. Remove the upper ease.
2. Remove the speaker eonneetor (A) frorn the ANT-LS board.
3. Remove the serew (C) fastening the speaker to the mounting board.
4. Remove the speaker.
Cl
(Al
FIGUBE 5-1-10.
SPEAKER REMOVAL/REPLACEMENT
5.1.20 Speaker Replacement
1. Replaee the speaker on the mounting board tdth the serew (C).
2. Conneet the speaker eable to the eonneetor (A) on the ANT-LS board.
3. Replaee the upper ease.
5-10

RKV .A
DISASSEMBLY AND ASSEMBLY
5 .2 KEYBOARD UNIT DISASSEMBLY AND ASSEMBLY
5.2.1 Key Cylinder Unit Removal
1. Remove the upper case.
2. Disconnect the connector (B) from the case lock switch cable (A).
3. Remove the screws fastening the key cylinder unit mounting plate.
4. Remove the key cylinder unit mounting plate.
(Bl
(Al
FIGURE 5-2-1.
KEY CYLINDER UNIT REMOVALlREPLACEMENT
5.2.2 Key Cylinder Unit Replacement
1. Fasten the key cylinder rnounting plate with the screws.
4. Connect the connector (B) to the ANT-LS board.
5. Replace the upper case.
5-11

DISASSEMBLY AND ASSEMBLY
REV.A
5.3 POWER SllPPLY UHIT (ATRPS) DISASSEMBLY ARD ASSEMBLY
5.3.1. Secondary-side Circuit Board Removal
1. Remove the five screws (A) to remove the cover (B).
2. Remove the four screws (C).
3. Pull up the secondary-side circuit board (D) 5 cm and disconnect the fan
connector (E).
4. Remove the cable clamp (F) in the following order:
(1) Hold the cable clamp (F) and rotate the clamp so that the cut
section of clamp 1S mated with the cut section of the power supply
case.
(2) Remove the cut section of the cable clamp.
(3) Remove the cable clamp.
5. Remove the cables (G) along the cut section of the power supply case to
remove the secondary-side circuit board.
(Bl
(Al
(0)
(F
FIGDRE 5-3-1. SECONDARY SIDE CIRCUIT BOARD RKKOVAL/REPLACKMKRT
5-12

REV .A
DISASSKMBLY AND ASSKMBLY
5.3.2 Secondary-side Circuit Board Replacement
1. Replace the cable clamp (F) on the cable (G).
Hold the cut section of the cable clamp so that it will not come off.
2. Insert the thinner section of the cable clamp in the hole on the power
supply case.
3. Connect the connector (E) to the secondary-side circuit board CD).
4. Fasten the secondary-side circuit board with the four screws (C).
5. Fasten the cover (B) with five screws (A).
5-13

DISASSEMBLY AND ASSEMBLY
REV.A
5.3.3 Fan Unit Removal
1. Remove the secondary-side circuit board.
2. Rernove the four screws (A) to rernove the fan unit.
(A)
FIGURE 5-3-2.
FAN UNIT REMOVALlREPLACEMENT
5.3.4 Fan Unit Replacement
1. Fasten the fan unit (B) with the four screws (A).
2. Replace the secondary-side ci.rcuit board.
5-14

RKV .A
DIASSEMBLY AND ASSEMBLY
5.3.5 Primary-side Circuit Board Removal
1. Remove the secondary-side circuit board.
2. Remove the fan unit.
3. Remove the t~lO connectors (D).
4. Remove the five screws (C) fastening the primary-side circuit board and
remove the screws (E) fastening the two cables connecting the AC outlet.
5. Slide the primary-side board horizontally to remove the board.
(E)
(A)
(C)
FlGUKE 5-3-3.
PRIHARY-SIDE CIRCUIT BOARD REMOVAL/RPPLACEKENT
5.3.6 Primary-side Circuit Board Replacement
1. Replace the primary-side circuit board by sliding in horizontally.
2. Fasten the primary-side board with the five screws (C).
3. Fasten the two cables connecting the AC outlet to the primary-side board
with the screws (E).
4. Connect the two connectors (D).
5. Replace the fan unit.
6. Replace the secondary-side circuit board.
5-15

CHAPTER
6
ADJUSTMENT AHD MAINTENANCE
TAßLE OF CONTENTS
Section
Title
Page

CHAPTER
7
DIAGRAMS AHD REFERENCE MATERIALS
TAßlE OF CONTENTS
Section
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
Title
SLIDE SWITCH &JUMPER CONNECTOR SETTINGS
Slide Switch Settings ....•.............................
Jumper Connector Settings •....................•........
GATE ARRAY DESC RIPTION .
GAATAB .•...•..•••...•.•.••..•..••.••.••....•••.•.•.••••
GAATCB .....•..•••..••...•.••..•....••••..••••••......••
GAATDB
GAATCK
GAATM2
GAATIO
GAATMl
GAATRF
GAATSP
GAATFD
••••..••••..••••••••.••••••••••.••••••••••••.••••
•••••••.••••.•.••••••••••••••.•••••.•••••••••••••
..•.•..•.•...•.••...•....•..•...•...••••...•••.••
•..••....••....••...•....•••....•....•.•..•....••
•••.•..............•.•...•••..•••.•..••••..•.••.•
.• •.•.••...••..•.•.•......•••..•••.•....••••••..•.
.••.•••.•••••••••.•••••.•••••••••••.•••••••••••••
•...•.••••...•...••..••....••••...•••...•..••••.•
Page
7-1
7-1
7-2
7-6
7-6
7-8
7-10
7-12
7-15
7-16
7-18
7-21
7-24
7-26
DIAGNOSTICS PROGRAf.1 7-28
LIST OF FIGURES
Figure
Title
Page
7-1-1
7-1-2
7-1-3
Slide Switch Setting 7-1
Va1ume Adj ustmen t 7- 1
Jumper Connectars 7-2
LIST OF TAßlES
Table
7-1-1
7-1-2
7-1-3
7-1-4
7-1-5
7-1-6
7-1-7
Title
Page
Hain (ANTA) Board Jumper Connections 7-2
Factory Settings (Main ANTA Board) 7-3
System Memory (ANT-RM) Board Jumper Connetions 7-3
Factory Settings (ANT-~1 Board) 7-4
HDD Controller (WHCD) Board Jumper Connections 7-4
Factory Settings (WHDC Board) 7-4
~1ulti -Function Adapter (SPFG) Board Jumper Connections.. 7-5

7-1-8 Factory Settings (SPFG Board) ........................... 7-5
7-2-1 GAATAB Pin Arrangement ·................................. 7-6
7-2-2 GAATAB Pin Description ·................................. 7-7
7-2-3 GAATCB Pin Arran gemen t ·................................. 7-8
7-2-4 GAATCB Pin Description ·................................. 7-9
7-2-5 GAATDB Pin Arrangement ·................................. 7-10
7-2-6 GAATDB Pin Description ·................................. 7-11
7-2-7 GAATCK Pin Arrangement ·................................. 7-12
7-2-8 GAATCK Pin Description ·................................. 7-13
7-2-9 GAAH12 Pin Description ·................................. 7-15
7-2-10 GAATIO Pin Description ·................................. 7-16
7-2-11 GAATM1 Pin Description ·................................. 7-18
7-2-12 GAATRF Pin Description ·................................. 7-21
7-2-13 GAATSP Pin Description ·................................. 7-24
7-2-14 GAATFD Pin Description ·................................. 7-26

REV .A DIAGRAMS AND REFERENCE MATERIALS
7.1 SLIDE SWITCH & JUMPER CORRECTOR SETTINGS
7.1.1 Slide Switch Settings
Monitor Select Switch
MONO : Monochrome Monitor (Factory setting)
COLOR: Color Monitor
CPU
Speed
6
8
10
Select Switch
6 r-filz
8 MHz (Factory setting)
10 MHz
OFF
ON
1-=11
I
I
MONO COLOR
MONITOR SELECT
1c.=J1
LLJ
6 8 10
CPU SPEED
FIGURE 7-1-1.
SLIDE SWITCH SETTINGS
Volume Adjustment
Turn clockwise to increase the volume.
Turn counter-clockwise to decrease the volume.
/~
VOLUME
FIGURE 7-1-2.
VOLUME ADJUSTMENT
7-1

DIAGRAMS AND REFERENCE MATERIALS
REV.A
7.1.2 JUMPER CONNEC'l'OR SETnNGS
Jumper Connectors
Jumper connectors provide a means to make a semi-permanent selection of a
particular operational function, for instance, the 'A' or 'B' function in Fig.
7-1-3 (1), where 'c' is the common terminal. If a jumper connection i8 called
'A-C', the jumper 1s connected as in configuration '2' in Fig. 7-1-3. If a
jumper connection is called 'B-C', the jumper is connected as in configuration
'3' in Fig. 7-1-3.
FIGURE ]-1-3.
JUMPER CONNEC'l'ORS
Hain (ANTA)
Board Jumper Connections
TABLE ]-1-1. MAllf (ANTA) BOARD JUMPER CONNECnONS
Jumper Number Function
J6 J5 J4 J3 J2 Jl
A-C Set CPU clock mode 6/8/10
* *
E-C Inhibit
A-C A-C Inhibit
A-C B-C Input CPU clock as NPX clock (1/3)
B-C A-C Input 8 MHz as NPX dock
* B-C B-C Inhibit
A-C 2 wait cycles for EPROM access
**
* * B-C 1 wait cycle for EPROM access
**
A-C A-C 4 ,..ait cycles for ext. 16-bit device access
**
A-C B-C 3 wait cycles for ext. 16-bit device access
**
E-C A-C 2 wait cycles for ext. 16-bit device access
**
B-C B-C
* * * *
1 wait cycle for ext. 16-bit device access **
Legend:
*
Not Applicable
**
Hait cycles available at 10 MHz operation
7-2

REV.A
DIAGRAMS
AN» REFERENCE MATERIALS
Factory Settings (Main ARTA Board)
TABLE 7-1-2. FACIDRY SETTINGS (MAlB ARTA BOARD)
Jumper
Factory
Number Setting Function
J1
]"-C
J2 A-C. > Input CPU clock as
J3 B-C > NPX clock
J4 A-C) 2 wait cycles for EPROM access
J5 ]"-C > 4 vlait cycles for external
J6 A-C > 16-bit device access
System Memory (ART-RH)
TABLE 7-1-3. SYSTEM MEMORY (ART-RH) BOARD JUMPER CONNECTIONS
Jumper Number
J7 J6 J5 J4 J3 J2 J1 Function
A-C A-G A-C 640KB Memory
A-C A-C B-C 512KB Memory
A-C B-C A-C
A-C B-C B-C 256KB Memory
B-C A-C A-C
B-C A-C B-C
B-C B-C A-C
* * B-C B-C B-C OOOKB (disable all RAM)
A-C A-C 27128
A-C B-C B-C A-C * * B-C B-C 27256 EPROM size
A-C A-C Select ROM pair 24].. and 24B
A-C B-C B-C A-C B-C B-C * * * * * Select ROM pair 23A and 23B
Legend: + = Not Applicable
Inhibited
7-3

DIAGRAKS AHn REFERENCE MATERIALS
HEV.A
Factory Settings
(ANT-RH Board)
TABLE 7-1-4.
FACTORY SETTINGS (ANT-RH BOARD)
Jumper Factory
Number Setting Function
J1 A-C > 64üKB
J2 A-C > Memory
J3 A-C > Size
J4 B-C > 27256 EPROM
J5 B-C > Memory Size
J6 A-C > Select ROM socket
J7 A-C > pair 24A and 24B
Hard Disk Controller (WHDC)
TABLE 7-1-5. HOD CONTROLLER (WHDC) BOARD JUMPER CONNECTIONS
Jumper Number
J3 J2 J1 Function
* * B-C
* * A-C
* B-C
*
* A-C
*
B-C
* *
A-C
* *
Select primary address sets
Select secondary address sets
Non-latched status (LED)
Latched status (LED)
WAR mode
WA2 mode
Factory Settings (WHDC Board)
TABLE 7-1-6. FACTORY SETTINGS (WHDC BOARD)
Jumper
Number
J1
J2
J3
Factory
Setting
f.,-C
B-C
B-C
Function
Secondary address sets
Non-latched status
\1AR mode
7-4

REV.A
DIAGRAMS AND REFERENCE MATERIALS
Multi-function Adapter (SPFG)
TABLE 7-1-7.
MULTI-FUBCTIOR ADAPTER. (SPFG) BOARD JUMPER CONRECTIORS
Jumper Number
J8 J7 J6 J5 J4 J3 J2 Jl JI0 J9 Function
A-C A-C Primary register set (3FO-3F7) AT:FDC
A-C B-C Secondary regis. set (370-377) AT:FDC
B-C A-C PC register set (3FO-3F7) : FDC
* * B-C B-C * Disable FDC register set
A-C A-C A-C Primary parallel I/F (378-37F) :IRQ 7
B-C A-C B-C Secondary paral. I/F (278-27F):IRQ 5
* * * * A-C B-C * * A-C * Parallel I/F on video adapter
( 3BC-3BF) : IRQ 7
* * B-C B-C * Disable parallel I/F
A-C A-C A-C Primary serial I/F (3F8-3FF) : IRQ 4
B-C A-C B-C Secondary serial I/F (2F8-2FF):IRQ 3
A-C B-C Disable serial I/F
* B-C B-C Disable serial I/F
A-C AT drive I/F
* B-C EQUITY-3 drive I/F
A-C Standard configuration
B-C * * * * * * * * * Test mode of VCO
Factory Settings
(SPFG Board)
TABLE 7-1-8.
FACTORY SETTIRGS (SPFG BOARD)
Jumper Factory
Number Setting Function
J1 A-C > Primary register
J2 A-C > set of AT
J3 A-C > Primary
J4 A-C > parallel
J10 A-C > I/F IRQ 7
J5 A-C > Primary
J6 A-C > serial
J9 A-C > I/F : IRQ 4
J7 A-C AT drive I/F
J8 A-C Standard configuration
7-5

DIAGRAMS AND REFERENCE MATERIALS REV.A
7.2 GATE ARRAY DESCRIP TION
7.2.1 GAATAB
GAATAB controls the CPU address bus, system address bus and the internal
address bus. It has an 8-bit refresh counter.
TABLE 7-2-1.
GAATAB P IN ARRANGEMENT
SIGNAL PIN PIK SIGNAL
NAME 1/0* NO. NO. 1/0* NAME
TESTN I 1 64 Vcc
ALP. I 2 63 I A16
Al I 3 62 I Al5
AZ I 4 61 I A14
A3 I 5 60 I Al3
XAO Tri 6 59 Tri XA16
XAl Tri 7 58 Tri XA15
LSAO I 8 57 T DXA
XAZ Tri 9 56 Tri XA14
XA3 Tri 10 55 Tri XA13
SAO Tri 11 54 Tri. XA12
SA1 Tri 12 53 Tri SA16
SA2 Tri 13 52 Tri SA15
SA3 Tri 14 51 Tri SA14
SM Tri. 15 50 Tri SAl3
GNDA 16 49 GNDB
GNDB 17 48 GNDA
SAS Tri 18 47 Tri SA12
SA6 Tri 19 46 Tri SAH
SA7 Tri 20 45 Tri SA10
SA8 Tri 21 44 Tri SA9
XA4 Tri 22 43 Tri XAll
XAS Tri 23 42 Tri XA10
XA6 Tri 24 41 Tri XA9
OP.-N I 25 40 I R590N
XA7 Tri 26 39 Tri XA8
A4 I 27 38 I A12
A5 I 28 37 I All
A6 I 29 36 I A10
A7 I 30 35 I A9
A8 J 31 34 I G590N
Vcc 32 33 I C590
* Legend: I Input Pin
0 Output P in
Tri Tri-state Pin (Input, Output, High-impedance)
7-6

REV .A
DIAGRAMS AND REFERENCE MATERIALS
TABLE ]-2-2.
GAATAB PIN DESCRIPTION
SYMBOL 1/0* PIN NO.
NAME AND
FUNCTION
A16-1 I 63-60,38-35,
31-27,5-3
LSAO I 8
SA16-0 Tri 53-50,47-44
21-18, 15-11
XA16-0 Tri 59,58,56-54,
43-41,39,26,
24-22,10,9,
7,6
ALE I 2
OEN I 25
DXA I 57
C590 I 33
G590N I 34
R590N I 40
TESTN I 1
CPU address bus.
Converted address O. It is identical to CPU
address 0 (AO), except when word to byte
conversion is being performed.
System address bus.
Internal address bus.
Address latch enable. A16-1 are latched by ALE.
Enable control of latched address (A16-1). When
low, LSAO and latched A16-1 are enabled.
Direction control of internal address bus(XA16­
0) buffer. When high XA16-0 are driven by SA16­
0, and when low SA16-0 are driven by XA16-0.
Clock of refresh counter. Refresh counter
increments at C590 rising edge.
Outpu t enable of refresh counter. When low,
refresh address is placed on SA7-0.
Reset on refresh counter. When low, refresh
counter is cleared.
Test input. Should be pulled up.
* Legend: I
o
Tri
Input Pin
Output P in
Tri-state Pin (Input, Output, High Impedance)
7-7

DIAGRAHS AND REFERENCE MATERIALS REV.A
7.2.2 GüTeB
GAATCB controls the CPU control bus and the most significant 7 bits of the
address bus. Contains one inverter, one NOR gate and one NANO gate.
TABLE 7-2-3.
SIGNAL PIN
NAME 1/0* NO.
GAATeB PIN ARRANGEMENT
PIN SIGNAL
NO. 1/0* NAME
GSA-N
DLA
ALE
OE-N
RFMRN
RFC-N
BHE
MIO
SBHE
SMIO
XBHE
(NC)
LA17
LA18
LA19
GOOA
GOOB
LA20
LA21
LA22
LA23
A17
A18
A19
(NC)
A20
A21
(NC)
A22
A23
(NC)
Vcc
I
I
I
I
I
I
I
I
Tri
O&H-Z
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
I
o
I
I
o
I
I
o
I
I
Tri
Tri
Tri
Tri
O&H-Z
O&H-Z
O&H-Z
O&H-Z
O&H-Z
Tri
Tri
Tri
Tri
Vcc
Vi
VO
NRI2
NDl1
NRO
NDIZ
OOll
000
DXR\~
GSRWN
IOW-N
IOR-N
MEMRN
MEMWN
GNDB
GOOA
8A17
SA18
8A19
SMR-N
SMW-N
(NC)
(NC)
(NC)
(NC)
XIO\m
(NC)
XIORN
XMW-N
XMR-N
(NC)
* Legend: I
o
Tri
O&H-Z
Input P in
Output Pin
Tri-state Pin (Input, Output, High-impedance)
Output & High-impedance Pin
----....;;...---~-~---------------
7-8

REV .A DIAGRAMS AHn REFERENCE MATERIALS
TABLE 7-2-4.
GAATCB PIB DESCRIPTIOB
SYMBOL 1/0* PIB NO. NAKE AND FUBCTIOB
A23-17 Tri
SA19-17 O&H-Z
LA23-17 l
BHE
SBHE
XBHE
MIO
SHIO
IOWN
lORN
MEMHN
MEHRN
XIOWN
XlORN
XMWN
XMRN
SMWN
SHRN
DLA
GSAN
ALE
OEN
DXRW
GSRWN
RFMRN
RFCN
VI
VO
NDIl
NDI2
NDO
NDIl
I
Tri
Tri
I
O&H-Z
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
O&H-Z
O&H-Z
I
I
I
I
I
I
I
I
I
T
l
I
o
I
30,29,27,26,
24-22
45-47
21-18,15-13
7
9
11
8
10
53
52
50
51
38
36
35
34
43
44
2
1
3
4
55
54
5
6
63
62
57
58
56
60
CPU
address bus.
System address bus. (8-bit connector).
Unlatched system address bus. (16-bit
connector).
CPU bus high enable signal.
System bus high enable signal. (16-bit
connector).
Internal bus high enable signal.
CPU memory / 1/0 signal.
Buffered memory / 1/0 signal.
System 1/0 write signal. (8-bit connector).
System 1/0 read signal. (8-bit connector).
System memory write signal (16-bit connector).
System memory read signal (16-bit connector).
Internal 1/0 write signal.
Internal 1/0 read signal.
Internal memory write signal.
Internal memory read signal.
System memory write signal (8-bit connector).
System memory read signal (8-bit connector).
Direction control of CPU address bus (A23-17)
buffer. When high, LA23-17 are driven by A23­
17. And when low A23-17 are driven by LA23-17.
Enable control of address bus (SAI9-17) buffer.
When low, SA19-17 are driven by AI9-17.
Address latch enable. A19-17 and MIO and BHE
are latched by ALE.
Enable control of latched address (A19-17), MIO
and BHE. When low, SA19-17 are driven by latched
A19-17. When low, SMIO and SBHE are driven by
latched MIO and BHE, respectively.
Direction control of CPU control bus. When
high, XIOWN, XIORN, XNWN and XNRN are driven by
IOWN, IORN, MEMWN, and HE}ffiN respectively. When
low, IOWN, TORN, MEMWN and MEMRN are driven by
XIOWN, XIORN, XMWN, and XHRN respectively.
Enable control of SMWN and SMRN. When 10\., SHWN
and SMRN are enabled.
Memory read pulse of refresh cycle. RFMRN is
used in conjunction with RFCN signal.
Refresh enable. When low, MEMRN, XMRN and SMRN
are driven by RFMRN.
Input of inverter.
Output of inverter.
Input of NAND gate.
Input of NAND gate.
Output of NAND gate.
Input of NOR gate.
7-9

DIAGRAMS AND REFERENCE MATERIALS REV.A
NDI2 I 61 Input of NOR gate.
NOR 0 59 Output of NOR gate.
7.2.3 GAAmB
* Legend: I Input Pin
0 = Ouput P in
Tri Tri-state Pin (Input, Output, High-impedance)
O&H-Z Output and High-impedance P in
GAATDB has two data bus buffers (system data bus buffer and memDry data bus
buffer) and a low to high byte conversion buffer.
TABLE 7-2-5.
GAAmB PIN ARRANGEMENT
SIGNAL PlIi PIN SIGNAL
NAME 1/0* 11). 11) • 1/0* NAME
DO Tri 1 64 Vcc
D1 Tri 2 63 Tri D15
D2 Tri 3 62 Tri D14
D3 Tri 4 61 Tri Dl3
MDO Tri 5 60 Tri D12
MD1 Tri 6 59 Tri MD15
DMD I 7 58 I CBA
GMDHN I 8 57 I SBA
GMDLN I 9 56 Tri MD14
MD2 Tri 10 55 Tri ~1Dl3
MD3 Tri 11 54 Tri MD12
SDO Tri 12 53 Tri SD15
SD1 Tri 13 52 Tri SD14
SD2 Tri 14 51 Tri SDl3
SD3 Tri 15 50 Tri SD12
GNDA 16 49 GNDB
GNDB 17 48 GNDA
SD4 Tri 18 47 Tri SDll
SD5 Tri 19 46 Tri SD10
SD6 Tri 20 45 Tri SD9
SD7 Tri 21 44 Tri SD8
MD4 Tri 22 43 Tri MD 11
MD5 Tri 23 42 Tri HDlO
MD6 Tri 24 41 I DD
D245 I 25 40 I GDH-N
G245N I 26 39 I GDL-N
MD7 Tri 27 38 Tri MD9
D4 Tri 28 37 Tri MD8
D5 Tri 29 36 Tri Dll
D6 Tri 30 35 Tri DlO
D7 Tri 31 34 Tri D9
Vcc 32 33 Tri D8
* Legend: I Input Pin
o Output P in
Tri Tri-state Pin (Input, Output, High-impedance)
7-10

REV .A DIAGRAMS AHn REFERENCE MATERIALS
TADLE 7-2-6.
GAA'IDB PIB DESCRIPTIOB
SYMBOL
1/0*
PllI !K).
NAME AND FUBCTIOB
D15-0
MD15-0
SD15-0
DD
GDHN
GDLN
CBA
SBA
DMD
GMDHN
GMDLN
D245
G245N
Tri
Tri
Tri
I
I
I
I
I
I
I
I
I
I
63-60,31-28
4-1,33-36
59,56-54,43,
42,38,37,27,
24,23,22,11,
10,6,5
53-50,47-44
21-18,15-12
41
40
39
58
57
7
8
9
25
26
CPU
data bus.
Memory data bus.
System data bus.
Direction control of CPU data bus(D15-0) buffer.
When low, CPU reads data from MD15-0 or SD15-0.
Enable control of CPU data bus high byte (D15-8)
buffer. When low, it enables high byte.
Enable control of CPU data bus low byte (D7-0)
buffer. When low, it enables low byte.
Read data latch. SD7-0 are latched at CBA rising
edge.
SBA selects latched or un-latched data. When
high, latched data are selected. SBA is used in
conjunction with CBA signal.
Direction control of Memory data bus (HD15-0)
buffer. When high Memory data is read.
Enable control of Hemory data high byte (MD15-8)
buffer. When low, it enables high byte. GMDEN
is used in conjunction with D~ID signal.
Enable control of Hemory data low byte (MD7-0)
buffer. When low, it enables low byte. GHDLN is
used in conjunction with DMD signal.
Direction control of low to high byte conversion
buffer. When low, it indicates high to low byte
conversion during data transfers to 8-bit
peripherals (write). When high, it indicates low
to high byte conversion during data transfers
from 8-bit peripherals (read).
Enable control of low to high byte conversion
buffer. It is active low signal and is used in
conjunction with D245 signal.
* Legend: I = Input Pin
o = Output P in
Tri Tri-state Pin (Input, Output, High-impedance)
7-11

DIAGRAMS AND REFERENCE MATERIALS
REV.A
7.2.4 GAATCK
GAATCK includes following functional blocks.
(1) Clock generator
CPU dock, 80287 dock, System clock,
DMA clock, 8042 dock, 8254 dock,
NTSC dock (14.31818 MHz)
(2) Ready circuit
(3) Reset circuit
(4) Bus controller
HEMR, MEMW, lOR, lOW, lNTA, ALE, DTR, DEN
(5) Shut down circuit
TABLE 7-2-7.
GAATCK PIR ARRANGEMENT
SIGNAL PIR PIR SIGNAL
NAME 1/0* JIiI) • JIiI) • 1/0*
,..•_,_ .._~--_.~._--,. -----. --._.-.~.,,--- ..----.----.._._.-
NAME
C14M I 1 64 Vcc
HLDA I 2 63 I C48H
Al I 3 62 I COFF
RSWN I 4 61 I CDLY
RSWP I 5 60 I CSPDO
PWGD I 6 59 I CSPD1
(NC) 7 58 (NC)
(NC) 8 57 (NC)
(NC) 9 56 0 RSN
ENAS 0 10 55 0 C1M
DTR 0 11 54 0 EMEMR
ACKN 0 12 53 0 DEN
EALE 0 13 52 0 BALE
RSDV 0 14 51 0 AEN
CLKO 0 15 50 0 SCLK
GNDA 16 49 GNDB
GNDB 17 48 GNDA
MEHR O&lI-Z 18 47 0 OSC
MEMW O&H-Z 19 46 O&H-Z lOR
ALE 0 20 45 O&lI-Z IOW
lNTA O&H-Z 21 44 0 PCLKP
DCLK 0 22 43 0 PCLKN
RDY 0 23 42 0 RSCPU
(NC) 24 41 0 C8H
(NC) 25 40 (NC)
RC I 26 39 (NC)
HSTR I 27 38 (NC)
HlO I 28 37 I SRDY
Sl I 29 36 I ARDY
SO I 30 35 I AREN
C20M I 31 34 I TEST
Vcc 32 33 I CLKI
* Legend: I Input Pin
0 = Output Pin
O&H-Z Output & High-impedance Pin
7-12

REV .A DIAGRAMS AHn REFERENCE MATERIALS
TABLE 7-2-8.
GAATCK PIN DESCRIPTION
SYMBOL 1/0* PU NO. NAME AND FUNCTION
C48M
C20M
C14M
PCLKP
PCLKN
OSC
CIM
C8M
DCLK
SCLK
CLKO
CLKl
CSPDI
CSPDO
I
I
I
o
o
o
o
o
oo
o
I
I
I
63
31
1
44
43
47
55
41
22
50
15
33
59
60
Clock input. 48 MHz.
Clock input. 20 MHz.
Clock input. 14.31818 MHz.
(+) KB controller (8042) clock. 6 MHz.
(-) KB controller (8042) clock. 6 MHz.
Clock output. 14.31818 MHz. (for option slot)
Clock output. 1.19 MHz. (for 8254)
Clock output. 8 MHz, duty 33%. (for 80287)
DMA CLOCK
System clock.
CPU clock output.
CPU clock input. CLKl should be connected to
CLKO externally.
CPU clock select.
CPU clock select.
CSPDI
o
1
1
o
CSPDO
1
1
o
o
SCLK
6 MHz
8 MHz
10 HHz
12 MHz
CLKO
12 MHz
16 MHz
20 HHz
24 MHz
CLKl
12 MHz
16 MHz
20 MHz
24 MHz
DCLK
3 MHz
4 MHz
5 MHz
6 MHz
pweD
RSWN
RSWP
RSN
RSDV
AREN
ARDY
SRDY
RDY
MIO
SI
SO
I
I
I
o
o
I
I
I
o
I
I
I
6
4
5
56
14
35
36
37
23
28
29
30
Power good. When low, it indidates that power is
not good and reset signals (RSN, RSDV, RSCPU)
are activated.
(-) Reset switch activation signal. RSWN becomes
low.
(+) Reset switch activation signal. RSWP becomes
low.
(-) Reset signal. (for internal circuit)
(+) Reset signal. (for option slot)
(-) Asynchronous ready and synchronous ready
enable.
(-) Asynchronous ready input. It is used in
conjunction with AREN signal.
(-) Synchronous ready input. It is used in
conjunction with AREN signal.
(-) Ready output.
Memory or 1/0 select. When low, the current bus
cycle is in the r/o space.
Bus cycle status.
Bus cycle status.
MIO
SI
o 0
o 0
o 1
o 1
1 0
so
o
1
o
1
o
Type of bus cycle
IN TA
10 READ
10 WRITE
NONE, IDLE
HALT OR SHUT DOWN
7-13

DIAGRAHS AHn REFERENCE MATERIALS
REV.A
1
1
1
o
1
1
1
o
1
MEHORY READ
MEMORY WRI TE
NONE, IDLE
COFF
CDLY
HLDA
ALE
DEN
DTR
MEHR
MEMW
IOR
IO\-l
INTA
EHEHR
EALE
BALE
MSTR
ACKN
AEN
Al
Re
RSCPU
ENAS
TEST
I
I
I
o
o
o
O&H-Z
O&H-Z
O&H-Z
O&H-Z
O&Il-Z
o
o
o
I
o
o
I
I
o
o
I
62
61
2
20
53
11
18
19
46
45
21
54
13
52
27
12
51
3
26
42
10
34
(+) Control off. When high, command and DEN
signal are forced inactive.
Command delay. When high, the start of command
output is delayed.
Hold acknowledge. When high, command output
becomes 3-state off.
Address latch enable.
Data bus enable.
Data transmit/receive. "!hen high, this control
output indicates that a write bus cycle is being
performed.
(-) Hemory read command.
(-) Hemory write command.
(-) 1/0 read command.
(-) 1/0 write command.
(-) Interrrupt acknowledge.
(-) Early memory read signal.
Early address latch enable.
Buffered address latch enable.
(-) Haster. A processor or DHA controller on the
1/0 channel may pull this signal low.
(-) Acknowledge. \l.Then low, mtA controller (or
refresh controller) has control of the address
bus, data bus and control bus.
(+) Address enable.
Address 1.
(-) Reset CPU input from 8042.
(+) Reset CPU output. When high, CPU is reset.
RSCPU becomes active when:
(1) P~?GD is low·.
(2) Reset switch is activated.
(3) 8042 pulls RC signal low.
(4) CPU executes shutdown cycle.
(-) Enable control of RTCAS (RTC address strobe)
signal.
(-) Test input. TEST should be pulled high.
* Legend: 0
I
O&H-Z
Output
Input
Output & High-impedance Pin
7-14

REV .A DIAGRAMS AND REFERENCE MATERIALS
7.2.5 GAA'l'M2
GAATM2 generates memory address and RAS, CAS, WE signals used witb GAATM1 and
tbe delay line to control DRAM.
TADLE 7-2-9.
GAA'l'M2 PIN DESCRIPTION
SYMBOL
1/0*
PIX NO.
NAME AND
FUNCTION
SA18-0
MA8-0
HEMR
HEMW
EMRN
XMWN
RFHN
D40
D80
D160
D200
RA1
RAO
CAR
CAL
RAS1
RAS0
CASH
CASL
WE
RAS
TEST
I
o
I
I
I
I
I
I
I
I
I
I
I
I
I
o
o
o
o
o
o
I
3,5,6,13-16,
18,20-24,
27-32
44,43,41,40,
9-7 ,12,11
61
62
46
63
64
52
50
48
47
35
37
38
39
59
60
56
55
45
53
54
System address bus.
DRAM
address bus.
(-) System memory read signal.
(-) System memory write signal.
(-) Early memory read signal.
(-) Internal memory write signal.
(-) Refresb signal.
40 ns delayed signal from RAS.
80 ns delayed signal from RAS.
160 ns delayed signal from RAS.
200 ns delayed signal from RAS.
(+) RA1 signal is used to generate RAS1 signal.
(+) RAO signal is used to generate RASO signal.
(+) CAR signal is used to generate CASH signal.
(+) CAL signal is used to generate CASL signal.
(-) Row address strobe for DRAM (80000H-9FFFFH).
(-) Row address strobe for DRAM (OH-7FFFFH)
(-) Column address strobe for DRAM (OH-9FFFFH,
odd byte).
(-) Column address strobe for DRAM (OH-9FFFFH,
even byte).
(-) Write enable signal for DRAM.
(+) RAS is generated from logical OR of MEMR and
HEMW. This output is used to generate delay
signals (D40, D80, D160, D200)
(-) Test input. TEST should be pulled up.
* Legend: I = Input Pin
o Ouput Pin
7-15

DIAGRAMS AN» REFERENCE MATERIALS REV.A
7.2.6 GAATIO
GAATIO
includes following functional blocks.
(1) Address decoder of 1/0 space.
(2) D~~ page register (741S612 compatible)
(3) Port B.
(4) ~~I enable register.
(5) Address latch for D~.
(6) Interface circuit between NP (80287) and CPU (80286).
(7) General purpose gates.
--- 1 inverter, 1 NANO gate, two 3-state buffers.
TABU 7-2-10.
GAATIO PIN DESCRIPTION
SYMBOL 1/0* PIB NO. NAME AND FUNCTION
XD7-0
A23-17
STB2
STB1
I
I
AE01 0
MSTN
Tri
O&H-Z
XA16-10 O&H-Z
XA9-8
XA7-1
XAO
XIWN
XIRN
RSTN
DK7N
DK6N
DK4N
DK3N
DK2N
DKON
DAK4
RFHN
ACKN
Tri
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AEN2 I
AEN1 I
AE02 0
I
38-31
66,68,70,72,
74,76,80
77,75,73,71,
69,67 ,64
62,63
61-55
52
12
11
30
21
20
19
18
17
16
14
85
86
26
27
22
23
96
97
87
Internal data bus.
CPU address bus.
>
> > Internal address bus.
>
>(-)
Internal 1/0 write signal. (= -XIOW)
(-) Internal 1/0 read signal. (= -XIOR)
(-) Reset.
-DACK7. D~~ acknowledge 7.
-DACK6. D~~ acknowledge 6.
-DACK4. D~~ acknowledge 4.
-DACK3, D~ acknowledge 3.
-DACK2. D~ acknowledge 2.
-DACKO. D~ acknowledge O.
+DACK4. This signal is output.
(-) Refresh signal.
(-) D~ acknowledge. ACKN is active when DMA or
refresh cycle is being performed.
(+) DHAC-N02 (16-bit D~ controller) address
strobe signal.
(+) DMAC-N01 (8-bit DMA controller) address
strobe signal.
(+) Address enable signal of D~C-N02.
(+) Address enable signal of DMAC-N01.
(-) AE02 is active when D~~C-N02 has control of
the system.
(-) AE01 is active when D~C-N01 has control of
the system.
-t~STER. When low, it indicates that the master
on the option slot (DMAC or CPU on the slot) has
the control of the system.
7-16

REV.A
DIAGRAMS AND REFERENCE MATERIALS
ITAN
SMIO
NERN
NBSN
Q1
ENAS
CD2N
CD1N
CI2N
CIlN
CTMN
CKBN
RTRW
RTDS
RTAS
NPRS
NCSN
CBSN
IR13
DXD
NMI
SPEK
TM2G
ENPR
IOEN
OUT2
PCKN
VI
VO
NAII
NAZI
NAnO
TS20
TSI
TSO
TSVI
TSVO
I
I
I
I
I
I
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
I
I
I
o
I
I
o
O&II-Z
I
O&H-Z
I
O&H-Z
100
88
8
7
89
98
24
25
42
41
47
99
44
45
46
6
5
9
43
39
10
51
48
81
92
49
82
84
83
95
94
93
91
1
2
13
50
-INTA. Interrupt acknowledge.
Memory or 1/0 select.
(-) NP (80287) error.
(-) NP (80287) busy.
Q1 is a timing signal to generate RTAS signal.
(-) Enable control ot RTAS signal.
(-) Chip select of D~~C2 (8237).
(-) Chip select of DMAC1 (8237).
(-) Chip select of INTC2 (8259).
(-) Chip select of INTC1 (8259).
(-) Chip select of system TIMER (8254).
(-) Chip select of keyboard controller (8042).
(-) Write signal of real time clock (HD146818).
(-) Read signal of RTC (HD146818)
(+) ALE signal of RTC (HD146818).
(+) NP (80287) reset signal.
(-) Chip select ~w (80287).
(-) CPU (80286) busy signal.
(+) Interrupt request 13.
Direction control of 8 bit internal data bus
(XD7-0) buffer.
(+) Non-maskable interrupt request.
Output signal for speaker.
Time r CH2 gate. This signal is connected to
channel 2 gate input of timer LSI (8254).
(+) Enable RAM parity check.
1/0 channel error (option slot).
Timer CH2 output. This signal is connected to
channel 2 output of timer LSI (8254).
(-) Parity check error.
Input of inverter.
Output of inverter.
Input of NAND gate.
Input of NAND gate.
Output of NAND gate.
Output of 3-state buffer.
Enable control (active low) of 3-state buffer.
Output of 3-state buffer.
Enable control (active low) of 3-state buffer.
Output of 3-state buffer.
* Legend: I
o
Tri
O&l1-Z
Input P in
Ouput Pin
Tri-state Pin (Input, Output, High-impedance)
Output & High-impedance P in
7-17

D1AGRAKS AND REFERENCE MATERIALS
REV.A
7.2.7 GAATMI
GAATM1
includes the following functional blocks.
1. Address decoder for ROM and DRAM
2. Parity checker / generator
3. Additional circuitry for the memory expansion card
(This circuit is not used in EQUITY 111+ / EPSON PC AX.)
TABLE 7-2-11.
GAATMI P1N DESCRIPTION
SYMBOL 1/0* PIN No. NAME AND FUNCTION
A23-17
RFHN
XAJ
I
I
I
3-9
17
2
CPU address bus.
(-) Refresh signal.
ROM address select. XA16 or XA15 should be
connected to XAJ. ROM address range:
CSFN
CSEN
XAJ
X.A16
OFOOOO-OFFFFF
FFOOOO-FFFFFF
OEOOOO-OEFFFF
FEOOOO-FEFFFF
XAJ
XA15
OF8000-0FFFFF
FF8000-FFFFFF
(OE8000-0EFFFF)
(FE8000-FEFFFF)
OFOOOO-OF7FFF
FFOOOO-FF7FFF
(OEOOOO-OE7FFF)
(FEOOOO-FE7FFF)
ALE I 15
HI1)A I 16
XMRN I 14
XBHE I 18
XAO I 19
JRAH J 60
JRAL I 59
JEFN I 56
JEO
JROM
J1MN
I
I
I
57
55
28
(+) Address latch enable.
(+) Hold acknowledge.
(-) Internal memory read signal.
Internal bus high enable signal.
Internal address bus o.
(+) Enable control of RAM from 080000H to
09FFFFH.
(+) Enable control of RAM from 040000H to
07FFFFH.
(-) RAM address select. When low t RAM address is
assigned from FOOOOOH to F9FFFFH. Th is input
should be high or open in EQUITY 111+ / EPSON PC
AX.
(+) RAM address select. When high t RAM address
is assigned from OOOOOOH to 09FFFFH. This input
should be high or open in EQUITY 111+ / EPSON PC
AX •
(+) Enable control of ROM. When high t ROM is
enabled. This input should be high or open in
EQUITY III+ / EPSON PC AX.
(-) Chip select input for memory expansion card
which uses 1Mbit RAM chips. This input should be
high or open in EQUITY 111+ / EPSON PC AX.
7-18

REV.A
DIAGRAMS AND REFERENCE MATERIALS
JKN
RA23
D40
I
I
I
LMGN 0
CRON 0
CRAN 0
CSFN 0
CSEN 0
RA1 0
RAO 0
CAR 0
CAL 0
RS3N 0
RS2N 0
DHD 0
MA9 0
DM15-0
HP01
MPOO
I
I
MPIl 0
HPIO 0
EPR1
EPR2
PCKN 0
ERON
I
I
I
O&I1-Z
25
23
24
10
12
11
53
54
64
63
62
61
31
30
13
29
48-33
50
52
49
51
21
22
20
32
(-) Chip select input for memory expansion card
which uses 256Kbit RAH chips. This signal should
be high or open in EQUITY 111+ / EPSON PC AX.
(+) Timing input for RS3N and RS2N. (When GAATMl
is used in memory expansion card.) This signal
is not used in EQUITY III+ / EPSON PC AX, and
should be high or open.
40 ns delayed signal from RAS. (When GAATM1 is
used in memory expansion card.) This signal is
not used in EQUITY III+ / EPSON PC AX, and
should be high or open.
(-) Chip select of low order 1Hbyte memory
space. LMGN is active when memory space from
OOOOOOH to OFFFFFH is accessed.
(-) ROM chip select.
RAM chip select.
(-) Read signal of BIaS ROM.
(-) Read signal of reserved ROM.
(+) RA1 signal is used to generate RAS1 signal
in GAATM2.
(+) RAO signal is used to generate RASO signal
in GAATM2.
(+) CAR signal is used to generate CASH signal
in GAATM2.
(+) CAL signal is used to generate CASL signal
in GAATM2.
(-) Row address strobe for DRAM. (When GAATM1 1s
used in memory expansion card.) This signal is
not used in EQUITY 111+ / EPSON PC AX.
(-RAS2) Row address strobe for DRAM. (When
GAATM1 is used in memory expansion card.) This
signal is not used in EQUITY 111+ / EPSON PC AX.
Direction control of memory data bus buffer.
Dynamic RAM address 9. (When GMTM1 is used in
memory expansion card.) This signal is not used
in EQUITY III+ / EPSON PC AX.
Memory data bus.
Parity bit of odd address byte. MP01 is paritychecked
with MD15-8 in memory read cycle.
Parity bit of even address byte. MPOO is paritychecked
with }ID7-0 in memory read cycle.
Parity bit of odd address byte. MPIl is
generated from ~ID15-8 in memory write cycle.
Parity bit of even address byte. MPIO is
generated from MD7-0 in memory write cycle.
(+) Enable RAM parity check. When high, parity
check circuit is enabled. And when low, parity
check circuit is cleared.
(-) Enable RAM parity check. This signal 1s not
used in EQUITY 111+ / EPSON PC AX, and should be
pullec1 down.
(-) Parity error signal. When low, it indicates
that parity error has occurred.
(-) Parity error signal. 3-state output. This
signal is not used in EQUITY III+ / EPSON pe /IX.
7-19

DIAGRAMS AHn REFERENCE MATERIALS
HEV.A
* Legend: I
o
O&H-Z
Input Pin
Output Pin
Output & High-impedance Pin
In EQUITY 111+ / EPSON pe AX the following
INPUT
JEFN JEO JROM JIMN JKN RA23 D40
EPR2
OUTPUT
RS3N RS2N MA9
ERON
signals are not used.
high or open
low
no connection
]-20

REV.A
DIAGRAMS AND REFERENCE MATERIALS
7.2.8 GAATRF
GAATRF
includes the following functional blocks.
1. DRAM refresh control circuit.
2. DHA control circuit.
3. 16 8 data conversion circuit.
4. Wait states insertion circuit.
5. Command delay control circuit.
6. XAO, XBHE control circuit.
SYMBOL
1/0* PIN NO.
TABLE 7-2-12.
GAATRF PIN DESCRIPTION
NAME AND FUNCTION
~.,rSO
WS1
I 15
I 40
Zero wait insertion. When low, wait state is not
inserted. -OWS signal of option slot is
connected to this pin.
Wait states control of BIOS-ROM access.
The number of wait states of BIOS-ROM (OEOOOO­
OFFFFF, FEOOOO-FFFFFF) is controlled by WS1.
CSPD WS1 Wait states
0 (10 MHz) 0 2
0 (10 HHz) 1 1
1 (6 or 8 MHz)
* 1
(* : don' t care)
WS2 I 39 WaU states control of 16-bit memory devices on
the option card which activates -MEMCS16 signal.
WS3 I 38
CSPD ~VS3 WS2 Wait states
0 (10 ~mz) 0 0 4
0 (10 MHz) 0 1 3
0 (10 MHz) 1 0 2
0 (10 MHz) 1 1 1
1 (6 or 8 MHz) * *
1
(* don't care)
AO I 44
CPU address bus O.
ALE I 11
(+) Address latch enables.
MEMR I 7 (-) System memory read signal.
MEMW I 8 (-) System memory write signal.
IOR I 9 (-) System 1/0 read signal.
IOW I 10 (-) System 1/0 write signal.
INTA I 12 (-) Interrupt acknowledge.
CSRA I 48 (-) Chip select signal of internal DRAM (0­
09FFFF) •
CSRO I 47 (-) Chip select signal of internal ROM (OEOOOO-­
-OFFFFF, FEOOOO-FFFFFF).
M16 I 17 (-) Chip select signal of 16-bit memory devices
on the option siot. (-MEMCS16 signal of option
siot is connected to this pin.)
7-21

DIAGRAMS AN» REFERENCE MATERIALS
REV.A
1016
IRDY
NPCS
CSPD
I
1
1
1
18
61
45
52
(-) Chip select signal of 16-bit 1/0 devices on
the option slot. (-10CS16 signal of option slot
is connected to this pin.)
(+) 1/0 channe] ready signal. (+10CHRDY signa]
of option slot is connected to this pin.)
(-) Chip select signal of numeri cal processor
(80287) •
CPU speed select.
CSPD CPU speed
o 10 MHz
1 6 or 8 MHz
Q1
ARFY
AREN
COFF
LSAO
AEN1
AEN2
DAEN
XAO
XBHE
o
o
o
o
o
1
1
o
Tri
Tri
2
25
16
60
23
43
42
32
49
35
(+) Q1 signal is active from phase 2 of first Tc
cycle to phase 1 of last Tc cycle.
(-) Asynchronous ready.
(-) Asynchronous ready enable.
(+) Control off. This signal becornes active
during 16

REV.A
DIAGRAMS AND
REFERENCE MATERIALS
OUT1
HRQ1
XHW
HRQ
HLDA
HAK1
RFNO
RFNI
RFPO
I
I
I
o
I
o
o
I
o
21
22
46
30
3
31
28
63
24
OUT1 signal of 8254 (Timer LSI)
(+) Hold request input from 8237 (D}~C LSI).
(-) Internal memory write signal.
(+) Hold request output to CPU.
(+) Hold acknowledge input from CPU.
(+) Hold acknowledge output to 8237 (DMAC LSI).
(-) Refresh signal. This signal is generated in
GAATRF.
(-) Refresh signal input.
(+) Refresh signal.
RFlD
RF2D
DMMR
XIOR
DRDY
XMR
CA20
A20G
A20
o
o
I
I
o
O&H-Z
I
I
O&H-Z
37
36
41
50
29
64
34
33
62
(-) Refresh signal which is delayed by one DMA
clock cyc1e from RFNI signal.
(-) Refresh signal which is delayed by two DMA
clock cycles from RFNI signal.
(-) D}~ memory read signal.
(-) Internal 1/0 read signal.
(+) D~~ ready signal.
(-) Internal memory read signal.
CPU address bus 20. A20 signal of CPU is
connected to this pin.
(+) Gate signal of A20. P21 signal of 8042 (one
chip CPU) is connected to this pin.
System address bus 20.
CA20
o
1
*
A20G
1
1
o
A20
o
1
o (* don' t care)
CLK
SCLK
DCLK
I
I
I
51
6
13
Processor clock.
System clock.
DMA c1ock.
CPU speed
6 HHz
8 ~rnz
10 MHz
CLK
12 HHz
16 MHz
20 MHz
SCLK
6 HHz
8 MHz
10 }ffiz
DCLK
3 MHz
4 tffiz
5 HHz
RST
RSTO
TEST
I
o
I
20
19
53
(-) Reset input.
(+) Reset output.
(-) Test input.
* Legend: I
o
Tri
O&H-Z
Input Pin
Output P in
Tri-state Pin (Input, Output, High-impedance)
Output & High-impedance Pin
7-23

DIAGRAMS AND
REFERENCE MATERIALS
HEV.A
7.2.9 GAATSP
GMTSP
includes the follo\ving functional blocks.
1. Address decoder for serial port (DART, 16450 or 8250)
2. Parallel port. (PTDR: printer data register,
PTSR: printer status register,
PTCR: printer control register)
3. Oscillator for DART. (1.8432 MHz output)
4. General purpose 3-state gate.
TABLE 7-2-13.
GAATSP PIN DESCRIPTION
SYMBOL
1/0*
PIN NO.
NAHE AND FDNCTION
SA9-0
SD7-0
IOWN
IORN
AEN
RES
PIFI
PIFO
1
Tri
I
I
I
lS
I
1
13-4
22,24,29,31
54,56,61,63
17
16
14
32
20
21
Address bus
Data bus
(-) 1/0 write pulse.
(-) 1/0 read pulse.
(+) Address enable. This signal becornes high,
when DMA cycle is being executed.
(+) Reset.
Address select pin for parallel port.
Address select pin for parallel port.
PIFI
1
1
o
o
PIFO
1
o
1
o
parallel port address
378, 379, 37A
278, 279, 27A
3BC, 3BD, 3BE
disable
SIFI
SIFO
I
I
18
19
Address select pin for serial port.
Address select pin for serial port.
SIFI
1
1
o
o
SIFO
1
o
1
o
serial port address
3F8 --_. 3FF
2F8 --- 2FF
disable
disable
XTl
XT2
OSC
TSA
TSC
TSY
OD7-0
OSLI
OINl
OATF
o
I
I
O&II-Z
o
o
o
o
51
50
52
48
49
47
23,25,28,30
55,57,60,62
41
43
Crystal input. (3.6864 MHz)
Crystal input. (3.6864 }ffiZ)
1.8432 MHz clock output.
Data input of 3-state buffer.
Control input of 3-state buffer.
Output of 3-state buffer.
Printer data bit 7-0.
(-) Printer select.
(-) Printer initialize.
(-) Auto feed.
7-24

REV.A
DIAGRAMS
AN» REFERENCE MATERIALS
OSTB
SLN
INI
ATF
STB
BSY
ACK
EOP
SLP
ERR
IRQ
OIRE
ACKP
SCSN
DDIR
o
I
I
I
I
I
I
I
I
I
O&II-Z
o
o
o
o
45
38
40
44
46
34
33
35
36
37
15
3
2
53
64
(-) Printer data strobe pulse.
(-) Printer select.
(-) Printer initialize.
(-) Auto feed.
(-) Printer data strobe pulse.
(+) Printer busy.
(-) Acknowledge.
(+) End of paper.
(+) Printer select.
(-) Printer error.
(+) Interrupt request. IRQ becomes active, when
-ACK signal becomes low and interrupt request is
enabled.
(-) Interrupt request enable.
(+) Acknowledge.
(-) Chip select signal of serial port.
(-) Direction control of data buffer. This
signal is active while serial port or parallel
port are being read.
* Legend: I o
Tri
0&11-2
Input Pin
Output P in
Tri-state Pin (Input, Output,
= Output & High-impedance Pin
High-impedance)
7-25

DIAGRAMS AND REFERENCE MATERIALS
REV.A
7 .2 .10 GAATFD
GMTFD
includes the following functional blocks.
1. Address decoder for FDC(765) and 1/0 registers.
2. 1/0 register.
FDOR : Floppy digital output register.
FCR : Floppy control register.
3. Write precompensation circuit.
4. Clock ci.rcuit
5. DMA request circuit.
TABLE 7-2-14.
GAATFD PIK DESCRIPTIOK
SYMBOL 1/0* PIK 1«>.
NAME AND
FUNCTION
BA9-0 I 8-2,64-62
BD5-0 I 14-19
IOWN I 11
IORN I 10
AEN I 9
RSE I 52
FDIl I 46
FDIO I 45
Address bus.
Data bus.
(-) 1/0 write pulse.
(-) 1/0 read pulse.
(+) Address enable. This signal becomes high,
when DMA cycle is being executed.
(+) Reset.
Address select pin for FDC.
Address select pin for FDC.
FDIl FDIO FDC address AT/XT
1 1 3FO 3F7 AT portI
1 0 370 377 AT port2
0 1 3FO 3F7 XT
0 0 disable
(When FDll, FDIO = 0, 1
can not be accessed.)
Floppy control register
MOT2
MOTI
DS2
DSI
FRES
RlvC
3X7N
3XVN
FCSN
BDIR
o
o
o
o
o
o
o
o
o
o
30
29
25
24
49
23
32
47
44
59
(+) Motor enable 2. (DRIVE B)
(+) Motor enable 1. (DRIVE A)
(+) Drive select 2. (DRIVE B)
(+) Drive select 1. (DRIVE A)
(+) FDC (765) reset signal.
(+) Reduced write current.
(-) Read 3X7 signal. This signal becomes active
while 1/0 address 3X7 is read. X means F (when
FDIO=I) or 7 (when FDIO=O)
(-) Chip select of 3X6 and 3X7. This signal
becomes active while 1/0 address 3X6 or 3X7 are
accessed.
(-) Chip select of FDC (765).
(~) Direction control of data buffer. This
signal is active whiJe FDC (765) is being read.
(CPU access or DMA transfer)
7-26

REV.A
DIAGRAMS AND REFERENCE MATERIALS
DREN
DAKN
FDAN
BTC
FTC
FDRQ
DRQ
FWD
WB
PSI
PSü
WD
C48
TEST
MIN
OSC
CLK
WCLK
PINT
SYNC
VDRQ
SIDE
HS
INV
INVN
SEEK
DTKO
TRKO
o
I
o
I
o
I
o
I
I
I
I
o
I
I
o
o
o
o
I
I
o
I
o
I
o
I
I
o
60
12
50
13
42
40
61
35
36
33
34
28
55
38
48
57
54
56
41
43
53
51
22
20
21
37
31
39
(-) Enable DMA and interrupt.
(-) D~~ acknowledge. (input frorn 8237)
(-) DMA acknowledge. (output to 765)
(+) Terminal count. (input frorn 8237)
(+) Terminal count. (output to 765)
(+) D~~ request. (input from 765)
(+) D}~ request. (output to 8237)
(+) Write data. (input from 765)
(+) Write enable. (input from 765)
Peak shift. (input from 765)
Peak shift. (input from 765)
(+) Write data. (output to FDD)
48 MHz clock input.
(-) Test pin.
Mini/Standard. (for SED9420)
16/9.6 MHz clock output. (for SED9420)
FDC dock. (8/4.8/4 ~rnz)
FDC write clock. (IM/600K/500K Hz)
(+) Interrupt request of FDC. (input frorn 765)
VFO synchronize. (input frorn 765)
(+) VFO DREQ. (for SED9420)
(+) Side select. (Head select, input frorn 765)
(+) Head select. (output to FDD)
Input of inverter.
Output of inverter.
(+) Seek. (input from 765)
(+) Track O. (input from FDD)
(+) Track O. (output to 765)
* Legend: I = Input P in
o Output Pin
7-27

DIAGRAMS AHn REFERENCE MATERIALS
REV.A
DIAGNOSTICS PROGRAM
CONTENTS
1. System Board Check .•••..•••.•.....•••••.•• 7-29
2. f';1emory Check............................... 7-38
3. Keyboard Check 7-41
4. Monochrome Display Adapter and CRT Check 7-46
5. Color Graphics Adapter and CRT Check 7-52
6. Floppy Disk Drives and Controller Check ••.. 7-64
7. Math Coprocessor (80287) Check •••••....••.. 7-70
9. Parallel Port (Printer Interface) Check ..•• 7-75
11. Serial Port (RS-232C) Check ••••••••.....•.. 7-78
12. Alternate Serial Port Check................ 7-82
14. Dot-matrix Printer Check 7-83
17. Hard Disk Drives and Controller Check •••.•. 7-85
21. Alternate Parallel Port Check.............. 7-90
7-28

REV .A DIAGRAMS AND REFERENCE MATERIALS
1. System Board Check
This module checks the operation of each IC contained in the
systemboard. The checking operation is performed in the following
order,and the program displays an error message when some error is
detected.If noerror is detected, the program displays no error
message.
1. 80286 Processor check
2. 146818 CMOS shutdown byte check
3. 27256 ROM checksum check
4. 8254 Timer Counter check
5. 8237 DMA Controller check
6. SN74LS612 DMA Page resister check
7. 8237 Memory reflesh check
8. 8042 Keyboard Controller check
9. 80286 instruction check
10. 146818 CMOS checksum and battery check
11. 8259 Interrupt Controller check
12. 8254 Timer Counter speed check
13. 80286 protect mode check
When the system board check is started, the program displays
following message.
+-----------------------------------------------------------------+
I
I
: SYSTEM BOARD CHECK :
I
I
+-----------------------------------------------------------------+
The remainder of this section describes the procedures for
each checking operation.
1) 80286 Processor Check
The 80286 Processor check performs writing and reading checks
on the 80286 flags and segment registers.
a. "Offh" is stored (safh) into the 8080 flag, then re-loaded
(lahf). The flags are checked and it is considered an error
if any of the below flags are not set (if the flag = 0):
CF (Carry Flag)
ZF (Zero Flag)
PF (Parity Flag)
SF (Sign Flag)
AF (Auxiliary Carry-BCD)
I
I
I
I
7-29

DIAGRAMS AND
REFERENCE MATERIALS
REV.A
The error message is as folIows:
+-----------------------------------------------------------------+
I
I
: Error code = 101 l
l 80286 CPU ERROR l
I
I
+-----------------------------------------------------------------+
b. "OOh" is stored (safh) into the 8080 flag, then re-loaded
(lahf). The flags are checked and the program displays an
error message if any of the flags listed in Item a. above are
not reset (if the flag = 1).
The error message is identical to that of Item a.
c. "Oaa55h" is sequentially written to and read from Registers
es, ds, and ss, then their values are checked. The program
displays an error message if the results do not match the
initial values.
The error message is identical to that of Item a.
d. Using "055aah" as the test data, acheck identical to that
described in Item c. is conducted.
The error message is identical to that of Item a.
2) 146818 CMOS Shutdown Byte Check
The 146818 CMOS shutdown byte check performs a WRlTE/READ
check on the shutdown byte of the 146818 CMOS.
a. The shutdown byte of offset 8fh of the CMOS is selected, "01"
is written and read, and the value is checked. The program
displays an error message if the result does not match the
initial value.
+-----------------------------------------------------------------+
I
I
: Error code = 110 :
: 146818 CMOS SHUTDOWN BYTE ERROR :
I
I
+-----------------------------------------------------------------+
b. The test data of Item a. above is shifted to the left, then a
check identical to that described in Item a. is performed for
a11 eight bit s.
The error message is identical to that of Item a.
c. Using "Oaah" as the test data, acheck identical to that
described in Item a. is performed.
The error message is identical to that of Item a.
d. Using "055h" as the test data, acheck identical to that
described in Item a. is performed.
The error message is identical to that of Item a.
I
I
I
I
I
I
I
I
7-30

REV.A DIAGRAMS AND REFERENCE MATERIALS
e. "OOh" is written to the shutdown byte, then this operation is
terminated.
3) 27256 ROM Checksum Check
The 27256 ROM checksum check performs a check on the sum total
of all 27256 ROM data in byte units, then confirms whether or not
that sum equa1s "OOh". The program displays an error message if the
sum does notequal "OOh".
+-----------------------------------------------------------------+
I
I
: Error code = 102 I
: 27256 ROM CHECKSUM ERROR :
I
I
+-----------------------------------------------------------------+
4) 8254 Timer Counter Check
The 8254 Timer Counter check performs acheck of the setting
and reading operation of the counter register of the 8254 Timer
Counter.
Count "0" of the 8254 Timer Counter is 1atched and the count
va1ue is checked. Next, acheck is repeated1y performed to confirm
that all 16 bits have the va1ue of "1". The program displays an
error message ifany bit of the count va1ue of "1" cannot be read.
+-----------------------------------------------------------------+
I
I
: Error code = 103 :
: 8254 TIMER COUNTER REGISTER ERROR l
1 I
I
I
+-----------------------------------------------------------------+
5) 8237 DMA Controller Check
The 8237 DMA Controller check performs a WRITE/READ check on
the eight registers (Port Nos. OOh to 07h) of the first 8237 DMA
Controller and on the eight registers (Port Nos. COh, C2h to CEh)
of the second 8237 DMA Controller.
The test data is used in the sequence of "OOOOh", "5555h",
"Oaaaah", and "Offffh". If an error is detected, the fo11owing
message will be disp1ayed:
+-----------------------------------------------------------------+
I
I
: Error code = 105 I
: 8237 DMA CONTROLLER REGISTER ERROR :
I
I
+-----------------------------------------------------------------+
I
I
I
I
I
I
I
I
I
I
7-31

DIAGRAMS AND REFERENCE MATERIALS
REV.A
6) SN74LS612 DMA Page Register Check
The SN74LS612 DMA Page register check performs a WRITE/READ
check on the 15 registers (Port Nos. 81h to 8Fh) of the SN74LS612
Page Register.
The test data is used in the sequence of "OOh", "SSh", "Oaah",
and "Offh". If an error is detected, the following message will be
displayed:
+-----------------------------------------------------------------+
I
I
: Error code = 106 :
: 612 DMA PAGE REGISTER ERROR l
1 I
I
I
+-----------------------------------------------------------------+
7) 8237 Memory Refresh Check
The 8237 Memory refresh check performs a repeated check on the
refresh detect bit of Port No. 61h, and checks if its status makes
a change.
The program displyas an error message if the status does not
change.
+-----------------------------------------------------------------+
1 I
I
I
: Error code = 105 :
: 8237 DMA REFRESH ERROR l
I
I
I 1
+-----------------------------------------------------------------+
8) 8042 Keyboard Controller Check
The 8042 Keyboard Controller check performs a check on the
operating status of the Keyboard Controller.
a. The status of the Keyboard Controller is repeatedly checked,
and the program displays an error message if its input buffer
is not empty.
+-----------------------------------------------------------------+
I 1
I
I
: Error code = 107 I
: 8042 TIME OUT ERROR :
I
I
+-----------------------------------------------------------------+
b. The Self-test command is output to the Keyboard Controller so
that it will execute a self-diagnostic test. If an error is
detected, the following message will be displayed:
I
I
I
I
7-32

REV.A DIAGRAHS AND REFERENCE MATERIALS
+-----------------------------------------------------------------+
I
I
: Error code = 108 :
: 8042 SELF DIAGNOSTIC ERROR :
I
I
+-----------------------------------------------------------------+
c. The Read Input Code command is output to the Keyboard
Controller, and the program displays an error message if it
does not assume the "Input buffer empty" status.
The error message is identical to that of Item a. above.
d. The Write Keyboard Controller's Command Byte command is
output tothe Keyboard Controller, and the program displays
an error messageif it does not assume the "Input buffer empty
status.
The error message is as foliows:
+-----------------------------------------------------------------+
I
I
: Error code = 108 :
: 8042 WRI TE COMMAND ERROR :
I
I
+-----------------------------------------------------------------+
e. The mode of the Keyboard Controller is reset to the following
modes and this operation is terminated.
PC Compatible Mode
Disable Keyboard
Inhibit Override
System flag
Enable Output-Buffer-Full Interrupt
9) 80826 Instruction Check
The 80826 Instruction check performs a WRITE/READ test on the
System Table Registers IDTR and GDTR as weIl as a SET/RESET test on
the direction flag and interrupt enable flag of the CPU flags.
a. The test data "Oaaaah" is written to and read from IDTR and
GDTR, then their values are checked. The program displays an
error message if the results do not match the initial values.
+-----------------------------------------------------------------+
I
I
: Error code = 113 l
l 80286 INSTRUCTION ERROR :
I
I
+-----------------------------------------------------------------+
b. Using the test data "5555h" and "OOOOh", an identical check
is performed.
The error message is identical to that of Item a. above.
I
I
I
I
I
I
I
I
I
I
I
I
7-33

DIAGRAMS AND
REFERENCE MATERIALS
REV.A
c. "Offffh" is set at IDTR.
d. The direction flag and interrupt enable flag are set using the
STD and STI instructions, and the status of the CPD flags is
checked. It is considered an error if the direction flag and
interrupt enable flag are not set.
The error message is identical to that of Item a.
e. Similarly, the direction flag and interrupt enable flag are
reset using the CLD and CLI instructions, and the status of
the CPD flags is checked.
The error message is identical to that of Item a.
10) 146818 CMOS Checksum and Battery Check
The 146818 CMOS checksum and battery check performs a check on
the battery status of the CMOS and the checksum.
a. The CMOS battery status is read to check if the battery is all
right. If not, the program displys following error message.
+-----------------------------------------------------------------+
I
I
: Error code = 111 :
: 146818 CMOS BATTERY ERROR :
I
I
+-----------------------------------------------------------------+
b. The CMOS shutdown byte is read to check if it is in "Shutdown
OK" status. If so, this operation is terminated here; if not,
execution proceeds to the checking of the checksum.
c. The total sum of the data from CMOS offset 90h to Oadh is
calculated, and the program displys an error message if the
resulting value equals zero.
+-----------------------------------------------------------------+
I
I
: Error code = 112 :
: 146818 CMOS CHECKSUM ERROR :
I
I
+-----------------------------------------------------------------+
d. The total sum of the data from CMOS offset 90h to Oadh is
compared with the checksum value (CMOS offset Oaeh and Oafh),
and the program disp1ys an error message if they do not match.
The error message is identical to that of Item c.
11) 8259 Interrupt Controller Check
The 8259 Interrupt Controller check performs the following
checks on 8259.
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7-34

BEY .A DIAGRAHS AND REFERENCE MATERIALS
a. The masking of all interrupts is reset, then a READ check is
performed on the mask register.
b. The masking of all interrupts is set, then a READ check is
performed on the mask register.
c. Interrupt state of the CPU is enabled in a status where all
interrupts are masked, and the program displays an error
message if an interrupt occurs.
If an error is detected during the above checks, the program
displays following error message:
+-----------------------------------------------------------------+
I
I
: Error code = 109 :
: 8259 INTERRUPT CONTROLLER ERROR :
I
I
+-----------------------------------------------------------------+
12) 8254 Timer Counter Speed Check
The 8254 Timer Counter speed check confirms if the timer is
interrupted within the proper interval.
The interrupt processing routine of 8259A is set to the special
setting, only the Count "0" output of the timer is placed into the
interrupt enable status, and the Count "0" value is checked.
a. Starting with a Count value of 50, it is checked whether an
interrupt occurs during 3memoryrefresh intervals. The
program displays an error message if no interrupt occurs.
+-----------------------------------------------------------------+
I
I
: Error code = 104 :
: 8254 TIMER COUNTER ERROR :
I
I
+-----------------------------------------------------------------+
b. Starting with a Count value of 250, it is checked whether an
interrupt does not occur during 4 memory refresh intervals,
then it is checked whether an interrupt occurs during 6
intervals. If an error detected, the program displays an
error message identical to that of Item a.
13) 80286 Protect Mode Check
The 80286 protect mode check performs a WRITE/READ check on the
80286 protect mode register as weIl as a check on the execution
status of the instructions during protect mode.
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7-35

DIAGRAMS AND
REFERENCE MATERIALS
REV.A
a. The transition into protect mode is checked. The Global
Descriptor table and Interrupt Descriptor table are prepared,
then execution shifts from real mode to protect mode. At this
point, the program displays an error message if the PE bit of
the Machine Status Word does not become "1".
+-----------------------------------------------------------------+
I
I
: Error code = 115 :
: 80286 PROTECT MODE ERROR 2 :
I
I
+-----------------------------------------------------------------+
b. The interruption of protect mode is checked. The program
displays an error message if the interrupt processing routine
set at the Interrupt Descriptor table in protect mode is not
executed within the prescribed time.
The error message is identical to that of Item a.
c. A WRITE/READ check is performed on LDTR (Local Descriptor
table register), and the program displays an error message if
the values do not match.
The error message is identical to that of Item a.
d. A WRITE/READ check is performed on TR (Task register), and the
program displays an error message if the values do not match.
The error message is identical to that of Item a.
e. A SET/RESET check is performed on DF (Direction flag), and the
program displays an error message if the set status and the DF
flag of the CPU do not match.
The error message is identical to that of Item a.
f. A boundary check is performed using the BOUND instruction,
then the absence of an out-of-boundary interrupt (INT 5) is
confirmed by checking the data within boundaries and the
occurrence of an out-of-boundary interrupt is confirmed by
checking the out-of-boundary data.
The error message is identical to that of Item a.
g. The operation of the PUSHA and POPA instructions is checked.
The register values are changed after execution of PUSH A,
POPA is executed, then it is checked whether the register
values prior to PUSHA execution match the respective register
values.
The error message is identical to that of Item a.
h. The operation of the VERR and VERW instructions is checked.
The setting of the Writable bit of the access right byte to
the Descriptor table is checked using the VERR and VERW
instructions, then it is checked whether testing of the
reading access right byte and writing access right byte of
the segments can be properly performed.
The error message is identical to that of Item a.
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7-36

REV.A DIAGRAMS AND REFERENCE MATERIALS
i. The operation of the ARPL instruction is checked. Using the
ARPL instruction, the operation is checked for the case where
the requested privi1ege level is adjustab1e and the case where
it is not adjustab1e.
The error message is identica1 to that of Item a.
j. The operation of the LAR instruction is checked. The access
right byte is loaded using the LAR instruction and is checked
for being the prescribed va1ue. The program displays an error
message if the access right bytecannot be read or if it is
not the prescribed va1ue.
The error message is identica1 to that of Item a.
k. The operation of the LSL instruction is checked. The segment
limit is loaded using the LSL instruction and is checked for
being the prescribed va1ue. The program displays an error
message if the segment limit cannot be read or if it is not
the prescribed va1ue.
The error message is identica1 to that of Item a.
1. A WRITE check is performed on the test data whi1e changing
the segment se1ector. The program displays an error message
if the segment se1ector has not proper1y changed.
+-----------------------------------------------------------------+
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: Error code = 114 :
: 80286 P ROTECT MODE ERROR 1 :
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+-----------------------------------------------------------------+
m. The system is returned to real mode by system reset. The stack
segment and stack pointer are reset, then this checking
operation is terminated.
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DIAGRAMS ARD REFERENCE MATERIALS
REV.A
2 • Memory Check
This module performs a WRITE/READ check on the Ramdom Access
Memory (RAM) in block units (1 block = 64 KB). The remainder of
this section describes the procedures for each checking operation.
1) 64 KB Check of "OOOOOh" - "OFFFFh"
a. The contents of "OOOOOh" - "OFFFFh" are evacuated to
"20000h" - "2FFFFh".
b. The test data, "55aah", is written to the entire 64KB area,
the 1/0 check and RAM Parity check are enabled, then a VERIFY
check and parity check are performed.
If an error is detected, the program displays following error
message:
+-----------------------------------------------------------------+
I
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: Error code = 201 :
: xxxxx yyyy zzzzzz ERROR :
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+-----------------------------------------------------------------+
(xxxxx represents the absolute address where the error detected,
yyyy represents the error data [any bit that is not "I"], and
zzzzzz is either "PARITY" in case of a parity error or "MEMORY" in
case ofa VERIFY error.)
c. Using "Oaa55h" as the test data, acheck identical to that of
Item b. is performed.
d. Using "010Ih" as the test data, acheck identical to that of
Item b. is performed.
e. The test data, "5555h" and "Oaaaah", is written sequentially
to the entire 64 KB area, then a parity check is performed.
Next, the test data is read and a VERIFY check is performed.
The test data "OOOOh" is written and a parity check is
concurrently performed.
f. The test data "OFFFFh" is written to the leading and trailing
words of the 64 KB block and test data "OOOOh" is written to
the other words. Next, the test data is read, then a VERIFY
check and parity check are performed.
g. If the check of the 64 KB block is normally terminated, the
contents of "20000h" - "2FFFFh" are re-written to "OOOOOh" ­
"OFFFFh".
h. Next, a message indicating the completion of the first 64 KB
block check is displayed on the screen.
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7-38

HEV.A DIAGRAMS AND REFERENCE MATERIALS
+---------------------------------_._---------------------~--------+
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: 000064 KB OK :
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+-----------------------------------------------------------------+
2) 64 KB Check of "10000h" - "1FFFFh"
a. The contents of "10000h" - "1FFFFh" are evacuated to "30000h"
- "3FFFFh".
b. to f. A RAM check identical to that of Item 1) is performed.
g. If the check of the 64 KB block is normally terminated, the
contents of "30000h" - "3FFFFh" are re-written to "10000h" ­
"1FFFFh".
h. Next, a message indicating the completion of the second 64 KB
block check is displayed on the screen.
+-----------------------------------------------------------------+
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: 000128 KB OK :
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+-----------------------------------------------------------------+
3) 64 KB Check of "20000h" - "2FFFFh"
a. The contents of "20000h" - "2FFFFh" are evacuated to "30000h"
- "3FFFFh".
b. to f. A RAM check identical to that of Item 1) is performed.
g. If the check of the 64 KB block is normally terminated, the
contents of "30000h" - "3FFFFh" are re-written to "20000h" ­
"2FFFFh".
h. Next, a message indicating the completion of the third 64 KB
block check is displayed on the screen.
+-----------------------------------------------------------------+
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: 000192 KB OK :
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I
+-----------------------------------------------------------------+
4) 64 KB Block Check of Address "30000h" and Onward
The CMOS settings are read, the highest RAM address is
calculated, then a RAM check identical to Item 1) is performed in
64 KB units up to that highest address.
Each time a 64 KB check is completed, the program displays
following message.
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7-39

DIAGRAHS AND
REFERENCE MATERIALS
REV.A
+-----------------------------------------------------------------+
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: XXXXXX KB OK :
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+-----------------------------------------------------------------+
(The XXXXXX represents the total size of the checked memory block.)
5) Lastly, a parity check is performed by word unit. Each time a
64 KB check is completed, the program displays following message.
+-----------------------------------------------------------------+
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: XXXXXX KB OK :
I
I
+-----------------------------------------------------------------+
(The XXXXXX represents the total size of the checked memory block.)
NOTE:The base memorysize is checkedusing int 12h.The expansion
memory size is checked by reading CMOS offset 30h and 31h.
In case an expanded memory is installed, the memory check is
performed in protect mode of 80286.
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7-40

REV .A DIAGRAKS AND REFERENCE MATERIALS
3. Keyboard Check
This module checks the operating status of the keyboard as well
as the input of each key. The remainder of this section describes
the checking procedures.
(In case of test multiple times, only keyboard function check is
performed.)
1) Keyboard Function Check
a. The keyboard is read without pressing any keys, and the
program displays an error message if the input status is not
empty.
+-----------------------------------------------------------------+
I
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: Error code = 301 l
: 8042 ERROR :
I
I
+-----------------------------------------------------------------+
b. The self-test command is output to the keyboard. The program
displays an error message if the Normal Termination code is
not returned.
+-----------------------------------------------------------------+
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: Error code = 301 :
: 8042 ERROR :
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I
+-----------------------------------------------------------------+
c. The interface test command is output to the keyboard. The
program displays an error message if the Normal Termination
code is not returned.
+-----------------------------------------------------------------+
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: Error code = 301 :
: KEYBOARD ERROR :
I
I
+-----------------------------------------------------------------+
d. The keyboard functions are disabled, then the response from
the keyboard is checked. The program displays an error
message if the keyboard is in data ON status with the keyboard
clock in OFF status. The error message is identical to that
of Item c.
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7-41

DIAGRAMS AND REFERENCE MATERIALS HEV.A
e. The keyboard functions are enabled, then the reset command is
output to the keyboard. The program displays an error message
in case there is no ACK response or in case the resetting
generates a BAT Completion code. The error message is
identical to that of Item c.
2) Keyboard Lock Check
a. First, determine whether or not to check the keyboard lock.
+-----------------------------------------------------------------+
I
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: Do you wish to check the keyboard lock (Y/N)? :
I
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+-----------------------------------------------------------------+
When "Y" is input after the prompt, the keyboard lock check is
executed. When "N" is input, the keyboard lock check is not
performed.
b. When the keyboard lock check is begun, the following message
is displayed, so insert the key into the front panel and turn
it to lock the keyboard.
+-----------------------------------------------------------------+
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: Lock the keyboard using the front-panel key :
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+-----------------------------------------------------------------+
The program displays an error message if the keyboard is not
locked within the prescribed time.
+-----------------------------------------------------------------+
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l Error code = 303 :
: KEYBOARD LOCKING ERROR :
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+-----------------------------------------------------------------+
c. When the keyboard becomes locked, the following message is
displayed, so turn the front-panel key to unlock the keyboard.
+-----------------------------------------------------------------+
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: Unlock the keyboard :
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+-----------------------------------------------------------------+
The program displays an error message if the keyboard is not
unlocked within the prescribed time. The error message is
identical to that of Item b.
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7-42

REV.A
DIAGRAMS AND REFERENCE MATERIALS
3)
Keyboard Input Check
First of all, select the keyboard type according to country.
+-----------------------------------------------------------------+
KEYBOARD
SELECT MENU
1 - US ASCII
2 - United Kingdom
3 - French
4 - German
5 - Italian
6 - Spanish
o - Exit
Enter selection number:
+-----------------------------------------------------------------+
When the keyboard type is selected, the OF2h command code is
output to the connected keyboard, and the keyboard is judged as
being of old type (89 keys) or new type (101 or 102 keys) by its
response.
+------------------+-------------------------------+
I Response I Keyboard Type :
+------------------+-------------------------------+
: only ACK I Old type (89 keys) :
: ACK, ABh, 41h I New type (101 or 102 keys) :
+------------------+-------------------------------+
The keyboard layout corresponding to the judged keyboard type
is displayed. By pressing an arbitrary key, the character
corresponding to the pressed key top will be displayed on the
screen.
When "y" and ENTER is input, the check is normally terminated.
If "N" and ENTER is input in the case that the pressed key top and
the displayed character are different, the program displays
following message:
+-----------------------------------------------------------------+
KEYBOARD
CHECK
Error code = 302
KEYBOARD IS NON-STANDARD, OR
KEYBOARD IS DEFECTIVE.
+-----------------------------------------------------------------+
7-43

DIAGRAMS AND
REFERENCE MATERIALS
HEV.A
REMARK: During the keyboard input check, the interrupt vector of
keyboard input is rewritten, the scan code of the keyboard
is directly read, then the corresponding character is
displayed.
a. Layout of old-type keyboard
+-----------------------------------------------------------------+
KEYBOARD
CHECK
Press Y followed by ENTER to exit.
Press N followed by ENTER if screen andkeyboard do not match.
+-----------------------------------------------------------------+
b. Layout of new-type (lOl-key) keyboard
+-----------------------------------------------------------------+
KEYBOARD
CHECK
Press Y followed by ENTER to exit.
Press N followed by ENTER if screen andkeyboard do not match.
+-----------------------------------------------------------------+
7-44

REV .A
DIAGRAMS AN» REFERENCE MATERIALS
c. Layout of new-type (102-key) keyboard
+-----------------------------------------------------------------+
KEYBOARD
CHECK
Press Y followed by ENTER to exit.
Press N followed by ENTER if screen andkeyboard do not match.
+-----------------------------------------------------------------+
7-45

DIAGRAKS AND
REFERENCE MATERIALS
HEV.A
4. Monochrome Display Adapter and CRT Check
This module checks the monochrome display and its adapter.
First, select which check to perform from the menu.
+-----------------------------------------------------------------+
MONOCHROME ADAP TER AND CRT CHECK MENU
1 - Monochrome adapter check
2 - Attribute check
3 - Character set check
4 - Video check
5 - Sync check
6 - Run all above checks
o - Exit
Enter selection number:
+-----------------------------------------------------------------+
(In case of test multiple times, only the monochrome adapter check
is performed.)
The remainder of this section describes each of the checking
procedures.
1) Monochrome Adapter Check
When the monochrome adapter check is selected, the program
displays following message:
+-----------------------------------------------------------------+
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: MONOCHROME ADAP TER CHECK :
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+-----------------------------------------------------------------+
a. A WRlTE/READ check is performed on the VRAM area used for the
monochrome display.
i) The Video Enable signal of the monochrome monitor is set to
OFF. Next, the test data "OOh" is written to and read from
the entire VRAM area ("BOOOOH" - "BOFAOH"), and a comparison
check is performed.
If the compared data do not match, the program displays
the address generating the mismatch, the written data, and
the read data.
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7-46

REV.A DIAGRAMS AND REFERENCE MATERIALS
+-----------------------------------------------------------------+
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: Error code = 401 :
: V-RAM ERROR address BOOOH:XXXX :
: write data YY read data ZZ :
I
I
+-----------------------------------------------------------------+
(XXXX represents the VRAM offset address that generated the
mismatch, YY represents the written data, and ZZ represents the
read data.)
ii) Next, using the test data "55h" , an identical check is
performed.
iii) Next, using the test data "Oaah", an identical check is
performed.
iv) Next, using the test data "Offh", an identical check is
performed.
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I
Lastly, "OOh" is written to the entire VRAM
area.
b. Black/White mode check of CRT status port
The Video Enable signal of the monochrome monitor is set to
ON status, then the program displays following message:
+-----------------------------------------------------------------+
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: MONOCHROME ADAPTER CHECK :
I
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+-----------------------------------------------------------------+
Next, "Offh" is written to the latter half of the VRAM area
("B07DOH" - "BOFAOH") for the monochrome display, and the CRT
status port of 6845 is checked.
A Black/White Video signal that changes to "1" from "0" is
normal. The program displaysfollowing error message if the
Black/White Video signal remains "0" (LOW) or "1" (HIGH):
+-----------------------------------------------------------------+
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: Error code = 402 :
: VIDEO SIGNAL ALWAYS LOW :
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+-----------------------------------------------------------------+
or
+-----------------------------------------------------------------+
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: Error code = 402 :
: VIDEO SIGNAL ALWAYS HIGH :
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+-----------------------------------------------------------------+
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7-47

DIAGRAMS AND
REFERENCE MATERIALS
REV.A
Lastly, "OOh" is written to the latter half C"B07DOH" ­
"BOFAOH") of the VRAM area and this check is terminated.
2) Attribute Check
When the attribute check is selected, the various types of
attributes that can be displayed are shown on the monochrome
display using characters.
+-----------------------------------------------------------------+
ATTRIBUTE CHECK
NORMAL INTENSITY
HIGH INTENSITY
BLINKING
REVERSE
UNDERLINED
Is the display correct CY/N)?
+-----------------------------------------------------------------+
Confirm whether each attribute is accurately displayed, then
input the answer.
If "N" is input, the program displays an errormessage.
+-----------------------------------------------------------------+
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: Error code = 403 :
: ATTRIBUTE ERROR :
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+-----------------------------------------------------------------+
3) Character Set Check
When the character set check is selected, the entire character
set from "OOh" to "Offh" is displayed on the screen.
Confirm whether the character set is accurately displayed, then
input the answer.
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7-48

REV.A
DIAGRAHS AN» REFERENCE MATERIALS
+-----------------------------------------------------------------+
CHARACTER SET CHECK
( All character set )
1s the display correct (Y/N)?
+-----------------------------------------------------------------+
1f "N" is input, an error message is displayed.
+-----------------------------------------------------------------+
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: Error code = 404 i
i CHARACTER SET ERROR :
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+-----------------------------------------------------------------+
4) Video Check
When the video check is selected, the following screen is
initially displayed with a high-intensity foreground color and a
black background color:
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7-49

DIAGRAMS AND REFERENCE MATERIALS
HEV.A
+-----------------------------------------------------------------+
BLACK
+-----------------------------------------------------------------+
When any key is pressed, the following screen is displayed
with a black foreground color and a high-intensity background color:
+-----------------------------------------------------------------+
INTENSIFIED WHITE
+-----------------------------------------------------------------+
Pressing any key terminates this operation.
7-50

REV .A DIAGRAMS AND REFERENCE MATERIALS
5) Sync Check
When the sync check is selected, the following screen is
displayed. Check this screen for any discrepancies in the
synchronization of all lines.
+-----------------------------------------------------------------+
+-----------------------------------------------------------------+
6) Run All Above Checks
When "Run all above checks" is selected, the checks described
in Items 1) to 5) are consecutively executed.
7-51

DIAGRAMS AB» REFERENCE MATERIALS
REV.A
5. Color Graphics Adapter and CRT Check
This module checks the color display and its adapter.
First, select which check to perform from the menu.
+-----------------------------------------------------------------+
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COLOR GRAPHICS ADAPTER AND CRT CHECK MENU
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1 - Color graphics adapter check
2 - Attribute check
3 - Character set check
4 - 40-column character set check
5 - 320X200 graphics mode check
6 - 640X200 graphics mode check
7 - Screen paging check
8 - Light pen check
9 - Color video check
10 - Sync check
11 - Run all above checks
o - Exit
Enter selection number:
+-----------------------------------------------------------------+
(In case of test multiple times, only the color graphics adapter
check is performed.)
The remainder of this section describes each of the checking
procedures.
1) Color Graphics Adapter Check
When the color graphics adapter check is selected, the program
displays following message:
+-----------------------------------------------------------------+
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: COLOR ADAP TER CHECK :
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+-----------------------------------------------------------------+
At this point, a WRITE/READ check is performed on the VRAM
area used for color graphics.
a. The Video Enable signal of color graphics is set to OFF. Next,
the test data "OOh" is written to and read from the entire
VRAM area ("B8000H" - "B9F3FH" and "BAOOOH" - "BBF3FH") used
for color graphics, and a comparison check is performed.
If the compared data does not match, the program displays the
address generating the mismatch, the written data, and read
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REV.A
DlAGRAHS AHn REFERENCE MATERIALS
data.
+-----------------------------------------------------------------+
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: Error code = 501 :
: V-RAM ERROR address B800H:XXXX :
: write data YY read data ZZ :
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+-----------------------------------------------------------------+
(XXXX represents the address generating the mismatch, YY represents
the written data, and ZZ represents the read data.)
b. Next, using the test data "SSh", an identical check is
performed.
c. Next, using the test data "Oaah", an identical check is
performed.
d. Next, using the test data "Offh", an identical check is
performed.
Lastly, "OOh" is written to the entire VRAM area, the Video
Enable signal is set to ON, and this check is terminated.
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DIAGRAMS AN» REFERENCE MATERIALS
REV.A
2) Attribute Check
When the attribute check is selected, the various types of
attributes that can be displayed using color graphics are shown
using characters. (40 x 25 character mode)
+-----------------------------------------------------------------+
I
ATTRIBUTE CHECK
HIDRHAINTElIßJlnTY
BLINKING
BLACK
BLUE
GREEN
CYAN
RED
MAGENTA
BROWN
WHITE
GRAY
LIGHT BLUE
LIGHT GREEN
LIGHT CYAN
LIGHT RED
LIGHT MAGENTA
YELLO\'1
WHITE (High intensity)
Is the display correct (Y/N)?
+-----------------------------------------------------------------+
Confirm whether each attribute is accurately displayed, then
input the result. (The display has returned to the 80 x 25
character mode.)
If "N" is input, the program displays an error message.
+-----------------------------------------------------------------+
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: Error code = 503 :
: ATTRIBUTE ERROR :
I
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+-----------------------------------------------------------------+
3) Character Set Check
When the character set check is selected, the entire character
set from "OOh" to "Offh" is displayed on the screen.
Confirm whether the character set is accurately displayed,
then input the answer.
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REV.A DIAGRAMS AND REFERENCE MATERIALS
+-----------------------------------------------------------------+
CHARACTER SET CHECK
( All character set )
1s the display correct (Y/N)?
+-----------------------------------------------------------------+
1f "N" is input, the program displays an error message.
+-----------------------------------------------------------------+
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: Error code = 504 :
: CHARACTER SET ERROR :
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+-----------------------------------------------------------------+
4) 40-Column Character Set Check
When the 40-column character set check is selected, the entire
character set from "OOh" to "Offh" is displayed on the screen in
40-column mode.
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DIAGRAMS
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REV.A
+-----------------------------------------------------------------+
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40-COLUMN CHARACTER SET CHECK
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( All character set in 40-column mode )
1s the display correct (Y/N)?
+-----------------------------------------------------------------+
1f "N" is input, the program displays an error message.
+-----------------------------------------------------------------+
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: Error code = 505 :
: 40-COLUMN CHARACTER SET ERROR :
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+-----------------------------------------------------------------+
5) 320 x 200 Graphics Mode Check
When the 320 x 200 graphics mode check is selected, the
following image pattern is displayed on the screen.This screen
has been created by writing directly to VRAM. (Color setting = "0")
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REV.A DIAGRAMS AND REFERENCE MATERIALS
+-----------------------------------------------------------------+
320X200 GRAPH1CS MODE
COLOR SET 0
CHECK
+----------------+ +-----------------+
GREEN
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+-----------------+
RED
+------------- --------------+
BROWN
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+-----------------+
1s the display correct (Y/N)?
CYAN
+-----------------------------------------------------------------+
Confirm whether the pattern is accurately displayed, then
input the answer.
1f "N" is input, the program displays an error message.
+-----------------------------------------------------------------+
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: Error code = 506 :
: 320X200 GRAPHICS MODE ERROR :
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+-----------------------------------------------------------------+
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DIAGRAMS AND REFERENCE MATERIALS HEV.A
Next, change the color setting to "1" to display the same
image pattern on the screen.
+-----------------------------------------------------------------+
320X200 GRAPH1CS MODE
COLOR SET 1
CHECK
+----------------+ +-----------------+
CYAN
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+-----------------+
MAGENTA
+------------- --------------+
WHITE
1s the display correct (Y/N)?
+-----------------+ RED
+-----------------------------------------------------------------+
Confirm whether the pattern is accurately displayed, then
input the answer.
1f "N" is input, the program displays an error message.
+-----------------------------------------------------------------+
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: Error code = 506 :
: 320X200 GRAPH1CS MODE ERROR :
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+-----------------------------------------------------------------+
6) 640 x 200 Graphics Mode Check
When the 640 x 200 graphics mode check is selected, the
following image pattern is displayed on the screen. This screen
has been created by writing directly to VRAM. (High-resolution mode)
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7-58

REV.A
DIAGRAMS AHn REFERENCE MATERIAL~
+-----------------------------------------------------------------+
640X200 GRAPH1CS MODE
CHECK
+----------------+ +-----------------+
(a)
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+-----------------+
(b)
+------------- --------------+
(c)
+-----------------+
1s the display correct (Y/N)?
+-----------------------------------------------------------------+
(a) Coarse stripes (b) Fine stripes (c) Completely filled
Confirm whether the pattern is accurately displayed t then input
the answer.
1f "N" is input t the program displays an error message.
+-----------------------------------------------------------------+
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: Error code = 507 :
l 640X200 GRAPH1CS MODE ERROR :
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+-----------------------------------------------------------------+
7) Screen Page Check
When the screen page check is selected t the characters "0" ­
"7" are respectively written to Pages 0 - 7 t then the screen paging
according to the changing of pages is checked.
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DIAGRAMS AND
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+-----------------------------------------------------------------+
SCREEN PAG1NG
CHECK
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX (a) XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Press any key for next page
+-----------------------------------------------------------------+
(a) The numeral corresponding to each page no. is displayed.
After completing the check up to Page 7, confirm whether the
screen paging was accurately displayed, then input the answer.
+-----------------------------------------------------------------+
SCREEN P AG1NG
CHECK
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX (a) XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
1s the display correct (Y/N)?
+-----------------------------------------------------------------+
1f "N"
is input, the program displays an error message.
7-60

HEV.A DIAGRAMS AND REFERENCE MATERIALS
+-----------------------------------------------------------------+
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: Error code = 508 :
: SCREEN P AGING ERROR l
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+-----------------------------------------------------------------+
8) Light P en Check
When the light pen check is selected, you must next specify
whether or not to actually perform the check.
+-----------------------------------------------------------------+
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: LIGHT P EN CHECK l
: Enter Y to start light pen check. :
l Enter N to return to the menu. :
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+-----------------------------------------------------------------+
Next, a white block is displayed on the the screen, so press
the light pen on the center of each block. The address that is
read from light pen is checked.
+-----------------------------------------------------------------+
+---+
: c i
+---+
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+---+
l b
i
+---+
+---+
: a :
+---+
PLACE LIGHT PEN ON
CENTER OF WHITE BLOCK
+-----------------------------------------------------------------+
Check the three blocks in the order of a - b - c.
The program displays an error message if the position where the
block is displayed and the light pen position do not match.
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DIAGRAMS AN» REFERENCE MATERIALS
REV.A
+-----------------------------------------------------------------+
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: Error code = 509 :
: LIGHT PEN ERROR :
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+-----------------------------------------------------------------+
9) Color Video Check
When the color video check is selected, the display of the
background color is changed in the sequence below:
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1. Black
2. Blue
3. Green
4. Cyan
5. Red
6. Magenta
7. Brown
8. White
9. Gray
10. Light blue
11. Light green
12. Light cyan
13. Light red
14. Light magenta
15. Yellow
16. White (high intensity)
After all of the background colors are displayed, confirm
whether they have been accurately displayed then input the answer.
+-----------------------------------------------------------------+
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: Is the display correct (Y/N)? :
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+-----------------------------------------------------------------+
If "N" is input, the program displays an error message.
+-----------------------------------------------------------------+
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: Error code = 510 l
: COLOR VIDEO ERROR :
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+-----------------------------------------------------------------+
10) Sync Check
When the sync check is selected, the following screen is
displayed. Check this screen for any discrepancies in the
synchronization of all lines.
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HEV.A DIAGRAMS AN» REFERENCE MATERIALS
+-----------------------------------------------------------------+
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+-----------------------------------------------------------------+
11) Run All Above Checks
When "Run all above checks" is selected, the checks described
in Items 1) to 10) are consecutively executed.
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DIAGRAMS
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KEV.A
6. Floppy Disk Drives and Controller Check
This module checks the floppy disks and floppy disk drives.
First, select which check to perform from the menu.
+-----------------------------------------------------------------+
I
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FLOPPY DISK DRIVE(S) AND CONTROLLER CHECK MENU
1 - Sequential seek check
2 - Random seek check
3 - Write, read check
4 - Speed check
5 - Disk change check
6 - Run all above checks
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o - Exit
Enter selection number:
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+-----------------------------------------------------------------+
(In case of test multiple times, the following checks are
consecutively performed.)
+-----------------------------------------------------------------+
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: 1 - Sequencial seek check :
: 2 - Random seek check :
: 3 - Write, read check :
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+-----------------------------------------------------------------+
The remainder of this section describes each of the checking
procedures.
1) Sequential Seek Check
Initially, the number of floppy disk drives installedis
checked by using Equipment Determination (int 11h). The program
displays following message if two drives are installed, so input
the name of the drive to be checked:
+-----------------------------------------------------------------+
I
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: Check which drive (AlB)? :
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+-----------------------------------------------------------------+
The sequential seek check sequentially searches from the
cylinder position of the innermost periphery to that of the outermost
periphery for the head, then checks the seek operation. This check
is performed with respect to Head "0" and "1".
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REV.A DIAGRAMS ARD REFERENCE MATERIALS
+-----------------------------------------------------------------+
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: SEQUENTIAL SEEK CHECK :
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: Current track is xxxx :
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+-----------------------------------------------------------------+
(The xxxx represents the number of the sought cylinder.)
The program displays an error message if the Floppy Disk
Controller (FDC) assumes one of the following statuses:
1. The FDC main status remains BUSY.
2. The FDC is not in Output Ready status when the program
going to output a command.
3. The FDC is not in Input Ready status when the program going
to input status.
+-----------------------------------------------------------------+
I
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: FLOPPY DISK DRIVE(S) AND CONTROLLER CHECK :
: Error code = 601 :
: FLOPPY DISK CONTROLLER ERROR :
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+-----------------------------------------------------------------+
The program displays an errormessage also when the seek
operation of the FDC after performing head seek is not normally
terminated.
+-----------------------------------------------------------------+
FLOPPY DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 602
SEQUENTIAL SEEK ERROR
TRACK -- xx
SIDE --- Y
+-----------------------------------------------------------------+
(xx represents the error cylinder number and y representsthe error
head number.)
2) Random Seek Check
The random seek checking procedure is identical to that of
Item 1), except for the procedure that the seek operation is
performed in randominstead of sequentially.
The messages are also identical except that "SEQUENTIAL SEEK"
is replaced by "RANDOM SEEK". (Error code = 603)
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DIAGRAHS AND REFERENCE MATERIALS
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3) WRITE/READ Check
The drive is selected as in Item 1). When a drive is
selected, precautions pertaining to the start of the check
operation are displayed.
+-----------------------------------------------------------------+
Use only a formatted blank diskette for this test.
Any data present may be erased.
If using drive A,
remove your Diagnostic Disk.
Enter Y to start this check.
Enter N to return to the menu.
+-----------------------------------------------------------------+
The WRITE/READ ;heck is performed by writing and reading Head
Nos. "0" and "1", alternately, to and from for all sectors of each
cylinder, from the innermost cylinder to the outermost cylinder [0].
The check data is "6db6h".
+-----------------------------------------------------------------+
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I 1
: WRI TE, READ CHECK :
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: Current track is xx :
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I 1
+-----------------------------------------------------------------+
(The xx represents the number of the checked cylinder.)
If an error is detected during the writing or reading of data,
the program displays following message:
+-----------------------------------------------------------------+
FLOPPY DISK DRIVE(S) AND
Error code = 604
WRITE ERROR
TRACK xx
SECTOR - Y
SIDE --- z
CONTROLLER CHECK
+-----------------------------------------------------------------+
(xx represents the error cylinder number, y represents the error
sector number, and z represents the error head number.)
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REV.A DIAGRAMS ARD REFERENCE MATERIALS
+-----------------------------------------------------------------+
I
FLOPPY DISK DRIVE(S) AND CONTROLLER CHECK
Error code = 605
READ ERROR
TRACK -- xx
SECTOR - Y
SIDE --- z
+-----------------------------------------------------------------+
(xx represents the error cylinder number, y represents the error
sector number, and z represents the error head number.)
4) Speed Check
The drive is selected as in Item 1). The speed check performs
60 times one-sector reading operationsof Sector 1 of Cylinder
No.32, Head No. 0, and the program measuresthe time for this
operation using the Channel 0 of 8254.
Measurement is performed by counting the 8254 interrupt, which
occurs every 1/18 second, and correcting by adding the number of
the final Timer Count value. Finally the program displays the
revolution speed in rpm (revolution per minutes).
expression:
(60 [times])/(interrupt count)*(18 [sec/times])*(60 [sec])
+-----------------------------------------------------------------+
The disk rotation speed should be more than xxx.x rpm and
less than yyy.y rpm
The disk rotation speed is now zzz.z rpm
Press any key to return to the menu
+-----------------------------------------------------------------+
(xxx.x represents the lower-limit revolution value, yyy.y represents
the upper-limit revolution value, and zzz.z represents the current
revolution value.)
The lower-limit revolution value is 294.0 for 360 KB drive and
720 KB (3.5"), 352.8 for 1.2 MB. (Normal revolution value - 2%.)
And the upper-limit revolution value is 306.0 for 360 KB drive and
720 KB (3.5"), 367.2 for 1.2 MB. (Normal revolution value + 2%.)
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DIAGRAHS AND
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HEV.A
If a floppy disk is not installed or a read error is detected,
the program displays following message:
+-----------------------------------------------------------------+
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: Disk is defective or not installed properly. :
: Press ENTER to return to the menu. :
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+-----------------------------------------------------------------+
5) Disk Change Check
The drive selection is identical to that of Item 1). The disk
change check can only be performed for 1.2 MB and 720 KB drives.
The program performs read DASD type command of int 13h to confirm
whether the specified drive is change line available or not.
Ifthedriveisno change line available,theprogram
displays following message, allowing you to return to the menu.
+-----------------------------------------------------------------+
Drive X is no change line available.
DISK CHANGE is not allowed with this drive.
Press ENTER to return to the menu.
+-----------------------------------------------------------------+
(The X represents the drive name of the specified floppy disk.)
If the drive is change line available, the program displays
following message, then remove the disk from the drive:
+-----------------------------------------------------------------+
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: Remove the disk from drive X. :
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+-----------------------------------------------------------------+
(The X represents the drive name of the specified floppy disk.)
If the floppy disk is not removed within the prescribed time,
the program displays following error message:
+-----------------------------------------------------------------+
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: Error code = 606 :
: DISK CHANGE CHECK :
: REMOVE ERROR :
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+-----------------------------------------------------------------+
When the floppy disk is removed, the program displays following
message, then re-insert the disk into the drive:
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REV.A DIAGRAMS AND REFERENCE MATERIALS
+-----------------------------------------------------------------+
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: Re-insert the disk into drive X. :
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+-----------------------------------------------------------------+
(The X represents the drive name of the specified floppy diskJ
If the floppy disk is not re-inserted within the prescribed
time, the program displays following error message:
+-----------------------------------------------------------------+
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: Error code = 607 I
: DISK CHANGE CHECK :
: INSERT ERROR :
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+-----------------------------------------------------------------+
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REMARKS:
The disk change check reads the Digital Input Register of
the FDC, then checks the disk change flag of Bit 7.
6) Run All Above Checks
When "Run all above checks" is selected, the checks described
in Items 1) through 5) are consecutively executed.
7-69

DIAGRAHS AND
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7. Katb Coprocessor Check (80287)
This module checks the mathematic coprocessor (80287).
When this module is called, the following message is displayed:
+-----------------------------------------------------------------+
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: 80287 COPROCESSOR TEST :
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+-----------------------------------------------------------------+
1) Coprocessor Installation Check
a. CMOS RAM Setting Check
First, Equipment Determination of int Ilh is called to check
whether or not the coprocessor is installed.
If the the coprocessor not installed, the program displays
following error message:
+-----------------------------------------------------------------+
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: Error code = 701 :
: COPROCESSOR NOT INSTALLED :
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+-----------------------------------------------------------------+
b. Check by Initialization
The Initialize instruction (finit) is output to the
coprocessor, then the status word of the coprocessor is read
(fstsw) to check the installation status.
If all error bits are not read as "0", the program displays
following error message:
+-----------------------------------------------------------------+
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: Error code = 701 :
: COPROCESSOR NOT INSTALLED :
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+-----------------------------------------------------------------+
2) Initialization Check of Coprocessor
The Initialize instruction (finit) is output to the
coprocessor, then the status word of the coprocessor is read (fstsw)
to check the initialization status.
If the all error bits are not read as "0" with BUSY = "0" and
ST = "0", the program displays fo11owing error message:
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REV.A DIAGRAMS AND REFERENCE MATERIALS
+-----------------------------------------------------------------+
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: Error code = 702 :
: COPROCESSOR INITIALIZE ERROR :
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+-----------------------------------------------------------------+
3) Invalid Operation Mask Check (1)
All exceptional interrupts of the coprocessor are masked, then
operation is performed with an empty register to generate a stack
underflow.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:
+-----------------------------------------------------------------+
I
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: Error code = 703 :
: COP ROCESSOR INVALID OPERATION MASK ERROR :
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+-----------------------------------------------------------------+
4) Invalid Operation Mask Check after Clearing of Exceptional Bits
All exceptional bits are cleared (fclex), then processing
identical to that of Item 3) is performed.
At this time, if the IR bit of the status word of the
coprocessor is "1", the program displays following error message:
+-----------------------------------------------------------------+
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: Error code = 703 :
: COPROCESSOR INVALID OPERATION MASK ERROR :
I
I
+-----------------------------------------------------------------+
5) ST Field Check
Two items of integer data are loaded (fild) and added (fadd).
At this time, if the ST field value of the status word of the
coprocessor is "6", the program displays following error message:
+-----------------------------------------------------------------+
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: Error code = 704 :
: COPROCESSOR ST FIELD ERROR :
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+-----------------------------------------------------------------+
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DIAGRAMS AN» REFERENCE MATERIALS
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6) Exceptional Data Comparison Check (1)
The data from the stack underflow status of Item 3) is compared
with"l"(fcom), iftheydo notmatch, theprogramdisplays
following error message:
+-----------------------------------------------------------------+
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: Error code = 705 :
: COPROCESSOR COMP ARISON ERROR :
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+-----------------------------------------------------------------+
7) Zero Division Mask Check
All exceptional interrupts of the coprocessor are masked, then
"1" is divided by "0" to generate a zero divide exception.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:
+-----------------------------------------------------------------+
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: Error code = 706 :
: COPROCESSOR ZERO DIVIDE MASK ERROR :
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+----------------------------------------~------------------------+
8) Exceptional Data Addition Check
The data items from Item 7) that resulted in zero division are
added together.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:
+-----------------------------------------------------------------+
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: Error code = 707 :
: COPROCESSOR ADDITION ERROR :
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+-----------------------------------------------------------------+
9) Exceptional Data Subtraction Check
The data items from Item 7) that resulted in zero division are
subtracted from each other.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:
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REV.A DIAGRAMS AND REFERENCE MATERIALS
+-----------------------------------------------------------------+
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: Error code = 708 :
: COP ROCESSOR SUBTRACTION ERROR :
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+-----------------------------------------------------------------+
10) Exceptional Data Multiplication Check
The data from Item 7) that resulted in zero division is
multiplied by "0".
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "I", the program displays following error
message:
+-----------------------------------------------------------------+
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: Error code = 709 :
: COPROCESSOR MULTIPLICATION ERROR :
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+-----------------------------------------------------------------+
11) Invalid Operation Mask Check (2)
All exceptional interrupts of the coprocessor are masked, then
"0" is divided by "0" to generate an invalid operation exception.
At this time, if the IR (Interrupt Request) bit of the status
word of the coprocessor is "1", the program displays following error
message:
+-----------------------------------------------------------------+
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: Error code = 703 :
: COPROCESSOR INVALID OPERATION MASK ERROR :
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+-----------------------------------------------------------------+
12) Exceptional Data Comparison Check (2)
The data from Item 7) that resulted in zero division is
compared with "0" (fcom), and the program displays an error message
if they do not match:
+-----------------------------------------------------------------+
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: Error code = 705 I
: COPROCESSOR COMP ARISON ERROR :
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+-----------------------------------------------------------------+
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DIAGRAMS AN» REFERENCE MATERIALS
REV.A
13) Mathematic Function Check
Addition, subtraction, multiplication, division, and the square
root operation are performed, then the precision is checked.
The program displays an error message if the mathematic result
is incorrect.
+-----------------------------------------------------------------+
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: Error code = 710 :
: COPROCESSOR PRECISION ERROR :
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+-----------------------------------------------------------------+
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DIAGRAMS AHn REFERENCE MATERIALS
9. Parallel Port (Printer Interface) Check
This module performs a loop-back check on the parallel port
(printer interface).
Before starting this check, attach the loop-back connector to
the parallel port. The pin connection of the loop-back connection
shoud be as folIows:
+----------------+------------+------------+----------------------+
: Signal Name : PIN Number : PIN Number : Signal Name :
+----------------+------------+------------+----------------------+
: Strobe : 1

DIAGRAMS AN»
REFERENCE MATERIALS
HEV.A
If an unmatching bit is detected after performing the
comparison, the corresponding pin number is displayed in an
error message.
+-----------------------------------------------------------------+
I
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: PARALLEL PORT CHECK :
: Error code = 901 :
: ERROR PIN xx :
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I
+-----------------------------------------------------------------+
(The xx represents the pin number corresponding to the unmatching
bit. )
b. Next, using the test data "SS h" , an identical check is
performed.
2) WRITE/READ Check of Control Port
a. The test data "Oah" is output to the control port (37 A), then
compared with the input from the same port. The configuration
of the control port is as folIows:
+----------+----------+---------------------------+
: Bit no. : PIN no. : Signal Name :
+----------+----------+---------------------------+
o 1 Strobe :
1 14 Auto Feed :
2 16 Ietialize Printer :
3 17 Select Input l
4 IRQ Enable :
5 not use l
6 not use :
7 not use :
+----------+----------+---------------------------+
If an unmatching bit is detected after performing the
comparison, the corresponding pin number is displayed in an
error message. The error message is identical to that of
Item 1).
b. Next, using the test data "05h", an identical check is
performed.
3) Loop-back Check of Control Signal
a. The test data "Oah" is output to the control port (37A) and
the test data "Olh" is output to the data output port (378).
Next, input from the status port (379); the result is OK if
Bits 7, 4, and 3 are "I" and Bits 6 and 5 are "0". The
configuration of the status port is as folIows:
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HEV.A
DIAGRAKS AN» REFERENCE MATERIALS
+----------+----------+---------------------------+
: Bit no. : PIN no. : Signal Name :
+----------+----------+---------------------------+
: 0 not use
: 1 not use
: 2 not use
: 3 15 Error
: 4 13 Se1ect
l 5 12 P.END (out of paper)
: 6 10 Acknow1edge
l 7 11 Busy
+----------+----------+---------------------------+
If an error is detected, the error message that identica1 to
that of Item 1) is disp1ayed.
b. The test data "05h" is output to the contro1 port (37~ and
the test data "OOh" is output to the data output port (378).
Next, input from the status port (379); the resu1t is OK if
Bits 7, 4, and 3 are "0" and Bits 6 and 5 are "1".
If an error is detected, the error message that identica1 to
that of Item 1) is diap1ayed.
c. Test data is output to the contro1 port and data output port
so that each signal of the status port goes ON, then the
resu1ts are checked.
If an error is detected, the error message that identica1 to
that of Item 1) is disp1ayed.
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DIAGRAMS AND
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HEV.A
11. Serial Port (RS-232C) Check
This module performs a loop-back check of the serial port (RS­
232C port).
Before starting this check, attach the loop-back connector to
the serial port.
The pin connection of the 9 pins loop-back connector is as
folIows:
+---------------------+----------+----------+-----------------+
l Signal Name lPIN NumberlPIN Number: Signal Name l
+---------------------+----------+----------+-----------------+
: Transmit Data : 3

HEV.A DIAGRAMS AND REFERENCE MATERIALS
When CTS = 1:
+-----------------------------------------------------------------+
I
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: Error code = 1101 :
: ERROR RTS CTS, CTS ALWAYS HIGH :
I
I
+-----------------------------------------------------------------+
b. DTR = 1 and RTS = 1 are output, then DSR and CTS are input.
The results are OK if both DSR and CTS equal "I". An error
message is displayed if either signal equals "0".
When DSR = 0:
+-----------------------------------------------------------------+
I
I
: Error code = 1101 :
: ERROR DTR DSR, DSR ALWAYS LOW :
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I
+-----------------------------------------------------------------+
When CTS = 0:
+-----------------------------------------------------------------+
I
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: Error code = 1101 I
: ERROR RTS CTS, CTS ALWAYS LOW :
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I
+-----------------------------------------------------------------+
2) Data Transfer Check using Various Baud Rates
The setting is fixed to even parity, two stop bits, and an
eight-bit data length. The check data is "00" - "FFh".
A timeout check during data transmission and reception and a
comparison check of the sent data and received data is performed.
The baud rates for performing the checks are used in the order
below:
+------------+
: 75 bps
: 110 bps
: 150 bps
: 300 bps
: 600 bps
: 1200 bps
: 2400 bps
: 4800 bps
: 9600 bps
+------------+
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7-79

DIAGlU\MS AND REFERENCE MATERIALS HEV.A
When the check is started, the following message appears:
+-----------------------------------------------------------------+
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SERIAL PORT CHECK
RS232C echo back check at various baud rates
Current baud rate is xxxx
Current test data is yy
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+-----------------------------------------------------------------+
(xxxx represents the baud rate used for the current check, and yy
represents the test data.)
The program displays an error message if either the TX Shift
Register Empty status is not assumed during data transmission or
the Data Ready status is not assumed during data reception.
+-----------------------------------------------------------------+
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: Error code = 1102 :
: TIME OUT ERROR :
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+-----------------------------------------------------------------+
Thesent data and received data is compared,and theprogram
displays an error message if they do not match.
+-----------------------------------------------------------------+
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1103
Error code =
VERIFY ERROR
Sent data
Redeived data
xx
yy
+-----------------------------------------------------------------+
(xx represents the sent data and yy representes the received data.)
3) Data Transfer Check using Various Data Lengths, Stop Bits, and
Parity
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The baud rate is fixed to 9600 bps.
data varies according to the data length.
The scope of the check
+-------------------+-------------------+
: data length : check data :
+-------------------+-------------------+
: 8 bits : 00 - FFh :
: 7 bits : 00 - 7Fh :
: 6 bits : 00 - 3Fh :
: 5 bits : 00 - IFh :
+-------------------+-------------------+
7-80

REV.A DIAGRAMS AND REFERENCE MATERIALS
A timeout check during data transmission and reception and a
comparison check of the sent data and received data is performed.
The data transfer conditions to be checked consist of the
following combinations:
+-----------------------------------------------------------------+
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No parity --\
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Odd parity --\
1-­ Data length 5 bits I
I
Even parity --+-+-­ Stop bit 1 --+-+--­
6 bits I
I
Parity 0 ----I \­ Stop bit 1.5 -I \--
7 bits IIIII
Parity 1 ---I
or 2 \-
8 bits
I
+-----------------------------------------------------------------+
When the check is started, the following message appreas:
+-----------------------------------------------------------------+
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SERIAL PORT CHECK
RS232C echo back check -- with various data format
Current data format: w data bits, x stop bits, parity -
Current test data is zz
yyyy
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I+-----------------------------------------------------------------+
(w represents the data length of the current check, x represents
the stop bits, yyyy represents the parity bit setting of NONE, ODD,
EVEN, SP ACED or MARKED, and zz represents the test data.)
In case of a timeout error detected during data transfer or
mismatching of sent data and received data, the error message
identical to that of Item 2) is displayed.
7-81

DIAGRAMS
AN» REFERENCE MATERIALS
REV.A
12. Alternate Serial Port Check
This module performs a loop-back check of the alternate serial
port (alternate RS-232C port).
Before starting this check, attach the loop-back connector to
the alternate serial port, then issue the instruction to start the
check.
+-----------------------------------------------------------------+
ALTERNATE SERIAL PORT CHECK
Attach loop-back connector to alternate serial port.
Enter Y to start this check when connector is attachd, or
Enter N to return to the menu.
+-----------------------------------------------------------------+
Since the checking procedure for the alternate serial port is
identical to that for the serial port, its checking procedure is
omitted here.
Only the differences are in port numbers and in the message
titles:
+-----------------------------------------------------------------+
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: Error code = 1201 :
: ERROR DTR DSR, DSR ALWAYS HIGH (or LOW) :
: ERROR RTS CTS, CTS ALWAYS HIGH (or LOW) :
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+-----------------------------------------------------------------+
+-----------------------------------------------------------------+
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: Error code = 1202 :
: TIME OUT ERROR :
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+-----------------------------------------------------------------+
+-----------------------------------------------------------------+
Error code = 1203
VERIFY ERROR
Sent data
Received data
xx
yy
+-----------------------------------------------------------------+
(xx represents the sent data and yy represents the received data.)
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7-82

REV .A DIAGRAMS AND REFERENCE MATERIALS
14. Dot-Matrix Printer Check
This module performs a printing check of the printer's with
ASCII characters and bit images data.
Before starting this check, connect the printer to the parallel
port, then issue the instruction to start.
+-----------------------------------------------------------------+
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: DOT-MATRIX PRINTER CHECK :
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: Is dot-matrix printer on-line (Y/N)? :
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+-----------------------------------------------------------------+
The procedures for checking the printer are as foliows:
(In case of test multiple times, only the printer connection check
is performed.)
1) Printer Connection Status Check
A NULL code is output to the printer and the printer status is
checked. If an error is detected, the corresponding error message
is displayed.
+-----------------------------------------------------------------+
DOT-MATRIX PRINTER CHECK
Error code = 1401
Status Time out error
Status 1/0 error
Status Not on-line
Status Acknowledge error
Status Busy
Status Out of paper
+-----------------------------------------------------------------+
2) Printing Check of Printer
ASCII characters and bit images are printed repeatedly by the
printer, then you can check the printing results:
+-----------------------------------------------------------------+
Print test data
Text data (20H-7FH,AOH-FFH)
Bit-image data (OOH-FFH)
Press any key to return to the menu.
+-----------------------------------------------------------------+
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7-83

DIAGRAMS AND REFERENCE MATERIALS
REV.A
a. Printing Check of ASCII Characters
The ASCII characters "20H"-"7FH" and "AOH"-"FFH" are printed
by the printer. The data is printed after printing the
following title:
+---------------------------------------------~-------------------+
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: Text data (20H-7FH,AOH-FFH) :
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+-----------------------------------------------------------------+
Printing is performed at 80 columns per line. If an error is
detected during printing, an error message is displayed that
is identical to that of Item 1).
b. Printing Check of Bit Images data
The bit images data of "OOH"-"FFH" are printed by the printer.
The data is printed after printing the following message:
+-----------------------------------------------------------------+
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: Bit-image data (OOH-FFH) :
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+-----------------------------------------------------------------+
The control code for bit-image printing is "ESC K n1 n2"
(specification of single-density bit images). If an error is
detected during printing, an error message is displayed that
is identical to that of Item 1).
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7-84

REV .A DIAGRAMS AND REFERENCE MATERIALS
17. Hard Disk Drives and Controller Check
This module checks the hard disks and the hard disk drives.
First of all, select which check is to be performed from the menu.
+--------------------------------------~------------- ------------+
HARn DISK DRIVE(S) AND
CONTROLLER CHECK MENU
1 - Seek check
2 - Write, read check
3 - Head select check
4 - Error detection and correction check
5 - Read, verify check
6 - Run all above checks
o - Exit
I Enter selection number:
I
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+-----------------------------------------------------------------+
(In case of test multiple times, the following checks are
consecutively executed in the order listed.)
+-----------------------------------------------------------------+
1 - Seek check
2 - Write, read check
3 - Head select check
4 - Error detection and correction check
+-----------------------------------------------------------------+
Each of the checking procedures are described as foliows:
1) Seek Check
The quantity of installed hard disk drives is first set using
function 8 of int 13. The following message is displayed in case
two hard disk drives are installed, so input the name of the drive
you wish to check.
+-----------------------------------------------------------------+
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: Check which drive (C/D)? :
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+-----------------------------------------------------------------+
The seek check performs a sequential check on all heads
simultaneously from the innermost cylinder position to the outermost
cylinder position, then checks the seek operation.
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7-85

DIAGRAMS AND REFERENCE MATERIALS HEV.A
+-----------------------------------------------------------------+
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: SEEK CHECK :
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: Current cylinder is xxx :
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+-----------------------------------------------------------------+
(The xxx represents the number of the cylinder being sought.)
If an error is detected in the seek operation t
message is displayed:
HARD DISK DRIVE(S)
Error code = 1701
SEEK ERROR
CYLINDER xxx
HEAD
y
AND
CONTROLLER CHECK
the following
+-----------------------------------------------------------------+
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+-----------------------------------------------------------------+
(xxx represents the number of the cylinder detected the error and
y represents the head number.)
2) WRITE/READ Check
Drive selection is identical to that of Item 1). Next t a
precaution is displayed when this check is started.
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+-----------------------------------------------------------------+
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The data on the highest physical cylinder may be destroyed
Enter Y to start this check.
Enter N to return to the menu.
by this check.:
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+-----------------------------------------------------------------+
The WRITE/READ check performs a WRITE/READ check for all
sectors of all heads of the innermost cylinder (highest cylinder).
The check data is "6db6h".
+-----------------------------------------------------------------+
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: WRITE t READ CHECK :
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+-----------------------------------------------------------------+
If an error is deteced during the writing or reading of data t
the following message is displayed.
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7-86

REV.A DIAGRAMS AND REFERENCE MATERIALS
In case of write error:
+-----------------------------------------------------------------+
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AND CONTROLLER CHECK
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HARD DISK DRIVE(S)
Error code = 1702
WRITE ERROR
CYLINDER xxx
HEAD
y
SECTOR zz
+-----------------------------------------------------------------+
(xxx represents the number of the cylinder detected the error, y
represents the head number, and zz represents the sector number.)
In case of read error:
+-----------------------------------------------------------------+
I
I
AND CONTROLLER CHECK
HARD DISK DRIVE(S)
Error code = 1703
READ ERROR
CYLINDER xxx
HEAD
y
SECTOR zz
+-----------------------------------------------------------------+
(xxx represents the number of the cylinder detected the error, y
represents the head number, and zz represents the sector number.)
3) Head Selection Check
Drive selection is identical to Item 1). The head selection
check makes each head seek the maximum cylinder position, then
checks the head selection status.
+-----------------------------------------------------------------+
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: HEAD SELECT CHECK :
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+-----------------------------------------------------------------+
If the head is not properly selected, the following message is
displayed:
+-----------------------------------------------------------------+
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HARD pISK DRIVE(S) AND CONTROLLER CHECK
Error code = 1704
HEAD ERROR
HEAD
x
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+-----------------------------------------------------------------+
(The x represents the number of the head detected the error.)
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7-87

DIAGRAMS AND REFERENCE MATERIALS
REV.A
4) Error Detection/Correction Check
The procedure is identical to that of Item 2) up to the
display of the precaution.
+-----------------------------------------------------------------+
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: ERROR DETECTION AND CORRECTION CHECK :
I
I
+-----------------------------------------------------------------+
a. In the error detection check, the test data "6db6h" is
prepared in the buffer then is written to the hard disk using
the normal "write" instruction. Writing and reading are
performed at Sector number 1 of the highest head of the
highest cylinder.
Next, the data is read using "read long", its leading byte
is destroyed (= "2ah"), then re-written it using write long".
If a READ or WRITE error occurs up to this point, an error
message identical to that of Item 2) is displayed.
The data is then read using the normal "read" instrucion, and
the the following message is displayed if no error has been
detected:
+-----------------------------------------------------------------+
I
I
: HARD DISK DRIVE(S) AND CONTROLLER CHECK :
: Error code = 1705 :
: ERROR DETECTION ERROR :
I
I
I 1
+-----------------------------------------------------------------+
b. In the error correction check, the test data "6db6h" is
prepared in the buffer then is written to the hard disk using
the normal write instrucion. Writing and reading are
performed at Sector number 1 of the highest head of the
highest cylinder.
Next the data is read using "read long", its leading byte is
destroyed (= "6eh"), then re-written using "write long".
(5 bits error.)
If a READ or WRITE error occurs up to this point, a error
message identical to that of Item 2) is displayed.
The data is then read using the normal "read" instruction,
and the read data and the test data are compared. An error
message is displayed if the read data and test data do not
match. Concurrently, detection of ERROR CORRECTION is also
checked.
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7-88

REV.A DIAGRAKS AND REFERENCE MATERIALS
+-----------------------------------------------------------------+
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: HARD DISK DRIVE(S) AND CONTROLLER CHECK :
: Error code = 1706 :
: ERROR CORRECTION ERROR :
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+--------_._-------------------------------------------------------+
5) READ/VERIFY Check
Drive selection is identical to Item 1). In the READ/VERIFY
check, all heads from the highest cylinder to Cylinder No. 0 are
read in track units, and the read statuses that detected bad sector
or any other READ error are preserved.
+-----------------------------------------------------------------+
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: READ, VERIFY CHECK :
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: Current cylinder is xxx :
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+-----------------------------------------------------------------+
(The xxx represents the number of the cylinder being read.)
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When the reading of all cylinders up to Cylinder No.
completed, the results are displayed:
0 is
+-----------------------------------------------------------------+
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: READ, VERIFY CHECK :
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: BAD TRACKS •.•...•.•..••...•. xxxx :
: READ ERROR TRACKS ..•.••.••.. yyyy :
: GOOD TRACKS ..•••••..•••••••• zzzz :
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: Press ENTER to return to the menu :
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+-----------------------------------------------------------------+
(xxxx represents the total number of bad tracks, yyyy represents
the total number of tracks detecting a READ error, zzzz represents
total number of normal tracks.)
6) Run All Above Checks
When "Run all above checks" is selected, the preceding checks
described in Items 1) to 5) are consecutively executed.
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7-89

DIAGRAMS ABO REFERENCE MATERIALS
REV.A
21. Alternate Parallel Port Check
This module performs a loop-back check of the alternate
parallel port.
Before starting this check, attach the loop-back connector to
the alternate parallel port, then issue the instruction to start
the check.
+-----------------------------------------------------------------+
I
ALTERNATE PARALLEL PORT CHECK
Attach loop-back connector to alternate parallel port.
Enter Y to start this check when connector is attached, or
Enter N to return to the menu.
+-----------------------------------------------------------------+
Since the checking procedure for the alternate parallel port
is identical to that for the parallel port, its checking procedure
is omitted here.
Only the differences are port numbers and the error message
titles.
I,
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Data output port
Status port
Controll port
278h
279h
27ah
+-----------------------------------------------------------------+
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: ALTERNATE PARALLEL PORT CHECK :
: Error code = 2101 :
: ERROR PIN xx :
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I
+-----------------------------------------------------------------+
(The xx represents the pin number corresponding to bit number which
is detected as an error.)
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7-90

CHAPTER
8
DIFFERENCE ßETWEEN 10MHz AND 12MHz
Section
8.1
8.1.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
Title
TAßLE OF CONTENTS
MAJOR PARTS
Excluding P.C.B. Units .
COMPONENT PARTS .••••.....••...........•..•.••.•.••••••••••.
ANTA Board Unit .
ANT-RM Board Unit .
ANT-RMA Board Unit .
ANT-MT Board Unit .
SPFG Board Unit .
Page
8.3 JUMPER SETTINGS 8-10
8.3.1 ANTA Board Jumper Settings 8-10
8.3.2 ANT-RM/RMA Board Jumper Settings 8-11
8.3.3 SPFG Board Jumper Settings 8-12
8.3.4 WHDC Board Jumper Settings 8-13
8.4 COMPATIBILITY LIST 8-14
8.4.1 Major Unit 8-14
8.4.2 P.C.8. Unit 8-15
8-1
8-1
8-3
8-3
8-6
8-7
8-8
8-9

8.1 MAJOR PARTS
8.1.1 Excluding P.C.B. Units
Modifieation Substitution
Unit Name Deseription Reason for Modifieation Possible
10MHz 12MHz
Switeh Modifieation Switch Panel Label 01 Switeh Panel Label B01 Beeause the CPU eloek No
Panel the de- (Y126027051) (Y126042051) sBeed is inereased from
Label seription of or 1 MHz to 12MHz.
the eloek Switeh Panel Label 02
speed (Y126027151)
Earth Addition of No Earth Plate C is Earth Plate C is installed Countermeasure for FCC NA
Plate C the Earth installed. (Y126039251)
Plate C
Hard Disk Modification Cable set ff5BX Cable set 1f5DY Hard Disk Cables for 12 No
Cable of the Hard (Y126306000§ (Y127300300§ MHz version should be
Disk Cables Cable set If BY Cable set 11 DZ longer than the 10MHz's
(Y126310000) (Y127300400) beeause the loeation of
the option slot eonneetor
is ehanged.
Serial Modifieation Serial Number Plate B06 Alphabet "A" is prefixed No
Number of the Serial Serial Number Plate 03 (Y126041651) to the serial number.
Plate Number Plate (Y126025251) [Old~ 010001 ---
New A010001 --
Code Label Modifieation No
of the Code (abbreviated) (abbreviated) (abbreviated)
Label
SPFG Board Cireuit design SPFG board unit SPFG board unit To solve the format No
modification (Y12720100001) (Y12720110000) error with the 360KB or
720KB FDD at 12MHz.
ROM BIOS ~1~ New Ver. Version 1.02 Version 2.00 ~1~ New version No
2 Modifi- ATR-B3 ~Y126814002~ ATR-B5 ~Y126814004~ 2 Cost reduetion
cation of the ATR-C3 Y126815002 ATR-C5 Y126815004 (ROM type: 27256 ->
ROM type ROM type: 27256-15 ROM type: 27128-15 27128)
Monitor Addition of No Monitor Conneetor Cable Cable set 1f5EM Countermeasure for FCC NA
Conneetor the Monitor is used. (Y126311000)
Cable Conneetor
Cable
I
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3:
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0)
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Modification Substitution
Unit Name Description Reason for Modification possible
10MHz 12MHz
ANT-RM Circuit design ANT-RM board unit ANT-RM board unit (1) To improve RAM No
Board modification (Y12620300000) (Y12620700000) access speed
(2) T9 ~djust signal
tlmlng
ANT-MT ~1) Cable set ANT-MT board unit ANT-MT board unit (1) Countermeasure for No
Board /'5BT addition (Y12620200000) (Y12620800000) FCC
(2) Modifi- (2) To allow to use a
cation of the full len~th Hard
location of Disk Con roller
the option
slot connector
ANT-RMA ANT-RMA board No ANT-RMA board unit is ANT-RMA board unit To keep constant parts No
Board unit newly' used. (Y12620900000) supply
authorizea * This is an alternative
unit for the ANT-RM board
unit.
ANTA Board Circuit design ANTA board unit ANTA board unit (1) To increase CPU No
modification (Y12620500000) (Y12620600000) speed
(2) Countermeasure for
FCC
~3~ Cost reduction
4 Countermeasure for
the genius problem
(5) To im~rove the
execu ion s~eed of
the keyboar controller
c =n
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m
1XI
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» ZC
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~
1XI

8.2 COMPONENT PARTS
8.2.1 ANTA Board Unit
Unit
Description
ANTA Board 1(1) Addition
of a filter
Y12620500000 circuit
-->
Y12620600000
Q)
I
(,,)
Modification
10MHz 12MHz
R39 R39
GAATCK 330hm GAATCK 560hm
50 50
SCLK CLK SCLK . ,
B3
(3C) CN1 OC) 2uH C40 1.
SCLK 34b 47PF-l-
6
(3B)
GAATRF
CN1
34b
~A~, , 0 CLK
GAATRF
SCLK
(1) Additional parts 6
B3 (Y130202002) (3B)
C40 (X221224703)
(2) Parts modification
R39 : 330hm ----> 560hm
(X154413302) (X154415602)
CN5 B1 8042
~ 2uH I I
1 I 1
2 I J-
l'"VV'o.
-l
B2
L...--...J 1
C42 2uH..1-
TESTO
C16
47pF I (3F)
-----j TEST1
39
m m 47pF
(1) Additional parts
C41 (X221221213)
C42 ( " )
(2) Parts modification
B1 (X506000029)->(Y130202002)
B2 ( " )->( " )
120pF li
lr C15
Countermeasure for FCC
Countermeasure for FCC
::D
~
Cl
Q
"TI
"TI
m::DmZ()
m
~m mẒ
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Q)
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Modification
Unit Description Reason for Modification
10MHz 12MHz
ANTA Board (3) . C

Unit Description
ANTA Board (6) Modification
of the
CPU
(7) Modification
of the
CPU socket
(8) Deletion
of the 20MHz
asc circuit
(9) Deletion of
the resistors
Modification
I I IReason for Modification
10MHz 12MHz
Location :
Part :
*LCC type
Location
Part
2A SAB80286-1-R
(X400802861)
or
INTEL
80286-10
(X401802861)
or
AMD
R80L286-10/C2H
(X402802868)
2A
: LCC type
(X6301l6802)
C10
~PF 12 GAATCX
CR2TI R16 IX201 I
20M 0 PLCC)
Cost reduction
This circuit is not
necessary because the
computer system does
not use 10MHz.
Countermeasure for
genius problem.
(10) New Key- I Location : 3F
board controlley Part : C42051KA
version (Y126813000)
Location : 3F
Part : C42051KB
(Y126813001)
To improve the execution
speed of the keyboard
controller.
00
I
C11
:D
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" " m
:DmZ(')
m
~m Z
Q
.....
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8.2.2 ANT-RM Board Unit
Modification
Unit Description Reason for Modification
10MHz 12MHz
ANT-RM Board (1) Modifi- Location : 19B to 22B Location : 19B to 22B To improve RAM access
cation of the Part : FUJITSU FUJITSU speed.
Y12620300000 D-RAM chips MB81464-12P MB81464-10P
---> (X400S84641) (X400S84643)
Y12620700000 or or
NEC NEC
uPD41464C-12 uPD41464C-10
(X400414642) (X400414641)
or
HITACHI
HMS0464-12
(X400S04641)
Location : 21A and 22A Location 21A and 22A
Part : NEC Part : NEC
uPD4164C-12 uPD4164C-10
(X40014164S) (X400141646)
or
MATSUSHITA
MN4164P-12
(X400041643)
(2) Modifi- Location : RL1 Location : RL1 To adjust signal timing
cation of the Part : 200ns to~e Part : 1S0ns to~e
delay line chip (XS1000 20) (XS1000 90)
(3) Modifi- Location : 24A and 24B Location : 24A and 24B ~1~ Cost reduction
cation of the Part : ATR-B3 ~Y126814002~ Part : ATR-BS ~Y126814004~ 2 New version
P-ROM ATR-C3 Y12681S002 ATR-CS Y12681S004
272S~-1S to~e 27128-15 toBe
VerSl0n 1. Version 2.
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8.2.3 ANT-RMA Board Unit
Modification
Unit Description Reason for Modification
10MHz 12MHz
ANT-RMA ANT-RMA board Not installed Installed To keep constant parts
Board unit newly (Alternative unit for ANT-RM supply.
authorizea board)

00
I
00
8.2.4 ANT-MT Board Unit
Modifieation
Unit Deseription Reason for Modifieation
10MHz 12MHz
ANT-MT Board (1) Addition Not installed Installed Countermeasure for FCC
of the eable Part: Cable set #5BT
Y12620200000 set #5BT (Y126303000)
--->
Y12620800000 (2) Modifi- 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 To allow a full length
eation of the Hard Disk Controller to
slot loeation
be installed in
CN~
CN~
eonneetor CN8.
~ ~ ~ ~ ~ ~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~
11 11 11 11 11 11 11 11 11 11 11 11
2
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8.2.5 SPFG Board Unit
Modification
Unit Description Reason for Modification
10MHz 12MHz
J
SPFG Board (1) Addition of GAATFD uPD765A-2 GAATFD
a delay circuit
B
~
1= I

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8.3 JUMPER SETTINGS
8.3.1 ANTA Board Jumper Settings
Unit
Jumper Function Factory Settings
J6 J5 J4 J3 J2 J1 10MHz 12MHz 10MHz 12MHz
ANTA - - - - - A Set CPU clock (6/8/10MHz) Prohibited J1: A J1: B
Board - - - - - B Prohibited Set CPU clock (6/8/12MHz)
- - - A - Prohibited

8.3.2 ANT-RM/RMA Board Jumper Settings
Unit
Jumper Function Factory Settings
J7 J6 J5 J4 J3 J2 J1 10MHz 12MHz 10MHz 12MHz
ANT-RM / - - - - A RAM size 640KB

CD
....
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8.3.3 SPFG Board Jumper Settings
Unit Jumper Function Factory Settings
J8 J7 J6 J5 J4 J3 J2 J1 J10 J9 10MHz 12MHz 10MHz 12MHz
SPFG - - - - - - A - - Primary register set (AT FDC)

8.3.4 WHDC Board Jumper Settings
Unit
Jumper Function Factory Settings
J3 J2 J1 10MHz 12MHz 10MHz 12MHz
WHDC - - B Select primary address sets

~
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8.4 COMPATIBILITY LIST
8.4.1 Major Unit
Unit 10MHz 12MHz
Main Power ATRPS OK OK
Unit Supply ANPS OK OK
K.B. ----- -------- OK OK
Unit
FDD 360KB MD5201-57 OK OK
Unit -58 OK OK
1.2MB FD1155C OK OK
FD1157C OK OK
MD5501-61 OK OK
Display Mono MRS-MO Board OK (See ~'(1) OK (See *1)
Adapter
Color MRS- CR Board OK OK
MGA Board OK OK
EGA Board OK (See ~'(2) OK (See ~'(2)
Descriptions:
*1 : Unit code Y14420620000 should be used.
*2 : Unit code Y12720400001 ---- Code view problem may occur.
Unit code Y12720400002 ---- Code view problem is solved on this verSlon.
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8.4.2 P.C.B Unit
Board 10MHz 12MHz
ANTA Board Y12620100000 (See *d) NG
Y12620100001 (See *d) NG
Y12620100002 (See j'd) NG
Y12620100003 OK NG
Y12620100004 OK NG
Y12620S00000 OK NG
Y12620600000 NG OK
ANT-RM Board Y12620300000 OK NG
Y12620700000 (See ''(a) OK
ANT-RMA Board Y12620900000 (See ''(a) OK
ANT-MT Board Y12620200000 OK (See ''(b)
Y12620200001 OK (See ''(b)
Y12620800000 (See "'b) OK
SPFG Board Y12720100000 OK NG
Y12720100001 OK NG
Y12720110000 (See ''(a) OK
WHDC Board Y12720300000 (See ''(c & "'d) (See ,',c & ''(d)
Y12720310000 (See "'c) (See )'(c)
Y12720300001 (See ''(d) (See ''(d)
Y12720310001 OK OK
Descriptions:
)'(a : Should be "OK" but an additional compatibility check is required.
*b : The location of the option-slot connectors are different.
*c : XENIX problem may occur.
*d : This board may not satisfy FCC standard.
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LIST OF
DIAGRAMS
UNIT NAME
V-CODE
ANTA Board Unit Y12620100000 •.•......•.••••.••..•• A-l
Y12620100001 .....•...•..•......••• A-2
Y12620100002 ...•..•..••..••..••.•• A-3
Y12620100002A ....••.••.•••..•..••. A-4
Y12620100003 ....•..•..••..•••••..• A-5
Y12620100004 ...•..........•••....• A-6
Y12620500000 ..•..•..••.••......••. A-7
Y12620600000 ••..•.....•••••••••..• A-8
ANT-RM Board Unit
ANT-RMA Board Unit
ANT-MT Board Unit
ATRPS Unit (Major Circuit)
(THIC-35 Board)
(Major Ci rcuit)
(THIC-35 Board)
ANPS
Unit
SPFG Board Unit (Sheet 1/2)
(Sheet 2/2)
(Sheet 1/2)
(Sheet 2/2)
(Sheet 1/2)
(Sheet 2/2)
Y12620300000
Y12620700000
Y12620900000
Yl2620200000
Yl2620200001
Yl2620800000
Y126501000
Yl2650100001
Yl26509000
Yl2720100000
Yl2720100001
Yl2720110000
PAGE
· . . . . . . . . . . . . . . . . . . . .. A-9
· . . . . . . . . . . . . . . . . . . . .. A-IO
· . . . . . . . . . . . . . . . . . . . .. A-IO
· . . . . . . . . . . . . . . . . . . . .. A-l1
A-ll
A-ll
· . . . . . . . . . . . . . . . . . . . .. A-12
· . . . . . . . . . . . . . . . . . . . .. A-13
· . . . . . . . . . . . . . . . . . . . .. A-12
· . . . . . . . . . . . . . . . . . . . .. A-13
· . . . . . . . . . . . . . . . . . . . .. A-14
· . . . . . . . . . . . . . . . . . . . .. A-15
· . . . . . . . . . . . . . . . . . . . .. A-17
· . . . . . . . . . . . . . . . . . . . .. A-15
· . . . . . . . . . . . . . . . . . . . .. A-17
· . . . . . . . . . . . . . . . . . . . .. A-16
A-17
WHDC Board Un it Y12720300000 ...................••. A-18
Y12720310000 ...........•..•...•.•. A-18
Y12720300001 .......•..•...•....... A-18
Y12720310001 A-18
MGA
kEYBOARD
Board Unit
FD1155C (1.2MB FDD) Unit (Sheet 1/2)
(Sheet 2/2)
HMD-720 (3.5 Inch HDD) Main Board
MFG
Board Unit
Exploded Diagram (Sheet 1/2)
(Sheet 2/2)
Y12720400001
...................................
A-19
A-20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-21
A-22
A-23
A-24
A-25
A-26

1
2
3
4
+5 +5
A B c o E F G H
R8 Slidl! SW' ~ Rli
470 ~ ~4.7K'2 :lr-----.,
~I Al.8 ß AC I 60 CSPOO COLY 61
i I B~ ~ ~ BC 59 CSPOI AR~~~ S,
.J.. R12 RIS AROYN 4
Z~ 1" 5 +5 3 Rl!Sl!1 Button +5 ZOK.'7 E SAO 1,'
R7' Jl'1?F~x2 RSW ~ ~Z SW3 RH10.1 Al 3 Al SAI
~7 A23 DIS 51 DIS AI7 AI7 ~ SA17 "
A2Z 014 AlB SAlB
~'r+ A21 013 47 l A19 l SA19
~
l
Öri' :~~ g:~ 4 11 m otm 4
'1 AlB 010 A22 8 LAU
W 11 t:iHl ::~ g: +5 ~~~ 6 ~m
• 1 AIS 07 ,.+-+~+J~==t=~~:~MCNRNC LL:Z 2Z 3
A14 06 C2S~L.A .... VCC AOXRW
Al f-1:g g: O.l)l~ .J.. GNOB SMRN 44
~
~n g~ 1;~~~I~~~!~~~fl~~~I~~~~It~~~I=~=:~ ~:~~
A :~ 2A 00 Lt:i:\wl ~5 ~~~N x~'8:~
4
~
:: A9

1
2
3
4
5
+5 +5
L
A B c o E F G H
R8 Slid~ SW. 1~ 'Rn
470 h ~4.7:.12 :j ....----...
8 8 DEN 153
2 B~ -J -J 8C 59 CSPOI ARENN
~ l.-dl RI2 R15 ARDVN
rff Jl'1OF~x2 RSW' : ~ ~~R~i~t3BUltOn +5 20K'1~1 3 Al E ~:~ : ~
+ 5 14'----
OSC '~e~~en BALE -7!!~iA36fEA3 1 SA3 14
TO" SCLK 10-6 A4 0 5A4
C24 CR3 1~::.t.'l,T-LS 63 DCLK .- 6 A5 SA5
O.l~1f 48MH: R"15-4 CUM SRDYN 10· 5 A6 8 SA6
+5 ~F7ll =' CN3'~~ RSW~E~~~~~~~~l=====~~ R_H~'~~:: 'A A2 0 SA2
+5 ... 34 3C OSC 47 9-~ :~ C S ~:~ ~~
,,'---- •• TESTN C1M 55 ... A9 SA9 rt f---
20K 14 3 I' AIO BSAIO
14.31818MH~~ RMI6~~ R:SDNV 56 ~: AI m ~::~ I~~
R14 ...."1.. 1 55 AAl, 3 ... R33 ACKN 7 'AIS
4 ,
::~
HCU04 4700 AEN I

1
2
3
4
5
+5 +5
A B c o E F G H
R8 5li~5W'RI3 ~ :,
47n~ 1W-

1
2
3
4
5
A B c o E F G H
+5 +5
R8 Slide 3, ~I
SW·RI
47fi h ~4.7K'2 :1,...----..,
~I Al A~ .8 AC 60 CSPOO COLY 61
iI I~ 12 ~ IC 5'1 CSPOI AR~~~ 15,
If
R12 R15
~7 1.23 DIS 5'
1 1 :~~ gl~ 4
1 1.18 Dl0
~~mAI7 09
1 :1~ g~
1
1.14
N1-l,~+101I. 13
06
D5
r~m~~AI2 All
04
03
~~:tijAl0 D2
r 1.9 Dl
~~:UJ:~ 2A 00 ;"~
J ~t:H1A6 I.S CODITI'!!.! ..I.I!.E
N!+-~II:~ M/~ 4
LU~Ut::l~:~
C23
0.047,.
~VSS
,.....Ll!. vss
~~
wd
"- 1.0 CLK
L-_.,.........~
.Ln :gg
015 ,,-
I
1
11
dlH~~~
~;b~~~l:~~I!!K~'-~'~;l
0471i C19 P
O. PAK 5
C 45 VS5 PEAEQ
IOpF VSS LCC
I ~, VSS80286-1
•.~C~2 68-Pin
CAP
~~~l with socket
S
CPU
MS-I
I I·~13 DI2
11 Numerical
. o~o Processor Ext.
D8 DIS 1-- 015
• D7 014 ~
D~ 013 I--
D4 DIP gg =
It::;rl~g~ 80287-8 Dl0 -
I' DO 40-Pin g:
2DK.IS Dl Socket 07
R40 06
20K~ ~ g:
\.-f+-+-_....._....:3~74CLK286 03
J3 l D2
~~C~~ 32 2 B g~
LI+-+-~~rrr-lcLK
J:1E iEn ~53: CKMCoi~~~t.I~214~~~~~~~~~~~~~~~~
Ne ...HI..DA
n NC ~
+S RESti 1
ARDYN.
~ 5 +5 3Reset Button +5 20KI17 11
R' Jl'1C?F~x2 3 R5WP 4 ~ .-a 2
SW3 RHIO.. AI 3 1.' E 51.0
+5 +5~p4~ 14'Q"S'C =r CN3t~P_ oie~een R5W~~~~~~~~~~'~~~~~~tt--------:~.-. aALE ., I. 1.2 Al 01 51.3 ~:~
C24 CR3 1il~~~.nT'LS 63 m~ '~_: :~ 0 ~:~
O.IJlIr48~ RM15-4 C48M SRDYN '0-' A6 ~ ~:~
+5 34 3 C OSC 47 .. ~ :~ C S5~19
" L.....- TESTN C1M S ... 1.9 ~
20K 14 • 11 Al0 BSA'O
14.31818MH~~ RM 16-6 RSDV - : I::
CMDI
i~~
NPS2
NNf:R
31 XA2
5
I
TC
SAO
A'
A12
13
4
=
m
?~mll~~~~~~i~~~~I~
otm 1
:1:
~I~I~~A~117-~~IA17 E 51.17 SA 17
1.22 8 LA19
+s__>-4-'''I~~~ 6 t :~~
...l_U.J..lu.t:=:::t:i:t~:~~:NC tm
C 2~~ :u ... vcc AOXRW
O,').I~ r'- GND8 SMRN 44
MEMRN SMWN
-- 63
DIS E SDIS
gl~
DU
Dll
l~~31!f~liG24SN
+5-
~ VCC REAOY ... I ~
o!~~' t
ZOKJl:~~ ~ ~
+ -C 6.r
O.IJI I~
MEMWN XMRN
10RN XMWN
10WN XIOAN
DLA S8HEN
GSAN XBHEN
ALE GSRWN
_ 1 OEN 1C NDll
.... r--_-4l:..l-Ig:g: N~J~
r- GND8 NAII
", ~~ N:~~
0 ~g:~
1 SD'2
OSD11
~o 8 s~~~
g! ~ m
os A SDS
04 SD4
D3 5D3
D2 502
Dl SDI
00 500
25 D24S :g::
DD 101012
MD13
4 gg~: :g:~
!!!J. ~::1l, B =g:
ZAa. OMD MD7
~ K GMDLN MD6
GMDHN MOS
VCC M04
VCC 10103
GNDA MD2
GNOA 10101
GNOII MOO
GAATDB
~ ~:: ~ 47
~~ R33 I~ A~~: S6 .. ~ :~~ ~:1~
HCU04 4700,1, AEN 1'1 : 1 m ~:n
""ih:. 4 I,.!oB, 1 C14M 54 ... .~ TE5TN XAO 7
3 V O C p 1 ~C~ C8 HCU04 EM~~~~ ~~.r m ~:~
~ ~ 10P ~33P E01068CA m~.. 1 A m
r
20MHZii[]~l ENASII011111!~~~'~~~~;~1~~f~~;;40·l:~m:.
470ll o.l,,~ ALE n~
32
,;:: ... J'JJ31 C20M INTAN XA10
XA5
riiiillJliii +5-tii VCC DTR XA6
~F']6 C~7r YCC Mil~~ GAATAB;;9~
C9 SHc"~:''HC'''4 ::i:::: I ~~~N ~::~
lOP* ~:+5 10RN ---ol I: C590 1l XA13
R5 I~"':~ IfJ '" ~=g~ ~~:;
_-f~~~~4~.7~K~~43~PCLKN CLKlil!- J'_~I' ß: GND8 XAI6
~
44 PCLKP .::~~ :!Ir- Wn' l'J GND8 Lg:~
141 PWGD SO-N I
...... S S ..... C8M SI-N
r ~===~p'3~A'
2i RCllGAATCK HLDA
+5
RSCPU
R6
GND8 GNDA ,'6 4.7K
49 GND8 GNDA
1- ~ <
GAATCB
AI
J4
J5
J6
1.20
-
~5 OEN
IRD
+5
61
RI
4700
n GAATIO 8 ~
L... QI TM2GIij==:t:t:t:::::l±tj=ti±Jt::±It±t--f----l
~~2 2C ~:~~~~l~~ä~Eg~~äf~i~~~f
I
L..-
INTAN
ASTN
AEN2
STBI
MSTRN STl2
ACKN OUT 2
ENAS DAKONlUl
5MI0 OAK2NIU)
~:~N g~~::~: I
.... ~:: E ~~~=
f-'l XAO 0 A17~
XAlIU) 1 A18~
~~:~\O ::
XA41U)9 1.2'
~::~~2 1.22
~ X~lUlE Im
I---- XAlIU)A PCKN ,
l'-'-o l XA9IU) C~~: E I
"
R32
4,!.0.I1.
..--+5
~-4 +5
~20K'3
-I
, -,oll"I +5
+5
RMI2..
LA23 ..... ~
20 ~~!~~-4t1
19
18 ~
17 j.:.'.;
20K.7
AM12-9
A19
E
AI
14
I.
I.
'I
~+5
t 5 - ...-l-I-I-'lI\I\r-4.;!.+ 5
,.f-l rTEO OS -- r- OS IRS ~ Ir-- 15 210
H ~ CLK2 g~1~t::@~IUlB~I-!!g~ 0' i- 0' 1F IR' ::~ L- t= I- r-r.;:::==::t:t:t======::::l:t:~ L.--- ~ ~~: :~:
..... CLKI 3E DO '-- 00 +S,o
16 GATE2 07~1~'--~1711~i D~4 07 IR7 2S_lflQ7~~E~~~~~~ - R,A'47ftn «
.... ~ GATEI D6 ~ I- D6 IR6 l-- 20KI4 1f~1~~E~~~~m
'-t+-t~ D4 f- 04 IA4 l-- L.---
B
f.--+J OU71 1.0 ~ 26 CAS11t1- SDI: ~ ~ L.--- ~ 140
CLKO Al INT CAS2:li-- AM6-7 ~,-- a:
+5 11.... :~ ~ I~ -
FI
24-PinGND~2O""'~ IRO VCC 28 20KKS 10.... - ~::
36
, cs 28-Pin : t - 23b
Timer VSS~~).I 20Kli 22b
Master I ... I ~~:
I
37b
3Ib
39b
40b
_---.~ ~~~ij~: 1 CSDZN 1 06 I A6 I "
r---. :I XAI4 XAIO CSDIN CSI2N 7 4~0~7i~~rlR~7rn2ISi'I·~I~~~~~~~~-J
D4 I R4 IR 1
1 ------.1~~~~~All~S~21415111~~~I~~II~~~IXAII'['IIXA'~ CSllN
::20::
AI BI" X07 07(u) XIWNM 03 I R3 :. :~
A7 87 XD6M XIRNlLO j: 02 1 E I A2 J
A6 8i p;
OS lAS R I
1.3 83 XXD D 2 3M II R
T A D
S I NTA CAS,
IU) ~ ..... CASO H:!:::Il~cJ
:~ :~ ~g~(U» ~~~~ I C'7+ S "LI INT IJ
~ DI R (U 14 \ili VCC 28 +S
_ AAJ:L ~~~ V~~~ R22 VAl ~t. l C 0 3 V CN3 ~ 8259A-2MLC32
XAI6 7 XAI6 S~'I":""-cC28 30K 1.!!.~ 1 ~~ "" 01
SKIIN VSS:,. 0,1" t;:ii:l~:I~!~ ... 6~S~.~~O;~~~Oi::"t::~r=SPEAKERj6 ~===I:t:t::;l 28-Pinvss 14 .).1
NC VSS' ~R23 312 ~ +K8D INH S SP/EN 1
R37 470A L.-.:., 4NJM386 I*oa.o GND 7 TO J1 Slave
+5 9100 n" ON ~~IRbS Interrupt Controll.r
+5
R17
470A
lb
2b
26b
49b
50b
33b
320
340
360
4Sb
46b
47b
350
450
460
470
210
290
34b
10
20
260
270
490
,lb
lOb
9b
Ib
7b
6b
Sb
4b
130
120
110
100
90
10
70
60
50
40
30
20b
Ub
17b
16b
ISb
14b
13b
370
Ho
390
400
4'0
30b
31b
4'b
32b
3b
42b
43b
44b
420
430
440
48b
480
300
310
50a
22a
+5 A29 lOK
~Wr.....-~"'J 27 b
C13
+5 '-t"~ 100P
C1,2 .L.+
10V,.
I"'!'!'~-O'
1M220JJ
OW5
+5VDC
+5VDC
+ 5VDC
+5VDC
+5VDC
8ALE
10CHRDY
AEN
RE5ET DRV
OSC
DRQ3
DRQ2
DRQl
~
~
rCLK
GND
GND
GND
GND
GND
SA19
SAU
5A'7
SA'6
51.'5
SAH
51.13
51.'2
SA11
51.'0
51.9
SAI
51.7
51.6
51.5
SA4
51.3
51.2
51.1
SAO
SD7
SD6
SD5
SD4
SD3
SD2
SD'
SDO
IRQ7
IRQ6
IRQ5
IRQ4
ülk
IRQ9
Hnnii
1/0 CHCK
DRQ7
DRQ6
DRQ5
DACK7
DACK6
DACK5
ORQO
OACKO
MEMR
MEMW
GND
~
5015
SD14
5013
SD'2
SDll
SO'O
SD9
SDI
LA23
LA22
LA21
LA20
LA19
LAU
LA17
iinTn
IAQ15
IRQ14
IRQU
IIIQ11
IRQ10
51HE
POWER GOOD
+SVOC
GNO
o a:
Cl:
o
CD
~
~
I
~
Z
Cl:
Z
o
Ṉ
z
u
o
~
z
u
TO J 1 ON
ANT-MT BOA
+5
"
c
a
.. ITJJJ..Uc
::: "
6
CN5
5pin DIN
R31
Keyboard Conneclor 1
K80 CLK 1- - B2
K80 DATA 2 ~ Rl
KEY 31il - C16.1 ~C15
[ GND 41~ 51. +5 T "Ti.7Px2
VOC SL:.I .1. ~ Ar. ••
TO ~ Cl'use
KEY BOARD I47P
~ ~ ~
74ACOO 4069VBP 7407
(U) •..• Internal Pul! up
Pass Condensers •.••• O.I>JF x 5
CN2
TO
CN1 ON ANT-RM BOARD
EQUITY m+/ EPSON pe AX
ANTA BOARD
UN I T NO.
Y12620100002A
A-4

1
2
3
4
5
+5 +5
A B c o E F G H
R8 Sli~SW'RI3~:1
47n h l'mUK12 ., .....----....
~I 1.' A~ .8 AC 60 CSPoO CO LV 61
:i I Bri B~ ~ IC 59 CSPDI AR~~~
IJ
I...B R12 RlS ARoYN s' +5 lR~s~tButton +S20K.,7
R' J'I~:~12 RSW~ Al E 51.0 11
+5 111=1 I~ J 4 ~ ~2, SW3 RHIO-' 'I.: l Al 51.1
+55F4~ 47n ~ CH3 RiGi-~.., .....,b RSW~~~~~~~~~~=====~~ &ALE ~~.-.MI\I\rlfrr;A3!-..;..fA2 -7 1.3 1 51.2 51.3
OSC TOll· SCLK 10 I 1.4 0 51.4
C24 CR3 Ill~."'l,T-LS 63 I oCLK 3: I~:: 1.5 51.5
0.1111r48Mtt RM15-4 C4 '" SRoYN 1.6 8 51.6
+S 34 3C OSC 47 .-: :~ C 5 ~S;197
" L---- TESTN Cl'" SS L!" .) 1.9 A
20K RSoV '4 ... '1 1.'0 BSA'O
14.31818 MUHH7 C_Rḷ RM16-6 .: ~:2' 51.11 47
~II-- 14M RSN 56 t-2 ' A,l ~::~
R14 ""IM R33 '~ ACKH 7 1: 1.'4 51.'4
HCU04 472~, 1, AEN 5' : ..L 1 ATAEl6SSTN ~::~
....:. 4 I~" 1 C14'" 54 I~~I-~-"""'!d ~:~ 7
3VOC~ 1r ~C~ TC8 HCU04 E"'~~~~ '6: ;~.~ ~~~ XA2
~ "M 10P ~33P E01068CA ~':~*)4 1A m
fii'i61[)I1M +S-tU- VCC oTR RS90N" XA6
20MJiJ,~L l2 ENAS~~0~~~~~~~~~~i~~~~~~~t=tl~j:j=3]'iGS90N X XAS
'!I"l6 C27r vcc M~l~~ GAATABX ;I,7
470ll O.IJly. ALE x A
,.;" .... l'I))31 C20'" INTAN =",.., XAIO
Ṣ
Cg rcuO'."HC·L!'04 :i::~ I 2 ~~:N ~::~
10P~ *CIO+S 10RN ----.l CS'O" XA13
_+«s;;~:;:;3~;PK~5~4~3 PCLKN '~!~l~
1"" fJ l g:g: ::li
44 PCLKP ;~~ I GNol L~:~
"'1 PWGo SO-N •
r-- 5 5 F-'- CI'" SI-N
~
r=;==='; A'~3~A1 Rc"GAATCK HLoA
+S
RSCPU
R6
GNol GNoA ~'6 4.7K
49 GN01 GNoA 4
t-
~
145·1
15
~
13
012
" "
A23 7 A23 DIS 5'
DIS
1 I :~~ gl~ 4 I 1
:Elt:mA18 DIO
1 :~~ g:~I~~il~'~
AI7 D9
A16 DI
"-l:!.J.il-UUAI5 07
NlJ..:J~UA 14 D6 ~f--I"" ......1
A12 04
All 03
I. 1.10 13 D511~1~1
D2
f- A9 DI
..... A6 ....I.I!.E
f- A5 CODI'IN'!'A
1.4 ·M/~ 4
~ ~ :~ m-M
,'-:~
'---;-;:-.6Z.fRESET
CLK
INTA
+.~S
HRQ
NM'
YCC HLDA 4
"'--C-,-,+ .l.--"'"i VCC .~ ~wr'
O.047 Jl l:d Qm'~li~~~s:lkl
~ C45 VSS PEAEO~
lOJ'F VSS LCC
T ~, vSS80286-1
~ TC~2 68-Pin
.047;1 CAP
CPU
AI7 1.17 E 51.17
A18 05AII
AI9 1 SAU
~~~~I~~~~mm
TC
SAO Al
10
Al ,'4
XI.,
51.'7
1
I
J4
JS
J6
l
"F
:1.;
'r S DEN 'RD
6 I
~ CoLY DRDY 29
~~~'~~,~~::g~= WSONIU)
oCLK
RSTO l'
Ub
10RNlU) X10RN "'W 20Ka8.... .......
Ub
INTANIU) X"'WN .........
17b
~ iöli 2 .......-5
10WN(U) XMAN --.." m A""'-~~ 1 -4
'6b
ISb
CA20CUI RFNO 4 _ AESET EOPbF I4b
I3b
37D
~ ~'~I~~~~~~~~~~~~~~~~=~~~==========~~~~ij~t~~~'~T~:CLK 3 '=-__ . , 20Ka8-2
AEN2 HAQI HRQ PI NS ..:.!-
1.20 HAK I ' f HLDA
~ 0~;""';-3
38D
- AENI lBMEN 1- A7
39D
r+-H--+;:(JRSTN RF2DN ~ l A' VCCl"le,:.'.-4......+S
400
410
DTR OUT' I I_I'
v- A4 OMA2 .- CU
30b
..- 01 A3 o.IJI
~ A2 GNo.!J!-
31b
e_ A18237A-5 Mt!;· 4 .
41b
+S RI C AO(16-Bit) u - +5 ~+S Ub
A20
SCLK
CSPDO
+S ~ voo
L..::~==~:,'~ g:g
+S'f
• AEN DRQ3 i6~DRQ3
ADSTI oR02 ±"""
I
1-
R32
4,!.~n
.-+5
r
~UL-D -,:,R:M~14~-~91~~a:a:t==t:a~~~acLK
20K ~ET P'NS
: ~
5
I:
'!' +5 R"'I-4
+5
+5
20K.4
l" · mij~~
I •.,.' A7:l ilfUlfli~SA::.... Ei
.1" 1., VCC 31 -t-S D: .....~....~+J 17
• 1.5 l 16 -
A4 7 A4 2F C37 7~r;c-;,~ ~'r~ 15 ~ 3
:~~.:~ GNDH' 0.111 +si ... -+5'" :~ ...
B C~A~=~4EO~WS'NlU) :c;:~ 1., D: 20KI' H ..;
WS2NlU) D121 ~~ OMA 1 " .... ~
WS3NlU) OSOl,') 06 8237A-5 '~.... -
, GAA TR F 05 ( ) 1 h.< : 7
RFPO g,,7 D3 40-Pin 6 ,. _
XAO 49 XAO l::::ilJ]~11l
3 B
~ E01069BB
~~~:" ~~~~ 4
ENAS DAKONIU)
5""OoAK2Nlu)
~:~N g:~:~~; I
=~;= g::;: :~: I
~~~ E ~~~:
XAO 0 AI7 I
XA'(UI 1 All ~ 1
~~:~\O :~
XA4lUl9 A21 7
~:~:~:2 1.22
~ x~lUlE Im
I-- h XA8IU)A PCKN ,
--lf~tt~~!!!!!"~"~D'4~8:-~B~it~~~~~_--~1_--"'~l'.~~~111]~
DAEN D2 5 -
GDHN R"'16-S o. DI HRQ ~ 4!§~U
GOLN 53 20K ~ HLOA ~ I 3
~~:~NT~~~::~~)e'~==~+~S~----+--+-h i I L.... ~
0245 1016Nl:;; ,
ALE R39 20K 1 20
~~~A NPCSNi~4~S~~~~~~~~n] J 3m +5 RM7
""Olu) CSRON ADSTI DA KO :>!!-=o +5 6 """:-9
CLK A20G rf==========f~~~U±UU~l:U~9~AlEjN~lp~~ilo~~ 507 .......
=~=~~ D~~~) , 3..( ~ADY +S 4 3
5 ~ ~ -_-~,
+++t+==t~COFF AFIDN
1"" +--r v- AS 2E
470n ~
89 GAATIO 48 I
L..- AE01 2C 01140
I ~~~~N :::~
RSTN STil
'- Ql TM2Gi~~~~§j~~~~i~I§~~~~~~
AMI2,.
LAU ...... ~
~~!:z~-4B
20
19
:~.,--,-""~"'-I
20K.7
1 1
AMI2-'
+5 ::
AuE
~j 40-~:~~ 'g6OR17~!~r~~~~~~,lr~~='iI20IKI"13~~IIIIIIIIIIH:
I-- D3 ~ 44b
~ g~ ~ :::
I-- l!.JI.!SAm 44D
,..J~-4+....l.l.dff
48b
OMA Controll.r ~ +S I~:
-I 48D
r;:mOO~~~~3fJE~~~~~==bJJ _
SOD
t 5 +5
, ..... 1-4 GATEI D' ~ H f- D' 'R6 201114
. '2 rTEo DS ~ ,... DS IRS I
L.t+--iij-g D4 :-- r- 04 IA4 "'...---
03 :-- I-, 03 IA3
~
e
CLK2 D' 01 1F IRI f- ~...---
~ CLKI 3E DO D2(~Ia~!D2DO IA2 +5 ~
CLKO Al INT CAS2H='S RM"7 ~,_
AO 26 CASI SD,1
~
4
S ~ lr::oo
OUT' 41 N
=IN' C·SO'4>-.."j.-h -
oun OUTO~S ~ ."..
~l
A +5 ..::.
RlL SP/EN a ~ ~7
" GATE2 D7 'r-- 7 ~~=t: DZ-4 07 IR7 2S_IAQ7~~~~~~~~~~1b:::-::=d~~-H+R"'II1'Mr'47"":'iin
8254-2 vcc 24 )& • 'f: 8259A-2 +5 ' I I...... -
24-Pin GND
I!l1ö.,. IAO vcc 21 20KI5 10 ...... ;.
T im.r I ~ 1 cs 28-P~~s~ : ~K~
I Mast.r 114
.b ' ,
l-f- b ..... XA9 lU) C~~:: I
t= 2 ALS245 ilt XAI3 CSIIN 4' OS IRS IR:
= '~§'~~lE9U~'11" XD7 XA14 xi~~~~ g~ ::~ I 11
;-- 1.7 17 X06lUl URN(U) DI IAI ,.
'-- A6 B6 X05IU) NC 13 DO
Ilillllll~~I~IX071U) .- A , a 02 1 E IR2 ,. I
'-- :'~D:~ 4 =~:~\ AT:~~46~~~t±~~~t1It1jtt=tL.tt----------~r--------l+-1-t:lE8t'·~O~"~'~HIR~O~ CAS2
f=' Al Il XD2IU) ATDSt", 26. INTA CASI ~
f- A2 12 ' OIIU) ATRW +S l.....J.. Im' c~~~m::::lIml~J
t: A, 11 XDOIU) SPEK ~ C17 ~ Wli VCC 21 +S
~ ~ ::: ;~~ V~\:'~ "~"':71"(C28 mr:~ f1~ ,~3v CN3l1~=UI~~9~ 8259A-2M~~'2
,.... SIlBH VSS.:" O.IJl ~n-~~!~t8"'6~S~.~~..2!.0~·"t::!Ir:1SPEAKEA~' 28-Pinvss 14 .JI
f- NC VSS' ~R23 3]2 1 T ~+KIID INH 5 SP/EN '
;::: """ 470n ~ 4NJM386 GND 7 TO Jl Slav.
.-- .....-- ~ ~::~ CSD2N D' IR6 '"
.---.. :t XAIO CSDIN it-- 7 4~D~7i~-rIR~7~2ISI'I'~~I~~1~~~~~_J
C '=' R37 "Ir ,r ONANT-LS
.--- ....., +S BÖÄRÖ' Int.rrupt Controll.r
i- i-, 910n
i- "'"'
3~
0 tm
~ 1.22 8 LAU
lllJllU~+~s~EIj~~n RF"'ANC6 t:~~ LA22
..
C25 ~ ~ Ui ~~~N A~XAR2~
O·'J'.lh ;~~IRN :=:
"'EMWN XMAN
10RN X"'WN
10WN XIORN
7 :~~N X~OM~~
DLA SIHEN
GSAN XIHEN
L
TTHTttt1H'-jttjj±tt==::::~ ALE GSRWN
OEN 1C NDII
~:.- 8~g: N~J~
,~ GNDII NAI' II!
" " ~~ N:~~1f1
GAATCB
A
A
3Sb
lb 2b
26b
49b
SOb
320
340
360
4Sb
46b
47b
350
450
460
470
210
290
34b
10
20 260
270
490
11b
lOb
9b Ib
7b
6b
Sb
4b 130
120
110
100
90
10 70
60 50
40
30 20b
29b
21D
20D
UD
IID
17D
"D
15D
140
UD
24D
UD
Ub
24b
Ub
22b
21b
36b
37b
38b
39b
40b
22D
OWS
+SVDC
+SVoC
+ 5VoC
+SVOC
+SVoC
IALE
10CHRoy
AEH
RESET oRV
OSC
oRQ3
oRQ2
oRQl
~
r CLK
GND
GNo
GNo
GNo
GNo
SAU
SAU
51.17
SAU
51.15
SAU
51.13
SA12
SA11
SAIO
SA9
SAI
SA7
SA6
SAS
51.4
51.3
SA2
SAI
SAO
507
506
SOS
504
SD3
SD2
SDI
500
IRQ7
IRQ'
IAQS
IAQ4
~
tem IAQ9
nnißIi
1/0 CHCK
DRQ7
oAQ'
oAQS
DACK7
DACU
oACKS
DAQO
DACIIO
MEMA
MEMW
GND
~ SDIS
SOU
5013
5012
SDII
SDIO
SD9
SDI
LAU
LA22
LA21
LUO
LAU
LAll
LA17
li'iIID
IAQ1S
IAQ14
IAQU
IAQII
IAQIO
SIIHE
POWER GOOD
+SVoC
GND
o
a:
O!l(
o m
~
~
1
~
Z
O!l(
Z
o
N
z
u
o
~
z
u
JCN6
TO Jl ON
ANT-MT BOARD
6 """,,4E
6
4ND
I
2~1
4E
."H.
AZ: 47DtlI2
4E _~ -r.-sK,.vboard Int.rta ,
~ 11.... V'" 10 f"'"lIInA' -,- XlAL2 I 0' 07' C. ~~~~~IT-~;1I
:g~ ~g 16 R21 UM
AO 8)42. D5 ~g~ OSCI 2 ;~I TO BATTERY 1.4Q.,.
..rsWl 3 -2l'lm\1r 1:13 fÜ-.12 PIS PI6C4al5lllAg;~f~igigE~~~=E~3ijAD3 3F D2 A02 °SS~ I!, UNC I 14 MA19SlZ \.A38 ,~60K .- .....
l'I)) P14 01 Aol CKOUT 21 NC 01 02 CN4 HIli--
CN5
NC PU DO AoO VDD 24 6V J2 I cO:
5pinDIN R31 lOKI2 NCU P12 P27 3 ;-- RnS-719 iJiQ --'!!.E..5~~19 J ;;:GND I 3276:K
K~yboardC t ..........._ ......._+5 NC 27 PlI PU;-- ZOK ~- Rßn 2SBBol6-- L. ~~L.
KIOCLK o~nec or I~ I A30 +S KIDCLK NC J ~JgTO ~~~3 NC OIF f+s4D6 ..-!'f ~s 3D PS IK +5 --er-' ~~~~ C12~
::~DATAJ. _ C16' TC15 5 TEST! P232~NC ~:!~ JI:Rlw 1•.,;~CI1 A26 R24~ •.tC4 • 27P,
I;;:; -..........- + ~40 ~ PP222122NCA20< :;;.~ 146818vssI!L 0'0047JlS1K~'OKf, ''''16VIOJl
[ GNo 41~h SA +S~ ~7PI2 p.iIr
voc S.L T "Po " u
(Voo) P20 '" 24-Pin· A25 Ql ~2 40 13 ,.
Ta Illr'" n - 55 RESET .4 .. * OK "-.
TC14 C38 PAOG SYtll:. '~' D:mt CMOS & R.al 1 .Ir C ,81 1a
KEY~ARO .~ ~1~~~ .- ,o-p;n'~' j~!~~~~~~~~~~A3~:~tttttfftL~~im~i·~iC~I~O~Cik~~~~~~~-~'~'~~~~~~~~~~~~~~~~~~~~~~~~~~tU
:(!p
~-I>-
74ACOO 4069VBP 7407
( u ) .... Int ~rnal Pu 11 up
Pass Cond~ns~rs ..... O.l}lF. 5
CN2
Address : C40 '0 C44
(not trac~d on aboy~ diagram )
TO
CNl ON ANT-RM BOARD
EQUITY m+/ EPSON pe AX
ANTA BOARD
UN I T NO. Y12620100003
A-5

.
1
2
3
4
5
+5 +5
A B c o E F G H
RS Slide SW 13 ~
470 h ~ 4.7:. 1 2 q....----....
r l W Al A2 Q A3 Q AC I 60 C5PDO COLY 61
B B DEN 153
2 B~ ~ ~ BC 59 C5PDl AAENN
_ ~ A12 AIS AADYN 4 0 +5 R B + 5 20 K .17
R7
' Jl~Llftr :.~.x2 A5W' 5 3 esel utton AI
1
E 5AO ,'1
~
+5 p7A 14""""""'" CN3~""""':! ~ A5W~~~4~~~~§~~'~~~~~~~-------;u9'9 5Al
·~..'aGi-..en BALE -7 3 A3 A2 1 5A3
OSC 5A2 7011 5CLK '~.: ~~ 0 ~~~
14
+5 11 r:T"" 3 ~ ~2 SW3 RH 10.91111131A
O.lJl 7 48~ RM15-4 3 e SRDYN '~: :~ 8 5 ~:~
+5 34 05C 47 4 AB 5Aa
" '-- TE5TN Clt04 s§ ... A9 C 5A9
20K • Al0 B5Al0
14 4~~ RM16-6 A5DY 14 ~. 113 AllSAll 47
.31818M ..., 'J4-M ASN ~S]6==============l--, .. ~ 1 : g 555 AAA ~'4~ 5~
R14 1M R33 0 ACKNt 7 A14
H;~O\ ~:2~2 1 AEN~§L!l +--+__+----.: 1 ~HTN ~~a
~ T v .. C14t04 Et04Et04AN 54 ~ TCC ::~ 7
3 VC1 ... .... C7 CS HCU04 COFF +5 TCC XA2
OP ~ ;l; lo;R2 ~33P E01068CA 10 ~.l~~.. 1 A m
'fl'36 C27 vcc to4~l~~ GAATABx xA
A 9
a
47DA D.1J1:!: ALE
,;;. ... ~31 C20t04 INTAN ~ XA10
C9 ~Hcul: ''HC-lI'04 ~:~:= I . .-+++-+-l----4

A
B
c
D
E
F
G
H
J
K
L
M
N
o
p
4~3 ~o5
2
3
4
5
6
7
8
C24 0.1_
1~~~~~~~~~~~i~~~~~i;;~~~~;~~~~~~'~'III~~I~~~~II!!!!!!!!!!!!!~~'IIII!!~~~~~~~~~~~~~~~~~~~t~[rI~;!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!II~~~iRj3~2'4:7~0lI!III!~~~:E:~:~~~
35b
~ ClIPDO R2 IK --olb
71T Sc C~ :~ --------t-+-t---......-W"v--~~,s:=8 ~~b
~ 13CI ARDYII RIWP" .. R4 05 .S 201(-17 I.,.ft I L-======g I --o50b
[1

2
3
4
5
6
7
8
CI4
0.1_
r
I ~
A
B
c
o
E
F
G
H
4,.m3 rw--- .a
1~~i~;,~~~~~iii~;;ii~;;::~;~~~~~~~~~III~~'~~~~II~~;!~~~~~~~~~~~'!IIII!!~~~~~~~~~~~~~~~~~~I~!t]~~!!!!!!!!!!!!!!!!!!!~!!!!!!!!!!!!!!!!!!!!!!!!!!!I~~~~Rj3~2;4:7'0Cl11~~~~:~~5:~:~~
03Sb
rin c.-oo R2 IK --0 Ib
~ C_I ARt:1II .~O I .& ....a 49b
C3Cl RIWP 3R...t8utton 6_ E IAO ~ 32.
m~ ~: .a~~
m ARDYIl :=: .a .a ~-17 ....0 (rR~~~~~~~~~~~~~~~~~~~~~i~~~~~~~~~~~~~~~~~~~~~~~~~f~]~~~~~~~f~~b:~;I ~~~:
4E All
a"
"'7'-
T~
62 ~ vcc VCC llIIY" HL':: 1:l t-S·lI:;;;;;;;==~=~=++W 54
__"'"1
CI9 IöCii ~;; .~-.
I VII PEREQ
.0
'----I~ClCl30~~;~N
.-.....-=.=10V$I
VII
~ :~g~
:~:
Illilllllllllllliliil~i~~~~~tJP:JjC!LK!2~;~
...... ~t~~
~
:~ ~ ::~
~
IIlT ~::~ Ht-- SDI& ._I R..,M,..•.-.... ::
..o:~
:~:
68-PIn
IIITRII ITII -;}- OUTI TO~ 2. INTA CAIO't'11~2-c:;Hh 14 8 JW ....-.... 25.
SI; ACKIl E 0UT2 41 oun OU -& ~ RD SPlEN llL- I _0 13 1t:~~~ 24.
J,.. ~ c~ft 80286
: EIlAI DAKOIl ::? VCC ~ • XDO ClllllktJ!~ 1XDO WR 8259A-2 IRI I.a+: _" 20K"s:~ -& ~ _....-.... 23.
~CAP
0.047.
'--+-----11"'0;-1::0 I g:: ::;:In 34 ~:028-Plnvcc ~ : RMI3 ~ 10 4 .....,...-.... ~:
I C_ 0 DAK41l GIlD ~ 0.1 I Ci C3I " 93 .....,.....-.... 23b
lIERIl 9 DAKIIl 11r VII ~ 82~-.-....
- 2 DAK71l T1mer 14
17 22b
2
RM4.S CPU • I E 10EN I IMosterl
3o. 20K" 36b 21b
j.o.e ~r",,=-----------J &IlCIN ARFHIl .., 37b
D2 XAO AI7 ~IIJI ~::
': : ~~-::::"1XA3 A20 :~:
~ DO
g; XA4 0 All .a RI7
Nurnerlc., Proc...or Exl. ::..f., ::: 410Q
1 "oe DIO & Dio - .1 Dio 101& XA7 IRII .a
4 E v::=-="XAI ~CKIl .a RIIII R2I IOK
0.047. k =- ~.
E :3~ ~ 2 1 SW3 ~f~~~~r---f-~R"~·:"fi~~11~3~AI 0 lAI 13 lAl! I .a I'
o RlWIl ~I~~~~~~~~~~l~~g~ ~ AI I :: 14 8A3 IC-I l~~;;;;=====8 33.
,...!! ro;c I IIALE -7 A3 0 ~~==!l~=========::J 11-To- fJm~~:i:~8:~~ XD. AOMB89237A ~ C8-BIlI :~ 9
0.1_
3 1A14 1A1& 8b 7b
;T;. '""" I'-"- GA ::~0IFI4~2__~XAl~IO \I XDa Il D& 40-Pln 8 _ 1A.2::
'"". ~ C20II lIEIIRtI IIlTAIl 18 2ALE OE-II
-& XAI2 XAII 04 ~ ~ ColG XAI3 13 XAII I XAO RF~O
XAO 2K R7 -&............. ~ c~lJll~E~!IXD~'~"iD4 XDI D3 :4·~:!Eij 7 8 SAlO lAll 4b 13.
.,J,. R8 O.C r2 1 D2 HIIQ~ ,~1A1 12.
4_= 10WIl 40 41 :: ::::H ~= RIII.-& -,I,- 2K 'l. .& t---< XD~ ~ If ~t:~p&!j rr-- 1A7 :~~
-=:f~~~~~~g~3~ c't.:c~ - XAII 111 GDLIl TEITIl ~&I3~~2OK:=~=.~O~ t_th L-tt-----,-=....lP"t---i c:. ~ t---< Ci HLDA I ......JW....3~11 rr-- 9.
I== =t~n~~::;:03_R_4 --1t-1!"-rt-., - DXA :::- I::: EI t=jt~lU1LJ~~~:~:~:JI~R~:2~~~FS~W~02~·=I~:.~t-;n:;;;witii~$~$~~~~=~~~~~~~==$~ w+ -;;&j;0~2OI-':":":"--+-D~:: 13Fl g: I",,~ :: o:g~~~::g 14 22P -;J;32.~':' ;];27P ~ ~
IWI
S
L.! ~14
CNS IlC:' -I DO
DI AGI
.-
CKOU
VDDIZ4
1:::1 llC IIA19_S
......
02_
.V J2
CIl4 C
R
Spln DIN All '01( llC :'I /
r
~112 P27 ~3I
.•- • ,,-, ••• • 11 ~ IRQ CKFI ...... I... T RIS 1 ~ DI D2 ,..0 \
K.yIlo.rd Co_ct.r GND I
12opJC2 •• llC 2 ~II P2. .0 IOK. 1I CI RRT r.... 25B808 Q2 7tr
,~C4~I_~~"~!:±;RIOf;:~I'*==.a=~_I:~CL~K~:;~IlC:]~1~IO ~2o n llC ow .a .' ~ AB (301 PI.-- IK _0 R2.~ _
CN2 TO CNI ON ANT -RM BOARD
[ KEY ~: ~~~A 3•.';: ~ I< ry ...: DATA I' i~:i? ~:; 24 li~"'" .... 1lC Ir"l- ~~W CII olK R24 C4
J!:1~10 .a P22 23 1lC 110.. 4 24-Pln VII ~ 0.0047. L
-
16V 10_
4Ir, " ".. &A .a l;J, ~40 VCC ~21 22 A20G 146818 7
VCC S,:::
R2& lOK
~~ *0-m 47P r DO '. ~~ ~" IOK 01
0.1.ti 74ACOO 4069V8P 7407
~:s40-PIn ls _11.1,:;
J. 8042 ~17
ro~~ 71=~ ~ ~ ~~_~~II~~~~~~:::-~~U~ij~~~C~M~O~S~~R~I~O~I~T~~~e~C~I~O~~~~~~7i~~~~~~~~~'~~~~~~~~~!~tLJ
=-!I~~~~~~jt~~~~~i~it~~~;;;;~;;;;;;~Jkf~ttt~tt~rtt~tt~I~~~~I~~ ~ J o~ ....... ~ ~ =
r-+++-+--"'4!'-1 COFF RFIDII I)f,--, ~::j:IM;::~:: 12EI -'- C33 41.
r++-lr+t--,---izHI~J" OUTI I [,,- A3 H0.1. ~?:
L
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GAATIO I t; mir ~t gj~~Hlf 5 ~~:~~~~j'IRRIQQ4'3sj~~~~~~~LU~===2OI

I
T
MD
111
I" 13
12
• 11
10
9
•
."3
A
....
B c o E F G H
, •
11
IID7 •• 11
IID7
" 3 0
2
1 0 •
2
3
4
5
0
a:
Cl
0 lD Z
L>
Cl
I-
Z
Cl
Z
0
'"
L>
Z
JRAII~ _o4~---------------------------nr~~~~~~~~~~~~~~~~~l~=l=+-..,
- ~ä 8
L-1+-If-Hf---------1f-+t-+-+-----------=-=-----!..:---I-iJI ~
~L~i~~~=======::::;_,
11 A~
r;:::i ° ° I
~
a°
111 ......-Il 111
-4A
D.I,,!'1 VCC
.a .11- 5A
vcc
.a;.0.1' -"_ IA
.a O-.I~,VCC 2A
0.1" YCC
.a -6A
0-,,, ~:VCC f-
.a 7A
Y! - DI h
D.I"FlVCC
.a eA
DO
I--
DI
DO
f-
Dil!­
DO
I-
DI~
50
~I­
- DI~ 12
DO ~-4--------==1
0.1" vcc 9A f-
11•• -M
c.=~~~... ., Be
:.h
I--
v--~"""*'l. I Dl 1I
0
t==:::;::j'~ 11 ~ DO .. 1T"1 ...... ''=-'I
l----~'*l; ~ DI ~
l----~_!l'_l 2 I tfI
f ~~~§~~0 ~
...--'
m Dll!- •
4
14
13
11
•
-
Icl./ VCC
" 19B
~ OE M
• I
5 4
3 4 6
: 4
B
A7G
I --H-.f0!!...,;I5l' I
... b-!!.. 0
~W
~ VCC
0.1 20B
" GM)
M
~
• A7 e
Iil?~:OE 11 : B~
3 : ~
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XA
ANT -RM BOARD
UNIT NO.Y 12620300000
A-9

A
B
c
D
E F G H
T
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I
14
13
12
11 .....
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12
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9
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11 6 11 6
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9
10
11
12
13
14
15
16
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(12MHz)
EaUITY 111 + /EPSON pe AX
ANT - RM/RMA BOARD
UNIT NO. Y12620700000/y12620900000
A-10

PG
TO
POWER
SUPPlY
UNIT
NO
CONNECT
CNIO
CNII
~ CNI
CN2 .5V
r.N~
1CN4
.4~bl
1CN5
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lOW GOOD
CN6
~2
.5V
1CN7
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~3 CNa
.12V
.12V
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::::
ICN9
~4 C6 C4
-12V
-12V AI
2
GND ~
!~3~F ti 33/lF~
3
GND o-L-.
'16V r; 16V 4
5
GND o-L..
6
7
GND o-L.. B
~4 C5 -.
-5V
-5V 9
.5V
_5 10
fi 33/lF 11
.5V ~6 • 16V
12
_7
13
.5V
.5V
- 14
•
+ + 15
+5V
GND
Cu.bJo; Set
+5V
GND
GND
.12V
_l
-* -
33/lF 16V 16
17
CI C2 C3 x3
71r "I,. f,- 19
2
21
2
23
2
2
2
2
2
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29
3
31
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2
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5 -5V
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6
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7 -12V
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9 +12V
10
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11
3 12
13
14
111
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16
17
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11
20
21
22
23
2
2
2
2
B
9
10
11
12
13
14
111
16
17
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01
2
3
4
!I
6
7
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I
- 10
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L..-.- 12
13
- 14
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16
-
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I
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S07
S06
S05
S04
S03
S02
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SAII
SAlB
SAI7
SAI6
SAlli
SAI4
SA13
SAI2
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SAIO
SAI
SAB
SA7
SA6
SA5
SA4
SA3
SA2
SAI
SAO
IROI
-
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OWS
b
2
2 a36 _
3
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2
3
4
11
6
7
17
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a
a
a
a
a
b
a
b21
RESET ORV
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OR03
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REFRESH
CLK
IR07
IR06
IROli
IR04
IR03
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T/C
BAlE
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SBHE
lA23
lA22
lA21
lA20
lAll
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lAI7
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-MEMW
SO B
SO I
SOlO
SOli
SOl2
SOl3
SOl4
SOIlI
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-IOCSI6
IROIO
IROII
IROl2
IROlli
IROl4
-OACKO
OROO
-OACK5
OR05
-OACK6
OR06
-OACK7
OR07
-MASTER
CNI2
TO CNI ON
ANTA BOARD
DESCRIPfI()IIS
Gable set #5BT is not installed on the Y12620200001.
cPtion slot locations
Unit Code 8 bit-bus connector 16 bit-bus connector
Y12620200000 CN1, CN7, CN8 CN2, CN3, CN4, CN5, CN6, CN9
Y12620200001 CN1, CN7, CN8 CN2, CN3, CN4, CN5, CN6, CN9
Y12620aooooo CN1, CN7, CN9 CN2, CN3, CN4, CN5, CN6, CN8
EQUITY 111 + /EPSON pe AX
ANT - MT BOARD
UNIT NO. Y12620200000/y12620200001/
YI2620800000
A-11

2 9 7 4 8 102718 24 23 22 21 17 19 15 16 20 2629 28 25
CI
0.1
~
R21
R22
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6
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7.5K
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100
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C5
C2 C4 R3 47K 200
0.1 1000P
~ PRECISION ADJUSTABLE SHUNT REGULATOR
5.IK
RI5
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RI7
510
7
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3.3K •
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, lOK
5.IK
R36
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-
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100 R39
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:
09 : , R40
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OUTPUT SOCKET
®
RIII CI06 O.OI/lF
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10 ~W
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0106
BUZIIA
0111
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FIOI
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RI05
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CII3 CIIS RI23 CII6
CI19
+
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CI20
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®
EQUITY III+/EPSON pe
ANPS UNIT (ALTERNATE
UNIT NO. Y126509000
AX
POWER
SUPPLY)
A-14

-----A
B C D E
F
G
H
T
liiCi

T
DACK2
2
3
4
t-
0
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CJ)
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0
5
0
t-
Z
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a..
0
T/C
RQ 3
4
15
7
RESETDRV
iOW
Tmf
AEN
SAS
SA8
SA7
SA6
SA15
SA4
SA3
SA2
SAI
SAO
SD7
SD6
SD15
SD4
SD3
SD2
SOl
SDO
A
826
v 827
8215 8
824 C
823
B
:
~
821 C f'tl,0
82
R34.7K
A
c
Sp•• 7407
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D
7C 1I .... 7C ... 12
.... I>'" Ir
"'8
R2S 2711
R
E
·4
• 15
F
tiTIf
33
RTS 32
sauT
11
CSOUT 24 NC
DIllS 23 NC
Ne 2S NC
.15
G
H
Spar.
LSI215 LSII'
71518• 13DI
18FI
11581
~ ~ ~.
13811
4
7
3
~
cO:!
EIA DATA TERMtiAL READlY
EIA REQUEST TO SEND
EIA TXDATA
SIG GND CN4
EIA CARRER DETECT
6
EIA DA TA SET READY
8
EIA CLEAR TO SEND
• EIA RtiG INDICATOR
2
EIA RX DATA
DATA7
6
15
4
4
3
2
I
---.l!.....
0 ST~08~
AU 00 XT
TIITT
~
I" .SLCT
12
.PE
11)0( RR"
115
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o
il:
il:
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n
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n
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Z
o zz
",
o
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o
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o
7
GND
81 810 831
~
8
1
+40~
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4.,"$
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L. __6"o

A B c D E F G H
T
r---------------------------------------------,
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r-.....t------......
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17 18
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C28
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05
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VCI
CIO
12
2Cext
VCC
82P
15-90PF
LG 80th 74574 s are in the same package.
~ The MPQ6700 is a quad PNPINPN
complementary pair transistor.
2
D2
IFC
2FC
L5629
VCCO
RNGI
RNG2
(IG)
GNOO
3
GND
! TPI
RI5
1.74K
1%
RI4
3.48K
'"
+ :One Point Earth
6
EI
E2 GND 9
CI5
VC2
(VCO)
ICext
4
IY
2Y
5
IOOP
15-90
PF
(2.0M)
(204M)
4
WINDOW
RD
WINDOW
RD
ALSI13A
GROUND PLANE
---------1---------
_____ ...1
3
RAW RO
RII
4.7K
,......-.-------..---+-------.----4l----J~ +5
RI
4.1
2SAIOl5Y
02
2SAIOl5Y
01
5
RI3
3.3K
R8
R4
SYNC
6
WCLK
VCOFB
Spare
TL081
7
DI
00
AO
3XVN
WR
3F 4
00
3F
-DLY21500kbps)
6 -OL Y 11300kbps)
3F VCOSEL
.-:....;",. ..:....:....._...:.;:13~ 12 -DLYOl250kbps)
LS74A
8
_l
13
12
RES
4E
.a.LS27
EQUITY 1II + /EPSON pe AX
SPFG BOARD (SHEET 2/2)
UNIT NO. Y12720100000/Y12720100001/
Y12720110000
A-17

A B c o E F G H
1
2
3
4
5
6
I­
ọ
..J
l/l
Z~
Oz
i=u
a.
o
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o
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l/l
ZN
Oz
j:u
a.
o
o
I-
loc~g~
R 21
100
1%
COHA2l-1__----.
6 3
~ 4
4 ~
3 6
2 7
1 8
01r
+ 10CHRDY
AEN
10
11
SAU
1&
12
13
17 '4
16 1~
1 ~ 16
14 17
13 18
12 19
11 20
1 ~ ~l
~ J l..ft-
ca 22p ~~
f
:;= ~10f04HZ CRI
7_ i~~ ~1oI
SA9
!I~~!;~~~~~:;6~-!J:~~~6~~~~~~~S~A~2:~1~
GND ~ 7
RESET DRV
+~YDC + ~
-~YDC IRQ9 4~ CI6f'
100" 16Y
DRQ2 6
-12YDC 7 7_
OWS !
+12 VDC C>---?-,.----+-+l---=t==:l f
r
+5
27 I- R13 R14
Pg~~~4'7~KX2
14 Ht--uTKIlJ'nn",,---, + ~
15 32 NC
1633NC
lR15
17 ~4 NC • 4.7K
TEm Pi-LJ--....----++++-+----c
WAUP 0
W1l
A~.~
07 H 7
6
~
4.
3 4
ba,t: 2=:i=~
HDO~
+~
l,-_......;4;.;',.-I S07 I
61
~I
4
41
31
2/1
1 •
O.
HD7
6
5
4
3
2
1
iöi
row
&ALE'
11 71
1 1~~~4
SAU
7/1
Fi5CS t:>~: NC
LNCIi P NC
töMri P:~ NC u
7 4
~ 1
4
3
VCC
GND
II HRST 1: 4 +5
1/1 +5 12K
0/1 YCCI f-U...
~%
m • YCC2 f-i'L-
CORRD
C32 1/4W
ERR 0.1"
ALE GNDI I-#-
GND2 f....U-
+~
7 wn7 •._"f 2201\x~
1/0 ~ ~H!QJ.D7_Jjl~~DO:~7--"V:;:CMC~Cl9 r---------__"!9:::~~~~~5~09='..:3C--------------~------...:5+j4~3 ~2+6+-:t-.~-y,_·---J==~'~H53 /RWC
4~, Eg~i~ Ir-+--!'!-I ~ GND Ho 0.1" r-----------.-.~5~""-'" ~ 8 4 HS2
TO J 1
ON ANT-LS
BOARD
l~~~'~m: SC~33~l~7-~'~~~g~f~~~~~~~~~~~~~~~~~~~~~~~~~~~~~q+==;l:7~A~'===i+ij~~===~~~~~ WG
ADRlg~~~~~ 3~ B~DY I~m sc
6C i WF DRDY 6 t2
~ TRKOO
~==!:t1 NC 3~ BDRQ L_~4_"3L-.....jf++_+-I-I-----t:=::ti~ -
H: NC ·c SOHLE 4E , .-. C 6 1 WHT
4 ~~_..;4--1h1 4 5 '1>~-------------H___1~--------+~+U-----4==t4~ ~
3Hl--+--I-J WD2010B :~ KEY(Plnremovedl
ii~.~7~~~I~*================~:=:~==~F==j2~1~~R-05 rl---------.... :~ 5C 11 17
wr 18 '?tm~ 6
H51
OE I BCS STEPlj217~~~~f~~~~l I (INDEX) ~ 21 INDEX
es 10 .A_ 11
~ 12 7~ 13 1
2016
(loons)
6F ~
--ll
WDCS
H1il
'mj
HAI 4
~
WAUP ~C 6
WAUPL !-L"---~-"'~ ,. 8 KEY(Pin removedl
I Delay L1ne R6~ r~iF ADJUSTI-''----+,...I-%--'Rv.~1I._t ~~OP ~~PI I I rr===~~~t;10m NC
I ~VCCJNA''0K.'101,ADLYDRl r61~ ~~Kf04VAf04I09 1 L ...J '~ Wf04Ff041+
Cl:: 38 4 TEARLY 20Y. 1/4W,.. 1 r -- - - -, Wf04Ff041
0.1" 1 F ~o '0 7 TNOf04HW 2~Y • 16
I
t-1 GND ~~ ~t:6~l PUf04PI-2"'~'---_ .......:~~.\'.'iK,..:'-=.Y,.:.. ...... D2 I L~II~4+t_"t_;::=::t=~~7~ R
I ... t~~ TDRUN C3 1 r+++---!1~3~1-< g 2 _I I ~ I g R~~~l +
4700P Rl 1 I ~:l II~ R9~ I
WD10C2OA 5 Y. t---'\Mr-. - 7A I P--'-'-',++"''+--'
I VALOR ~901\IT ~:OP I" Il.... 1 100 ~ %
I 2H '\O~'----..........-_a C2 1% 1 S% I 9IV" 81 f-

---------1
A B c D
2
4
CN2
CNI
AEN
1
lSI25
I
I 3 16HI
1-=-----.
1',i9J 2
r'!< -G
7fT
I Ne ....!!c MCSI6
,1---------...l6~0~,.OCN
, S lA23
, 22
8
I
DIR~
9
8
--------1-- -I
'" 21
~ ,20
• 19
18
17
.;-_;: 2D :-I SAI9
1,.--_~'4~ 18
1.--_.,3 14 17
1,.---'1''''-1- 16
20 15
1,.------';:;..1 14
13
12
11
ID
14
I:!'I
t"\..(,>;;A;;I... 1 ++-1-__-+_--.J!>:I.I A AEN
BAlE r.q.::8:=2:.8 ++-1-__-+__.1!2l
- BAlE
~IOW
,
I
I
I
I
I
I
I
I
II
SAO
11
10
&
6
D6
10
987654321o
R
S
E
T
18 I.
R S
S C
E L
'----i1--'3iL.1 SAoT K
r- +~S~DSDIS
r-- -+-:i i~
:m 10
___--l,...~iIi:. 9
2 8
.D+
27ta;]
vv
D D
D D
ISH)
G
AMYV
X
NC
(E02055BAI
I A
M 0 D
C C A
E E E
I? C) \J
DD ...4 D3
M 1 A
C 0 D
E C A
E E
14F)
G
A
M
YV
Y
NC
11 111I
G G G
N N N
D D D
MSA t'D~O:...- ....
~
ADI5~
ADIS~
14~
13~
12~
II~
'O~E
9 4
8
~t!!=::
5 41....-
4 ;..-.-
3 :...-
2 L......-
I 6~
o ~
J;; ..u 17
r-----I--------- ...D 16
MI6 ...2:,::8'--__+_--I
v-t-+
IG 0
2 8HE
4~ S2
r _--+-+_---!2~9~ 30 HSEL MPX
'---++--'-=;31=-1 MALT
rl--+-----'=:+-! DCLK
,..........!!. CCLK
~ DSEN
~ 34 CUDS
~ HSYN
Ir-ü- VSYN
.......-+_~7-=1!
96 VV VV
~ AI9 C C C C
97 C C C C
...::.!. 18
IDCK
~ DCLK
78 MALT
L.-_~I--_.uq MPX
L.-_--I--I-__~..lJII HSEL
~!! CPSL
....---+-+_-II~C8M
1
A 9
ADIS
14~
13 ~34 10 14
12 11 13
11 I!> 12
10 13 11
~ IIR 10
9 ~39 9
~~ :~ 8
~~ : ~
4~ 21 ~
3
~ 1'--~2-i::t2 4
2~ 23 3
I~ 24 2
o :48 : 2D 1
MONO ""D.::;.2_+----.
MI6fD:.:,I--+--+--.......J
S2~
~~
C8M ......... 32=----~....J
31 B2
WA IT p.::-'----+------===------'
....-+- ---I-+_~1~9::.{) RSET
---+-I-_~24:.:'-rlWAIT
-n'.::: S2
21 SI
20 SO
8HE
t----"'Il.....l ADIS
14
13
12
11
10
9
G8HE f..h.)-.3_0__-t .J
MONOt-
29 ---.
5" SI
7 SO
RSTN f:1...)-4:.:9~t_----f---J-Jr"1l-~----~~~-=.-=--=-~t1===J:14~~WAIT
EXT 131
-----+-+-----lIL""-1 RSET
r C8M
l
.--__-+-+-_.....;2~6;.1CSEL
7lT 27
G G G G
N N N N
D D D D
41544
NC
IOO~S
12E)
G
AMYVo
(E02052EAI
T
E
S
T
111 j..iaelt:=-------------........
RAS J,. ....r6;,..;;6
_
_
IRG.
I"'.....'
t!m.r---e 3.3Kx6
VH
BGRI
1"21. 11 IC~S 411'7
k iG 16AI
~ 2G lS244
I.
77­
2SCI815
A
Y
~2.147 1111 '~ 120P
.-.I---lC~7-1
C\I" 0:0: It)~ 0: 0:
UI L9 CN3
;;;:;;: 61"\
L3~- 3'"
L4~ 4_ R
U'I .JU!. 5~ G
L8 ~v 1~ B
L7 -,J!,!!; B~ VIDEO
L6 ~~ 9~ H
{~ V GND
FG
~I
-oR
L..- ~O G
83
no
".'
47P
b..-------4I
~B
L.-----~~D V
~H
CNS
2
4
6
8
10
12
1-13
CN4
(ö) eOMPOSITE
t2.~IDEO
Jr
I
9PIN
D-SHEll
eONNECTOR
,----- - - - - - ---
I HV8GR I
I 1 sTe12 1~411111 11
I t-
~I!>G • RII
,'17 ""-- 95
L ~
+5
A
ose
.5
.5
GND
GND
GND
_&30
10_/
/IOV
0.1_
MGA BOARD
UNIT NO.: Y12720400001
A-19

*
+5V
-r
,,;I: R2
01 ~ J27K
+ ~ CI
:;J;. 47p
4
MPU8
M5
,_ 2
9 RST/VPO
"'J
+5V
LS14 T 31 EA
r--_I~ M3~3~ ...;;1_2"'INTO
'--- -+-~2
Jumper-2 13
6 ~···V - INTI
XTI
19
C21.
IOOP~
XT2 ~1...:;,8_"""--I
C3 ~
IOOP .b
6MHz
I
~
5
AIS AI6
EI6 FI4
AOI BOO
012 013
CIO CII
C02 C03
B02 B03
BIO A05
F02 F03
F09 FIO
EOI E02
E09 EIO
.,~ LS125
019 EI9
CI8
C06
B06
BI7
F06
FI3
E05
CI9
C07
B07
BI8
F07
FI5
E06
EI3 008
EI4
EI8
EI7
PCJ-9
~
~
PCJ-IO
~
~
PCJ-II
~
~
E20 PCJ-12
-
~
020 PCJ-13
C08
B08
BI9
F08
FI6
PCJ-14
~
~
PCJ-15
~
~
PCJ-16
PCJ-21
~
~
PCJ-20
E07
PCJ-19
....,
009 PCJ-18
~P35
PI7
PI6
PI4
8
13
7 10
5
9
M5
~
9
7 rr LS125
P 11 t-2 --+_10~
,..-:.1.:.,.1_
,.....;:8~_.-
8 _ R7 180
...., --..
PCJ-24
R4
+SV
.!!,KT
......__+-_--+_--.1r l--_-.::::::....-__-()

A
B
c
D
E
F
G
H
T
DISK 11
SENSOR
PKG
WRITE
PROTECT
SENSOR
USE I
I 4CI
DSX I
I 4tl
I RDlE~ 1>--.....'/""1
,
2'
R46
330
'"LEDI
DISPLAY
LAMP
390
2
RI7
47K
O.l~
r +5F
RII
12K
TP&
CI9
=.&F
R43
IOK
R44
R45
IOK
HDE2
I 7HI
SPINDLE
MOTOR
3
INDEX
SENSOR
DRIVE SELECT 2
DRIVE SELECT 3
---,
RI9 '
330 ~
R20'
,..~)($!."'_~,>USE I
;SX:~: ~:P XL RU
~5 CJ ::
TP7
330P
R93
lOK
':IZ~HI 1>------"''"1
IHDM 1>-....----'-'"1
..
11 2
0
... 0
)(
... '" ! Q
II II
..
0
i
> > ... W
LAMO 43
SPFI
41
PH41
47
PH31
46
PH21
4&
PHII
42
HLDI
50
HLFO 49
P3
17 r::::- --,
12 , 4
I
11
: STEPPING
& 3 I MOTOR
10 U2 21
I
2
4 I
JBL 1006 P 27 I
11
__J
3 24 DI
I 19
FII41
HEAD LOAD
SOLENOD
4
5
HEAD LOAD
/ IN USE
MOTOR ON
WRITE GATE
NRITE DATA
R77
R71
R70
RIO
3K
3K
&.6K
3K
liDO
I
TKOO 40
PRn 41
RDTO 9 7
RDYO 1----f">RDY 0
I 7AI
DCGO
39
RDY I
I lAI
IS2837""
DI4
INDEX
TRACK 00
WRITE PROTECT
READ DATA
READY/DISK CHANGE
6
7
8
1
STEP
DIRECTION
SIDE SELECT
MIGH/NORMAL
DENSITY
DC .5V
GND
GND
DC .12V
.&F
19AI
R91
"11
IK
LAM2
RI4
lOK
,..---------------r>.&F
,..-------o·&S
'--_-OO·5SF
...--------f>.12S
L-.....--D .12SF
RII
3K
RI
RI3
5.6K
lOK
RI&
lOK
R91
.&F --w,....-+---.=.r
lOK
9
LSI4
.&SF -+---- SWFI
SWF3~6::.:0=-----~2.;..' O:~
L_... ~J 1fT
12 2PI 12 4HI
LSSO 1_5:::4::..... ~SF~S!.._ +_---.f"> iWOSHI
HDEOI-3=- .J
31
PsvOl---------------~':>
LSI L 4---------l =,: R60
DEN
62 ....--- m
: 1
I' 1
'---I
I I
PSV R&I
I rC-~~--w.-- .5F
I lOK
2Lu~ .5F
C31~:
TPI
R56 4.7K
r SV 2C:lI
.&S
R54
lOK
IIQI!--'.---t.> rD1~1
I 181
3 I -~...----------.....-------- HDE4
~::.J 12 IHI
12 &HI
C30
~ .I~ R&9
lOOK
JP
FG SG
FD 1155C (1.2MB
FDD UNIT)
CIRCUIT DIAGRAM
Sheet 1/ 2
A-21

I
A
B
c
o
E
F
G
H
T
2
3
JI
-DRIVE SELI
-DRIVE SEL2
-DRIVE SEL3
-DRIVE SEL4
IRESERVEDI
IRESERVED)
-DIR IN
-STEP
-Wo GATE
-SEEK COMP
-READY
-W.FAULT
-TRACKOOO
-INDEX
IRESERVEDI
32
8
12
10
20
16
..-- --rr_-=-011--012_'-:- --,
~ I
..-------~I--09 100- ~-:-I-------,
.-------'-1-05 60-;.1-----,
,..------:-1-03 40--:- 1 ---""1
I 7 8 I Ra 1
't: I
RI07
220DJ
RI08
220DJ
RI09
220DJ
L[:)
2 ll~L. 1 :::=
SSI
111
2lOllJ 11
26 r ----, ~
D-iH-+-l-+'-10 I ~o-':~"'Nvi
~ ~~~ ~
5.6 IIH) '-< ~ ..-
28 1 17 18 ..0:.
D-iH-+-l-+;...10
I 2~
30 '15 16 1
- I_I
D-iH-+-l-+-
D-iH-+-l-+-,",Oll
2
o
4
o
34
~
24
6
~
22
~
~ y8
0 3 O-C,:-'I'I ,..-(J
1
,13 14 I 10
, ~ I
'
4102"",--''' r-­
C
0:
X
C
HMD - 720 MAIN CIRCUIT DIAGRAM
0:
---.J1
A-23

.5
SAII
10
9
B
7654
AEN
SA3
2
1
o
-IOW
S07
6
5
4
3
2
I
o
N I I N
::E. ;. '~:,~ ';. IKxB
LS688 Ir. '.~' >:.. SW2
A200--------n 17 ... P7 Q7 118 ~ ..... r
21 I P6 Q6 16 6 ~
22 I P5 I Q5 14 - ~
23 I P4 C Q4 t-::1~2--- t-++-~u'r' ,..........
24 P3 2 Q3 .... ~
25 P2 Q2 -- ~
26 PI QI ~
27 I PO --9.9 ~ ~ ~
11 0 Ci P=Q 1. 5 r. 7
~ LS688 '? ~~~
I I :'.. IKx4
:~ P7 Q7 t '---- ~. '.'.. :~ SWI
A2B U---------:-i,3ifP6 I Q6 ~~+----4lf-+-hI--....;j~.rv-(~y./o--......,
29 11 P5 C Q51-!,~-+-----iH-+----'2HJ~ ~
30 I P4 I Q4 9 .......
31 P3 Q3 I x.,.. .......
~ P2 Q2~ T.T
PI QI ~ +5
~ PO --9.9 fu--<
B130- ~----___i~I:JCi P=Q PL" nT N 't.~r:;~~
IIC31 r. T ,J, 1J1'l I I I I I I 200g\l 4
WxB
LS04 ~r---A-L-S-5-6-3-""" ~. =::~ '. ::
6 I~LEOI
r......"I-'".~'--,--,2=--'
A2 n--------=+-oiiLfOB QB~~- ....
3 07 Q7~~---'-IoII"''7-00,.J
4 06 I Q6Pf:~---'·""'...;.lfIIIIL"""~3~
5 05 C Q5~~---""-,-lillL..........4'-:-'_
......... 5
6 04 4 Q4~~------II""'IIII--L...... l.oIIIl 6 7
7 03 Q3P!-:~------~:.I
B ,02 Q2P!-c!~------_ .....-=M.....~1IiB
9 • 01 QI ~
LL C ocpL, ....
, m LEOxB
.5V
GNO
MFG BOARD
A-24

134
132
126
500
\ ---
~
I
103
/~'~300
Exploded Diagram For EQUITY m+, EPSON PC/AX
( 2/2 )
A-25

231
241
/
230
108
./
(,
201
100
125
Exploded Diagram For EQUITY m+, EPSON PC/AX
( 1/2 )
A-26

EPSON OVERSEAS MARKETING LOCATIONS
--
EPSON AMERlCA, INC.
Bulldlng #6 23610 Telo Ave., Torrance
CA. 90505 U.S.A
Phone: 213 - 534 - 4234
Telex: 910- 344 - 7390
EPSON UK LTD.
Dorland House, 388 High Road,
Wembley, Middlesex, HA9 6UH, U.K.
Phone: 01- 902- 8892
Telex: 8814169
EPSON ITAUA S.p.A.
Via Timavo, 12 20124 Milano
Phone: 02 - 6709136
Telex: 315132 SEGI I
EPSON AUSTRAUA PTY. LTD.
Unit 3, 17 Rodborogh Road, Frenchs
Forest, NSW 2086, Australla
Phone: 02 - 452 - 5222
Telex: 75052
EPSON ELECTRONICS TRADING LTD.
25/F Harbour Centre, 25 Harbour
Road, Wanchai, Hong Kong
Phone: 5- 8314€OO
Telex: 65542 EPSON HX
EPSON DEUTSCHLAND GmbH
Zulplcher Strasse 6 4000 Dusseldorf
11 F.R. Germany
Phone: 0211 - 56030
Telex: 8584786
EPSON FRANCE S.A.
Evolic C - 201, 86/156, avenue Louis
Roche, 92230 Genneviliers
Phone: 1 - 4792 - 0113
Telex: 614966
EPSON - STI S.A.
Paris, 152 08036 Barcelona - Spain
Phone: 250 - 3400
Telex: 50129 - STTK
EPSON ELECTRONICS (SINGAPORE)
PTE, LTD.
No.1 Raffles Place #26 - 00
Oub Centre Singapore 0104
Phone: 5330477
Telex: RS 39536 EPSONS
EPSON ELECTRONICS TRADING
LTD. (TAIWAN BRANCH)
10F, No.287. Nanking E. Road, Sec.3,
Taipei, Taiwan
Phone: 2-7160855
Telex: 24444 EPSOf'J TB
SEIKO EPSON CORPORATION
80 Hirooka Shiojiri - shi, Nagano
399 - 07, Japan
Phone: 0263 - 52 - 2552
Telex: 3342 - 214

EPSON
Printed in Ja[BIl 88.10-1.5