Slides explaining Boundary Scan test principles - goJTAG

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The True/Complement Code True part Complement part 00 11 01 10 10 01 Open Assume stuck-at-0 Short Assume wired AND 00 00 00 00 00 00 How to distinguish between opens and shorts? 11 00 11 00 Important properties of the True/Complement Code are: There are equal numbers of 0-s 0 s and 1-s 1 s upon each line Hamming distance between any two code words is at least 2 • Some shorts and opens cannot be distinguished (e.g. n2/n3) 20
Extended True/Complement Code True part Complement part Open fault symptom 01 00 11 Code extension 01 01 10 01 10 01 01 11 00 Open Assume stuck-at-0 Short Assume wired AND 00 00 00 01 00 00 01 00 00 01 11 00 Idea: add two bits, that are the same at every STV code word Shorts and stuck-at faults are now distinguishable The <strong>test</strong> length is 2⎡log 2 (N)⎤+2 21
Page 1 and 2: Board-level testing and IEEE1149.x
Page 3 and 4: Industrial approach to board test
Page 5 and 6: Test Access: Past and Present • P
Page 7 and 8: Modeling of Interconnect Faults Net
Page 9 and 10: Open Faults Misplaced bond wire Mis
Page 11 and 12: Tri-state connections Chip 1 Chip 2
Page 13 and 14: Specific faults in tri-state nets D
Page 15 and 16: Consider a simple example… Test V
Page 17 and 18: The Counting Sequence 00 01 Open As
Page 19: The True/Complement Code True part
Page 23 and 24: More complex case: branching nets e
Page 25 and 26: Outline • Board level testing cha
Page 27 and 28: Test Access Via Boundary Scan TDI T
Page 29 and 30: Test Access Via Boundary Scan Drive
Page 31 and 32: Boundary Scan basics Pin Pin Core L
Page 33 and 34: Typical Boundary Scan Cell (BC_1) B
Page 35 and 36: Boundary Scan Working Modes SAMPLE/
Page 37 and 38: Boundary Scan Working Modes EXTEST
Page 39 and 40: Typical BS Interconnect Test Flow B
Page 41 and 42: Boundary Scan Working Modes IDCODE
Page 43 and 44: TAP Controller State Diagram DR Bra
Page 45 and 46: Outline • Board level testing cha
Page 47 and 48: BScan Implementation Examples VCC +
Page 49 and 50: Board-level Test using Boundary Sca
Page 51 and 52: Cluster Logic Test (Manual) BScan I
Page 53 and 54: RAM Test Example Address 10bit walk
Page 55 and 56: RAM Test Example: detection of open
Page 57 and 58: Boundary Scan Test Development Typi
Page 59 and 60: Boundary Scan - Evolution 1149.4 -
Page 61 and 62: New and Emerging Standards Combined

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