Slides explaining Boundary Scan test principles - goJTAG

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RAM / Flash Test BScan IC 1 Chip select lines BScan IC 2 RAM 1 RAM 2 Flash To generate test: • Specify constraints that will select only one device • RAM/Flash model in special format that provides description of read/write protocol • Combination of walking and counting sequences is used 52
RAM Test Example Address 10bit walking 1 0000000000 1000000000 0100000000 0010000000 0001000000 0000100000 0000010000 0000001000 0000000100 0000000010 0000000001 Data 32 bit counting sequence (true/complement) ….…write here something unique…… ……. 01010101010101010101010101010101 00110011001100110011001100110011 00001111000011110000111100001111 00000000111111110000000011111111 00000000000000001111111111111111 10101010101010101010101010101010 11001100110011001100110011001100 11110000111100001111000011110000 11111111000000001111111100000000 11111111111111110000000000000000 53
Page 1 and 2: Board-level testing and IEEE1149.x
Page 3 and 4: Industrial approach to board test
Page 5 and 6: Test Access: Past and Present • P
Page 7 and 8: Modeling of Interconnect Faults Net
Page 9 and 10: Open Faults Misplaced bond wire Mis
Page 11 and 12: Tri-state connections Chip 1 Chip 2
Page 13 and 14: Specific faults in tri-state nets D
Page 15 and 16: Consider a simple example… Test V
Page 17 and 18: The Counting Sequence 00 01 Open As
Page 19 and 20: The True/Complement Code True part
Page 21 and 22: Extended True/Complement Code True
Page 23 and 24: More complex case: branching nets e
Page 25 and 26: Outline • Board level testing cha
Page 27 and 28: Test Access Via Boundary Scan TDI T
Page 29 and 30: Test Access Via Boundary Scan Drive
Page 31 and 32: Boundary Scan basics Pin Pin Core L
Page 33 and 34: Typical Boundary Scan Cell (BC_1) B
Page 35 and 36: Boundary Scan Working Modes SAMPLE/
Page 37 and 38: Boundary Scan Working Modes EXTEST
Page 39 and 40: Typical BS Interconnect Test Flow B
Page 41 and 42: Boundary Scan Working Modes IDCODE
Page 43 and 44: TAP Controller State Diagram DR Bra
Page 45 and 46: Outline • Board level testing cha
Page 47 and 48: BScan Implementation Examples VCC +
Page 49 and 50: Board-level Test using Boundary Sca
Page 51: Cluster Logic Test (Manual) BScan I
Page 55 and 56: RAM Test Example: detection of open
Page 57 and 58: Boundary Scan Test Development Typi
Page 59 and 60: Boundary Scan - Evolution 1149.4 -
Page 61 and 62: New and Emerging Standards Combined

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