16-Bit Microprocessor Handbook

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Before making direct comparisons of these instruction execution times with those of other devices. however. note carefully that because of the 16-bit architecture of PACE and the INS8900. it may take many instructions on another microcomputer to perform the same operations as a single INS8900/PACE instruction. MOS level signals are input and output by PACE. TTL level signals are input and output by the INS8900. P-channel silicon gate. MOS/lSI technology is used with PACE. N-channel MOS technology is used by the INS8900. PACE AND INS8900 MICROCOMPUTER SYSTEM OVERVIEWS Figure 1-1 PACE/INS8900 LOGIC LEVEL conceptually illustrates a PACE system. Figure 1-2 conceptually illustrates an INS8900 system. As with any mini- or microcomputer system, the CPU outputs data, address, and control signals. In the case of PACE and the INS8900, the data and address signals use the same bus lines; therefore, they are said to be multiplexed. Timing signals needed by PACE are generated by the System Timing Element (STE). PACE signals are all MOS level; the STE therefore generates two sets of timing signals; one set are MOS level for PACE, the other set are TTL level for external logic. SYSTEM TIMING ELEMENT (STE) BIDIRECTIONAL Since PACE signals are MOS level, Bidirectional Transceiver Elements (BTEs) must be TRANSCEIVER present to translate outgoing signals from MOS to TTL levels, and to translate incoming ELEMENT (BTE) signals from TTL to MOS levels. BTEs are quite indiscriminating in the signals they translate: in either direction. any signal arriving at an input pin is faithfully reproduced at the corresponding output pin. Control signal options allow a BTE to operate bidirectionally. to drive output Signals only. or to place both the MOS and TTL outputs in a high-impedance mode. Since the BTE is 8 bits wide. two BTEs operating bidirectionally provide buffering for the 16-bit Address/Data Bus. A third BTE. operating in the drive-only mode. provides buffering for the PACE control signals (NADS. ODS. IDS. and Flags). A complete TTL level bus is created by combining BTE outputs with the TTL level timing signals output by the STE. Remember. though. that the 16 address/data lines are multiplexed. External logic that can demultiplex these lines and that can respond to the PACE timing and control signal logic can connect directly to the TTL level address/data lines. For example. National Semiconductor provides ROM and RAM devices with on-chip address latches: these devices can interface directly to the TTL level bus. If memory devices or I/O ports are used that cannot demultiplex the address/data lines. you must provide separate logic to perform this function. No special PACE family devices are available for this purpose: however. standard logic devices can be used. For example. two hex flip-flop devices and a quad flip-flop device would provide a latched 16-bit Address Bus. Two 8212 I/O ports could also be used to latch the 16 bits of address information. The PACE Address Data Strobe (NADS) ADDRESS LATCHES AND DECODERS signal can be used as the ClK input to the flip-flops or as the STB input to the 8212s. The PACE Address Data Strobe (NADS) signal can be used as the ClK input to the flip-flops. In many systems this is the most effective approach since a latched Address Bus allows you to use simpler address decoding techniques to generate memory chip enable and I/O port select Signals. Figure 1-2 illustrates an INS8900 microcomputer system. logic is quite elementary - and equivalent to that which you would expect with any other microcomputer. Control Bus. Data Bus. and Address Bus lines are buffered using INS8208 bidirectional buffers. These are National Semiconductor standard catalog devices. recommended by National Semiconductor and illustrated in their literature: however. any other buffer would do equally well. The Data/Address Bus is shown being demultiplexed by 8212s to create separate Data and Address Busses. This again is straightforward logic. 1-2
INTERRUPT AND JUMP CONDITIONS PACE - STE () ADDR/DATA ~ " BTE (2) CONTROL '4-.../ BTE :;:; TTL LEVEL TIMING/CONTROL If .. RAM WITH ADDRESS LATCHES ROM WITH ADDRESS LATCHES TTL LEVEL ADDRESS/DATA ADDRESS LATCHES AND/OR DECODERS ••••••, •• 4) : .--".. i ~ : · . : ! : i " I/O PORT 8212, 8255 MEMORY WITHOUT ADDRESS LATCHES TTL LEVEL ADDRESS DATA ~V, ~V, SENSE LINES IN CONTROL LINES OUT ADDRESS LINES OUT DATA LINES IN/OUT Figure 1-1. A National Semiconductor PACE Microcomputer System 1-3
Page 1: OSBORNE 16-Bit Microprocessor Handb
Page 4 and 5: Copyright © 1981, 1979, 1978, 1976
Page 7 and 8: Contents 1. The National Semiconduc
Page 9 and 10: INTRODUCTION This is one o'f two bo
Page 11 and 12: Thus a signal making a low-to-high
Page 13: We will demonstrate the capriciousn
Page 18 and 19: SENSE LINES IN INS8900 TWO INS8208s
Page 20 and 21: INS8900 AND PACE ADDRESSING MODES M
Page 22 and 23: This illustration shows base page.
Page 24 and 25: INS8900 AND PACE CPU PINS AND SIGNA
Page 26 and 27: The INSS900 clock logic has been si
Page 28 and 29: The maximum extension permitted by
Page 30 and 31: ....I ....I ~ EXECUTION ..... f----
Page 32 and 33: There are two draw\Jacks inherent i
Page 34 and 35: IRO INT ENABLE lEN NHALT LEVEL 0 IN
Page 36 and 37: The interrupt sequence does not sav
Page 38 and 39: ecute a Jump Indirect (JMP@) throug
Page 40 and 41: The following symbols are used in T
Page 42 and 43: Table 1-1. INS8900 and PACE Instruc
Page 48 and 49: Memory, as organized for the benchm
Page 50 and 51: PACE STE O.lf1-F lN914 7 I TCLK- ..
Page 52 and 53: In a DMA or multiprocessor we will
Page 54 and 55: Notice that the data from external
Page 56 and 57: When the output port's address is s
Page 58 and 59: One other portion of Table 1-5 requ
Page 60 and 61: PACE CPU r - -;;,;;;.;---- - - - ;;
Page 62 and 63: PACE CPU EXTRA CLOCK CYCLEISIOUE IN
Page 64 and 65: INS8900 Absolute Maximwn Ratings Vo
Page 66 and 67:
INS8900 Tming Waveforms ~ J ttl- jJ
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INS8900 Tming Wavefonns (continued)
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PACE STE absolute maximum ratings [
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PACE BTE/S absolute maximum ratings
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PACE STE/S switching' time waveform
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Chapter 2 THE GENERAL INSTRUMENT CP
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CP1600 PROGRAMMABLE REGISTERS The C
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If Register R4 or R5 provides the i
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ESCI MSYNc' BCl BC2 BDIR 015 014 01
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MC MC T1 T2 T3 T4 T1 T2 T3 T4 BC 1
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INSTRUCTION FETCH MEMORY WRITE BAR
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The PerF signal as an input inhibit
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INSTRUCTION FETCH INSTRUCTION EXECU
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SW The Status Word. whose bits corr
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I Table 2-2. CP1600 Instruction Set
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Table 2-2. CP1600 Instruction Set S
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Table 2-3. CP1600 Branch Conditions
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Table 2-4. CP1600 Instruction Set O
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SUPPORT DEVICES THAT MAY BE USED WI
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=rt-01~~1 .. DATA READ ..J ,I II I
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Interrupts may be generated by cond
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Bit 0 is always the complement of t
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When the CPU is ready to receive da
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The only accurate long time interva
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DATA SHEETS This section contains s
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CP1600 ELECTRICAL CHARACTERISTICS (
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CP1610 ELECTRICAL CHARACTERISTICS (
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Chapter 3 THE TEXAS INSTRUMENTS TMS
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Let us first consider the manner in
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can begin executing a new program.
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efore you switched to your current
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A CRU bit instruction outputs a 12-
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When bits are transferred from a me
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or the high-order byte of a general
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Pins AO - A 14 provide the 15-bit A
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DBIN goes high at the beginning of
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If the second (destination) operand
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Every CRU 1/0 instruction will requ
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The Address Bus is used in an unusu
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THE HOLD STATE The TMS 9900 has a t
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External logic identifies the prior
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At the conclusion of the interrupt
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decoder is high, the four outputs,
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A14 A13 A12 A11 AD 'M"EMEN CRUOUT C
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The CPU checks LOAD at the end of e
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The following symbols are used in T
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Table 3-2. TMS 9900 Instruction Set
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Figure 3-14 illustrates that part o
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HOLD HLDA IAQ (LSB) (AO) CRUOUT/A13
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TMS 9980 SERIES MICROPROCESSOR TIMI
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Memory Address Reset ~ ~ Memory Byt
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• Two levels of external interrup
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The TMS 9940 does introduce one add
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The TMS 9940-can, in fact. use stan
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Table 3-7 shows how the TMS 9940 in
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2) The address output on A 1 1- A8
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You could use the CRU to perform an
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TMS 9940 GENERAL PURPOSE FLAGS If y
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2) The XOP instructions will not wo
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When an external quartz crystal is
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Clock Logic Arithmetic and Logic Un
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.~ TMS 9901 PSI PINS AND SIGNALS Th
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ICO ~--.r---, INTERRUPT MASK BITS o
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You access interrupt logic through
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generate data in two CRU bits, one
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Either of the following two events
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Table 3-9, 'TMS9902 Control and Sta
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3) Write to the Interval Timer regi
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When the break control bit is set t
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The time interval separating serial
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Transmit logic has now been initial
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TMS9902 RECEIVE OPERATIONS As soon
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THE TMS9903 SYNCHRONOUS COMMUNICATI
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We will describe programming aspect
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Table 3-12. TMS9903 Synchronous Com
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Note carefully that in SDLC mode yo
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We will next describe the Parameter
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In Monosync mode a single Sync char
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Table 3-14. TMS9903 Synchronous Com
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TMS9903 INTERRUPT LOGIC There are s
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for the short frame may go undetect
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DATA SHEE"rS The following pages co
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TMS9900 TIMING REQUIREMENTS OVER FU
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TMS9940 RECOMMENDED PROGRAMMINGITES
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TMS9940 CLOCK CHARACTERISTICS Inter
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TIM9904 Switching Characteristics,
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TMS9901 Electrical Characteristics
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TMS9902 TMS 9902 ELECTRICAL SPECIFI
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TMS9903 EQUIVALENT OF OUTPUTS EQUIV
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TMS9903 nMING REQUIREMENTS OVER FUL
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Using a 240 nanosecond clock. the M
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There is one further major differen
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placement is treated as a signed bi
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Indirect. indexed addressing may be
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NOVA STATUS FLAGS Nova minicomputer
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The Memory Bus consists of a 16-bit
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C3 1 40 MO C2 2 39 M1 C1 3 38 M2 CO
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The following sequence is sufficien
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CPU LOGIC AND INSTRUCTION EXECUTION
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The numbers CD . ® . (3) . 0 and (
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This is how the Busy and Done statu
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__ __ ___ ______ __________ These a
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MBUSY is a signal used by external
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An actual example of I/O device log
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MICRONOVA AND 9440 INTERRUPT PROCES
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acknowledge signal output by the Mi
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If you want to nest interrupts then
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The following notation is used in T
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Table 4-2. MicroNova and 9440 Instr
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tt www xx Two bits choosing the I/O
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() +5V '--- 0 -- ~CK I PRE LS74 ~ Q
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This timing is also illustrated in
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iBO iBi SELB SELD YO iR'5 C Yi iR6
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The LS 139 2-to-4 decoder decodes i
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y MEMORY CLOCK. In order that all w
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MICRONOVA D. C. (STATIC) CHARACTERI
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9440 AC CHARACTERISTICS: T A = 0 to
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9440 AC CHARACTERISTICS: TA = 0 to
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9440 AC CHARACTERISTICS: TA = 0 to
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Chapter 5 THE INTEL 8086 The 8086 i
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The 8086 has a large family of supp
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8086 PROGRAMMABLE REGISTERS AND ADD
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All 8086 memory addresses are compu
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Any Stack instruction such as a Pus
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Instructions that access data memor
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Let us now examine the various data
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We may now illustrate direct, index
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Base relative implied data memory a
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The 8086 also has Stack memory addr
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Here is an illustration of base rel
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8086 CPU PINS AND SIGNALS 8086 CPU
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In the previous illustration you wi
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RD is a single bus control signal t
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The eight combinations of 52. 51. a
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If memory or an I/O device must be
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But the 8086. having asynchronous C
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Note that the CPU may have to wait
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For an 8286 or 8287 Bus Transceiver
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The 8288 Bus Controller. described
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If there is an active Hold request
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If a 16-bit data word lies on an od
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A number of the Vector table entrie
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SINGLE STEPPING MODE When the T sta
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Secondary memory reference instruct
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AAS instruction operations may be s
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Table 5-2. 8086 Branch-an-Condition
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The LOCK must directly precede MOVS
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The following abbreviations are use
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sss PPOO v x yy yyyy represents thr
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Table 5-4. A Summary of 8086 and 80
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I Table 5-4. A Summary of 8086 and
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! Table 5-4. A Summary of 8086 and
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i I Table 5-4. A Summary of 8086 an
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Table 5-5. 8086 and 8088 Instructio
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Page 407 and 408:
Page 409 and 410:
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Table 5-7. 8080A to 8086 Instructio
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THE 8088 CPU The 8088 is an 8086 mi
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8088 TIMING AND INSTRUCTION EXECUTI
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THE INTEL 8284 CLOCK GENERATOR/DRIV
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CSYNC PCLK AEN1 RDY1 READY RDY2 AEN
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In multi-CPU configurations you wil
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THE INTEL 8288 BUS CONTROLLER In co
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8288 and 8086 control signal timing
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THE 8282/8283 8-BIT INPUT/OUTPUT LA
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AO A1 A2 A3 A4 A5 A6 A7 OE GND -- -
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ALE - ~ +DE ADO ~ - \ r AD7 8282 ST
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Page 435 and 436:
8086/8086-2/8086-4 A.C. CHARACTERIS
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8086/8086-2/8086-4 CLK (8284 Oulpul
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8086/8086-2/8086-4 OSo,OS, !i.II.SO
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8086/8086-2/8086-4 CL'~ I I L TINYC
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8088 A.C. CHARACTERISTICS 8088: TA=
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8088 ClK (828~ Output) I WRITE ~~~~
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8088 T, T, ClK VCl OSo.OS, S"S"So (
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8088 NOTE: 1. SETUP REQUIREMENTS FO
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8282/8283 INPUTS 1= )K '" ' r~'==tm
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8284 ABSOLUTE MAXIMUM RATINGS· Tem
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8286/8287 ABSOLUTE MAXIMUM RATINGS
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8286/8287 50 50 8217 40 40 u III 30
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8288 STATE eLK ADDRESS/DATA ALE ) )
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Chapter 6 THE ZILOG Z8000 SERIES Th
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THE Z8001 AND Z8002 CPU'S Because t
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 o
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The Parity, Overflow, Sign, Zero, a
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Z8000 REGISTER DESIGNATIONS Z8000 s
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The index or displacement portion o
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A Za001 direct memory address may b
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Long segmented Z8001 indexed addres
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Long segmented base relative addres
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AD9 AD10 AD11 AD12 AD13 STOP Mi AD1
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When a zaooo microprocessor execute
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Z8001 AND Z8002 TIMING AND INSTRUCT
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14----T1---_.I ..... r-----T2---...
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I--T1--1 .... • --T2--"-1---TW --
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I: Memory Refresh T1 -\- T2 -I· T3
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Last machine cycle Instruction fetc
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Last machine cycle Aborted Instruct
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The segmentation trap. internal sof
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Block transfer instructions may tra
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The multiply instruction also has w
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As illustrated above. the contents
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THE BENCHMARK PROGRAM The Z8000 can
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Object Code b - immediate value cor
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Table 6-3. A Summary of the Z8000 I
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I I I i Table 6-3. A Summary of the
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Table G-3. A Summary of the Z8000 I
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Table 6-3. A Summary of the zaooo I
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0) m ..,J Table 6-3. A Summary of t
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Copyright © 1 979 McGraw-Hili, Inc
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Mnemonic Object Code Bytes Table 6-
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Table 6-4. Z8000 Instruction Set Ob
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Table 6-5. Z8000 Object Codes (Cont
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Table 6-5. Z8000 Object Codes (Cont
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Z8001,Z8002 Composite AC Timing Dia
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Z8001,Z8002 Absolute Maximum Rating
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The primary source for the MC68000
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As we have already pointed out. all
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System Byte ~~--.... --~~~------~,
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04 03 02 01 DO AS UDS LOS R/W OTACK
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A1-A23~ __________ ________________
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I 50 I 51 I 52 I 53 I 54 55 I 56 I
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ClK A1-A23---{~ ______________ ~~~
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elK A1-A23 R/W 00-015 -----..... Fi
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Figure 7-11 illustrates the timing
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Completion of Halt State. Address B
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Figure 7-13 shows the successful co
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The MC68000 provides extensive exce
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Memory Addresses 1---16 Bits (Hex
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---------j 0 = Write cycle aborted
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7) The contents of the Status regis
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Register Direct Addressing This add
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Address Registers AO ~-------------
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Address Registers AO~ _____________
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Byte .,___ o_o_o_o_o_oo_o ____ ~ __
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ABBREVIA TIONS Following are the ab
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STATUS The effect of instruction ex
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eeeee [EXT] ffffff gggggg hhhhhh ii
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Standard Read Cycle .. I. 6800 Peri
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+5 V o AS~----~--4~;---------------
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Table 7-5. MC68000 Instructions Whi
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Table 7-6. MC68000 Instruction Set
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I I I I I I Table 1-6 .. MC68000 In
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I Table 7-6. MC68000 Instruction Se
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I Table 7-6. MC68000 Instruction Se
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I Table 7-6. MC68000 Instructim Set
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Page 626 and 627:
Table 7-7. MC68000 Instruction Obje
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Table 7-7. MC6SOOO Instruction Obje
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Page 634 and 635:
Table 7-8. MC68000 Object Codes in
Page 636:
Table 7-8. MC68000 Object Codes in
Page 642 and 643:
THE 2901, 2901 A, AND 2901 B MICROP
Page 644 and 645:
THE 2901, 2901A, AND 29018 MICROPRO
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,....----,1>-........ 0 RAM3 CL~~D-
Page 648 and 649:
00-03 is a data input port. All dat
Page 650 and 651:
The 2901 local RAM consists of sixt
Page 652 and 653:
The 2901 local RAM generates a 4-bi
Page 654 and 655:
The Q register is a single 4-bit lo
Page 656 and 657:
Table 8-1. ALU Source Operand Contr
Page 658 and 659:
~ .- "% 3-IN MUX t 3-IN MUX I Local
Page 660 and 661:
" ","',"",·',w. ",,",'. I, t ,', "
Page 662 and 663:
, ~ ,'" , t: , ,,",',' ~Z.'~UX $fif
Page 664 and 665:
Local RAM Q Register A Latch B Latc
Page 666 and 667:
Let us now examine status logic of
Page 668 and 669:
CD ~ CJ) i7 yy I sr r 1 T 1 1 1 T 1
Page 670 and 671:
Given the bit numbering system used
Page 672 and 673:
17 SO 51 !±b 1G A B 2G 17 50 51 !
Page 674 and 675:
An arithmetic upshift causes 0 to b
Page 676 and 677:
We described logic associated with
Page 678 and 679:
This is the algorithm we are about
Page 680 and 681:
In Figure 8-15. CX and CY high is t
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THE 2903 MICROPROCESSOR SLICE The 2
Page 684 and 685:
AO A Word A1 Address A2 { A3 16 x 4
Page 686 and 687:
2903 MICROPROCESSOR SLICE PINS AND
Page 688 and 689:
At intermediate and most significan
Page 690 and 691:
The A latch contents are output con
Page 692 and 693:
Beginning with the logically simple
Page 694 and 695:
Now consider the data paths we just
Page 696 and 697:
We can take the S ALU input from DB
Page 698 and 699:
The 2903 has local RAM addressing.
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Table 8-7. 2903 Destination and Shi
Page 702 and 703:
The ALU shifter, but not the Q shif
Page 704 and 705:
By holding WE high you can output d
Page 706 and 707:
You can use this pair of ALU destin
Page 708 and 709:
Table 8-8. 2903 Special Functions S
Page 710 and 711:
There are some differences between
Page 712 and 713:
Z = FO • Pi . . . FN • QO • Q
Page 714 and 715:
The negative status, N, is output h
Page 716 and 717:
multiplier is in the low-order bit
Page 718 and 719:
+5V () - 00, L5S .... 0103 0100 010
Page 720 and 721:
But what happens if you get a negat
Page 722 and 723:
Move the divisor and most significa
Page 724 and 725:
If you look again at Table 8-9, you
Page 726 and 727:
For Step 1 we execute the Double Le
Page 728 and 729:
Finally. in Step 4 we execute a Two
Page 730 and 731:
DO - 03 04 - 07" 08 - 011 012 - 015
Page 732 and 733:
CIN 2901's r ----------------------
Page 734 and 735:
THE 2909 AND 2911 MICROPROGRAM SEQU
Page 736 and 737:
Macroinstruction object codes have
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RE R3 R2 R1 RO OR3 03 OR2 02 OR1 01
Page 740 and 741:
RE ------------------~ Stack Po.int
Page 742 and 743:
Microprogram Counter will be one mo
Page 744 and 745:
Consider first a typical subroutine
Page 746 and 747:
Table 8-11. The 2903 Twos Complemen
Page 748 and 749:
Status outputs from the 2901 or 290
Page 750 and 751:
Address Bits from Status from Micro
Page 752 and 753:
THE 2910 MICROPROGRAM SEQUENCER Thi
Page 754 and 755:
DO-Dll&~~ ~ Address Register/ ~ Dow
Page 756 and 757:
DO - 011. 10 -13 Control Inputs 1--
Page 758 and 759:
Table 8-12. 2910 Microprogram Seque
Page 760 and 761:
When the 2910 receives an RFCT inst
Page 762 and 763:
2910 MICROPROGRAM SEQUENCER ADDRESS
Page 764 and 765:
Table 8-13. The 2903 Twos Complemen
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egister. As we did in instruction 2
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10 EMPTY CI OE C(I+4) CN YO Y1 Y2 Y
Page 770 and 771:
Table 8-14. 2930 Series Program Con
Page 773 and 774:
Page 775 and 776:
Am2901 /2901 A SOURCE OPERANDS AND
Page 777 and 778:
Am2901 ELECTRICAL CHARACTERISTICS O
Page 779 and 780:
Am2901A ELECTRICAL CHARACTERISTICS
Page 781 and 782:
Am2901A SET-UP AND HOLD TIMES (mini
Page 783 and 784:
Am2901B I. Typical Room Temperature
Page 785 and 786:
Am29018 II. Am2901 B Guaranteed Mil
Page 787 and 788:
Am2903 Am2903 OPERATING RANGE PIN T
Page 789 and 790:
Am2910 MAXIMUM RATINGS (Above which
Page 791 and 792:
Am2909 • Am2911 OPERATION OF THE
Page 793 and 794:
Am2909/ Am2911 MAXIMUM RATINGS (Abo
Page 795 and 796:
Am2909 • Am2911 SWITCHING CHARACT
Page 797:
Am2930 Am2930 SWITCHING CHARACTERIS
Page 800 and 801:
PACE/INS8900 (Continued) direct ind
Page 802 and 803:
OSBORNE/McGraw-Hili Books of Intere
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16-Bit Microprocessor Handbook

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