16-Bit Microprocessor Handbook

Table 1-4 summarizes the operating modes of the BTE.
BTE MODE
~~~T:~L
WBD* is the main mode control signal; when this signal is low, the other control signals are ignored
and the BTE simply converts the MOS signals from the CPU into TTL-level output signals.
The TTL outputs have a high fan-out capability and can service up to thirty 50 milliampere loads.
The BTE used to buffer the PACE control signals normally operates continuously in this 'drive-only' mode (Mode
1) and is kept in this mode by simply connecting the WBD* signal to ground.
The BTEs used to buffer bidirectional (address/data) lines must be switched back and forth between Modes 1
and 2; Mode 1 is used for CPU data output and Mode 2 for CPU data input. The simplest way of accomplishing this
is to continuously enable the CE1, CE2*, and STR* controls by connecting them to appropriate logic levels (+5V or
ground) and then use the WBD* signal for directional control. For example, in a PACE system, the IDS signal from the
CPU could be used as the input to WBD*. During a PACE data input cycle, IDS will go high at the appropriate portion of
the cycle and place the BTE in Mode 2; IDS is low at all other times and the BTE will operate in Mode 1.
Table 1-4. PACE BTE Truth Table
MODE
CONTROL INPUTS
# CE1 CE2* STR* WBD*
1 X X X 0
2 1 0 0 1
MODE DESCRIPTION
Receive MOS signals and
drive TTL signals
Receive TTL signals and
drive MOS signals
0 0 0 1
Outputs in
3 0 1 0 1 high-impedance
1 1 0 1
state
4 X X 1 1
On positive-edge transition
of STR*, latch into Mode 2
or 3 as determined by state
of CE1 and CE2*
X = don't care
+5V
15
CEl t---...
BTE
105-----"'
BUS GRANT ___...____ ~l-4_t CE2*
13
STR* t---~
-
Figure 1-20. Signal Connections to Control BTE in a DMA System
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