16-Bit Microprocessor Handbook

There are 16 data and address lines (DO - 015), which are multiplexed for data input, data output and address
output. Two control lines. ODS and NAOS, identify output on the data and address lines as either data (ODS) or
addresses (NAOS)' A further control line, IDS. is used to strobe data input.
The EXTEND control input is used by slow memories or external devices to lengthen an instruction's execution
time by increasing the duration of a data input/output cycle: this extends the time available for memories or external
devices to capture data output. or to present input data.
The NINIT input control initializes PACE; the Program Counter is set to O. The Stack Pointer, the Stack and the Status
and Control Flags register are cleared.
BPS has already been described; it is used to select either normal or split base page, for base page direct addressing.
NHAL T is a bidirectional control signal used by interrupt and halt logic. As an input. NHALT can induce a Halt state,
or in conjunction with CaNTIN, it can generate a level 0 (highest priority) interrupt request. When the CPU executes a
Halt instruction, NHAL T is output high to identify the Halt state. The various uses of NHAL T and its interaction with
CaNTIN are described in detail later in this chapter.
The CONTIN signal is used to terminate a Halt condition and is also used as an output interrupt acknowledge
signal. When CaNTIN is properly sequenced with the NHAL T signal. it initiates a high priority interrupt. as we mentioned
in the preceding paragraph. CONTIN can also be used as a Jump condition input in the same way as JC 13, 14
and 15, which are described next.
JC13, 14 and 15 provide an interesting capability found in very few microcomputers discussed in this book: the condition
of these three inputs can be tested by a Branch-on-Condition (BOC) instruction, thus allowing external control
signals to directly manipulate PACE program instruction sequences.
F11, 12, 13 and 14 are the outputs for the corresponding flag bits in the Status and Control Flags register.
NIR2, 3, 4 and 5 are the external interrupt request lines. Interrupt priority arbitration logic is included on the
INS8900 (and PACE) chip. NIR2 has the highest priority of the external interrupt lines, and NIR5 has the lowest priority.
INS8900 AND PACE TIMING AND INSTRUCTION EXECUTION
PACE uses a combination of two clock signal inputs to time events internally within the
microprocessor CPU. The clock signals and the resultant internal clock phases can be illustrated
as follows:
PACE
CLOCK
SIGNALS
~
One Machine Cycle
..
One Clock Period One Clock Period One Clock Period One Clock Period
Internal Clock
Phase
I
T1
CLK-U
NCLKJ I
I
I
I
\
1
I
T2 T3
I T4
I
U
I \
I
T5
I T6 T7 I TS
I
I
I
I
U LJ \
I
I \ I
I \ r I
I
I
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