16-Bit Microprocessor Handbook

o cycusi
®
I--- > 11 +'e ~ 8 +'e CYCUS1
o
..J
W
~
~DRIVENLOWEXTERNALLY .,- ~U NHALT
I
I
~ ~
DRIVEN HIGH EXTERNALLY
(OR USING INTERNAL PULLUP)
5 CLOCK CYCLE MIN.
INTERRUPT RESP. TIME 0)
So 15 + 21e CYCLES0 > 5 + 1e CYCLES
.. __ J - J
$. 3 CLK
I
CYCLES
• ACK .•
~
APPROX.2 1/2+te0~
~
CLOCK CYC LES
CONTINUE DRIVEN BY PACE
CONTINUE
I
I -
DRIVEN
EXTERNALLY
~ \ ~
EXECUTION
EXECUTION SUSPENDED
- I -
CONTINUE DRIVEN EXTERNALLY
INTERRUPT SERVICE STARTS
I
- I -
I
I
I
CONT
NOTES:
1. EXTERNALLY GENERATED TTL INPUTS
OVERRIDE PACE MOS OUTPUTS
2. ~ CROSSHATCH INDICATES "DON'T
~ CARF'INPUT STATE.
3. te = DURATION OF EXTEND DURING PACE
I/O CYCLES. TIMING ASSUMES NO OTHER
EXTENDS AND NO SUSPENDS
Figure 1-15. Initiating INS8900 and PACE Level 0 Interrupt
Using NHALT and CONTIN Signals
Remember that other levels of interrupts store the contents of the Program Counter or the Stack and reset the lEN flag
in the Status and Control Flag register. This sequence obviously alters the "picture" of the CPU, since both Stack contents
and Status and Control Flag register contents are changed. To avoid this, the Level 0 interrupt response by the
CPU uses an external memory location to store the contents of the Program Counter. Memory location 000716 holds
the address of the memory word where the Program Counter will be stored. The contents of the Status and Control Flag
register are unaltered. CPU internal circuitry resets an "IRO INT ENABLE flag to prevent another interrupt from being
recognized (refer to Figure 1-16). but this is not discernible to you. After the Program Counter has been saved in the
designated memory location, the instruction contained in memory location 000816 is executed: this is the first instruction
of your Level 0 interrupt service routine. Suppose, for example, that memory location 000716 contains the value
FF0016. Following a Level 0 interrupt request. the Program Counter contents will be stored in location FFO016. Following
the Level 0 interrupt acknowledge, the actual instruction stored in memory location 000816 is executed.
Note that the Level 0 interrupt acknowledge sequence has not altered anything within the CPU that is discernible to
you or to a program: the Stack, Accumulators, and Status and Control Flag register are all unchanged. Additionally,
avoiding use of the Stack ensures that there will not be a Stack overflow - and in consequence a Stack interrupt will
not be generated by this interrupt response sequence.
The normal Return-from-Interrupt (RTIl instruction that must be executed at the end of your inter- RETURN FROM
rupt service routine causes the Program Counter to be restored from the Stack Since the Level 0 PACE LEVEL 0
interrupt sequence does not utilize the Stack to store the Program Counter, a different tech- INTERRUPT
nique must be used to return control to the interrupted program. First you must execute a Set
Flag (SFLG) or Pulse Flag (PFLG) instruction, referencing bit 15 in the Status and Control Flag register. This bit always
appears to be set to a '1', but must be referenced in this case to enable lower levels of interrupts. Next you must ex-
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