16-Bit Microprocessor Handbook

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OSBORNE 16-Bit Microprocessor Handbook OSBORNE/McGraw-Hili Berkeley, California
Page 1: OSBORNE 16-Bit Microprocessor Handb
Page 5: Contributing Authors The following
Page 8 and 9: 7. The Motorola MC68000 7-1 MC68000
Page 10 and 11: TIMING DIAGRAM CONVENTIONS Timing d
Page 12 and 13: Thus a low-to-high transition of on
Page 15 and 16: Chapter 1 THE NATIONAL SEMICONDUCTO
Page 17 and 18: INTERRUPT AND JUMP CONDITIONS PACE
Page 19 and 20: Clock Logic Interface Logic Interfa
Page 21 and 22: Splitting the base page between the
Page 23 and 24: If indirect addressing with indexin
Page 25 and 26: There are 16 data and address lines
Page 27 and 28: Figure 1-6 illustrates timing for a
Page 29 and 30: control panel. this 7/8 duty cycle
Page 31 and 32: Most microprocessor.s have a Bus Re
Page 33 and 34: itiated. Since we do not know wheth
Page 35 and 36: Figu re 1-14 depicts the interrupt
Page 37 and 38: o cycusi ® I--- > 11 +'e ~ 8 +'e C
Page 39 and 40: v LEVEL 0 INTERRUPT REQUEST NOTE: I
Page 41 and 42: Table 1-1. INS8900 and PACE Instruc
Page 43 and 44: Table 1-1. 'INS8900 and PACE Instru
Page 45 and 46: The following symbols are used in T
Page 47 and 48: NOTES: Table 1-3. Branch Conditions
Page 49 and 50: must be replaced by these instructi
Page 51 and 52: Table 1-4 summarizes the operating
Page 53 and 54:
Once the INS8900 address/data lines
Page 55 and 56:
~ ______ data onto the System Bus w
Page 57 and 58:
If two· 8255s are used in parallel
Page 59 and 60:
DATA SHEETS This section contains s
Page 61 and 62:
____________________ PACE CPU For s
Page 63 and 64:
PACE CPU INTERNAL CLOCK PHASE EXTRA
Page 65 and 66:
INS8900 Tining Specifications Symbo
Page 67 and 68:
INS8900 lining Wavefonns (continued
Page 69 and 70:
PACE STE recommended crystal specif
Page 71 and 72:
PACE STE test conditions NCLK, NCK,
Page 73 and 74:
PACE BTE/S r -- dc electrical chara
Page 75:
PACE BTE/S typical performance char
Page 78 and 79:
Were you to compare Figure 2-1 with
Page 80 and 81:
Were you to implement a 16-bit wide
Page 82 and 83:
Jump instructions use direct memory
Page 84 and 85:
active output of this signal: provi
Page 86 and 87:
INSTRUCTION FETCH BAR NACT DTB NACT
Page 88 and 89:
BAR NACT NACT 2 BC1 ---------------
Page 90 and 91:
Last machine cycle of an interrupta
Page 92 and 93:
It is quite easy to generate signal
Page 94 and 95:
Table 2-2. CP1600 Instruction Set S
Page 96 and 97:
Page 98 and 99:
Page 100 and 101:
mmm m p P rr sss z Three bits indic
Page 102 and 103:
CP1600 System Bus Signals DO 015 BC
Page 104 and 105:
The CP1600 and MC6800 system busses
Page 106 and 107:
THE CP1680 INPUT/OUTPUT BUFFER (lOB
Page 108 and 109:
The actual 256 addresses will be id
Page 110 and 111:
If PDO - PD15 are configured as two
Page 112 and 113:
The most important point to note is
Page 114 and 115:
scribed this process earlier in the
Page 116 and 117:
CP1600·CP1600A·CP1610 IUS TIMING
Page 118 and 119:
CP1600A ELECTRICAL CHARACTERISTICS
Page 120 and 121:
1081680 ELECTRICAL CHARACTERISTICS
Page 122 and 123:
THE TMS 9900 MICROPROCESSOR The TMS
Page 124 and 125:
generates an internal 16-bit memory
Page 126 and 127:
As illustrated above. when you perf
Page 128 and 129:
Six object code bits identify the d
Page 130 and 131:
The source/destination memory locat
Page 132 and 133:
If eight or fewer bits are transfer
Page 134 and 135:
VBB VCC WAIT mAo HOLDA REsET IAQ HO
Page 136 and 137:
I a..~"'---CLOCK PERIOD 1---.......
Page 138 and 139:
enable strobe WE does not go low un
Page 140 and 141:
MEMEN as a contributor to select lo
Page 142 and 143:
cJ>1 rMACHINE CYCLE' MACHINE CYCLE
Page 144 and 145:
. - -- :: . .. - A14 A13 A12 A11 AO
Page 146 and 147:
The IDLE instruction is usually exe
Page 148 and 149:
AREA DEFlNmoN MEMORY MEMORY WORD CO
Page 150 and 151:
All interrupt service routines shou
Page 152 and 153:
External logic must maintain its in
Page 154 and 155:
THE TMS 9900 RESET You reset the 99
Page 156 and 157:
This is equivalent to complementing
Page 158 and 159:
I ! i Table 3-2. TMS 9900 Instructi
Page 160 and 161:
Table 3-2. TMS 9900 Instruction Set
Page 162 and 163:
THE BENCHMARK PROGRAM For the TMS 9
Page 164 and 165:
The minimum and maximum number of c
Page 166 and 167:
Accumulator Registens) Data Counten
Page 168 and 169:
HOLD-~" HLDA~---I IAQ ..... 1----1
Page 170 and 171:
Table 3-6. TMS 9980 Interrupts INTO
Page 172 and 173:
I LEVEl.. 1 r--f }- INTO ...... r I
Page 174 and 175:
This description of the TMS 9940 mi
Page 176 and 177:
The TMS 9940 has an AC status in bi
Page 178 and 179:
P23 P22 P21 P20 P19 P18 EC/P17 I DL
Page 180 and 181:
1 C016 and ending with pin P31 cont
Page 182 and 183:
- 0 P31 .. P30 'It INTi. - .. m;:-
Page 184 and 185:
Assuming that a TMS 9940 has output
Page 186 and 187:
Note that the TMS 9940, being a sma
Page 188 and 189:
TANK 1 TANK2 GNDl Q o «1>4 ct>3 ct
Page 190 and 191:
The clock input OSCIN must have a f
Page 192 and 193:
RS'fi CRUOUT CRUCLK CRUIN iN'i'6 iN
Page 194 and 195:
Device select logic determines the
Page 196 and 197:
From the programmer's viewpoint. a
Page 198 and 199:
Quite apart from interrupt logic. t
Page 200 and 201:
TMS 9901 REAL-TIME CLOCK LOGIC If y
Page 202 and 203:
THE TMS9902 ASYNCHRONOUS COMMUNICAT
Page 204 and 205:
Signals that connect the TMS9902 to
Page 206 and 207:
In the sequence above, CRUBS repres
Page 208 and 209:
For a Receive buffer full interrupt
Page 210 and 211:
Because of this resynchronization.
Page 212 and 213:
w ~ po.) .." cO· t: ro w W 9 -i ~
Page 214 and 215:
3) i5Srl is held low. 4) The interv
Page 216 and 217:
Transmit CRC Transmit Logic .......
Page 218 and 219:
3) CEo an enable signal which must
Page 220 and 221:
Let us begin by examining the Contr
Page 222 and 223:
You can only write into the Sync2 r
Page 224 and 225:
Table 3-13. TMS9903 Synchronous and
Page 226 and 227:
a TMS9903 secondary station in an S
Page 228 and 229:
The interrupt status bits include C
Page 230 and 231:
underrun, a continuous high (markin
Page 232 and 233:
When you select the Test mode by wr
Page 234 and 235:
TMS9900 TMS 9900 ELECTRICAL AND MEC
Page 236 and 237:
TMS9900 ~All~ INPUTS YDlllllllOlIWO
Page 238 and 239:
TMS9940 TEST FUNCTION This test fun
Page 240 and 241:
TIM9904 Electrical Characteristics
Page 242 and 243:
TIM9904 EQUIVALENT OF D INPUT Vee -
Page 244 and 245:
TMS9901 twltPU -l '- tr(t/» -I !.-
Page 246 and 247:
TMS9902 ... 1'0------ lel,;1 ------
Page 248 and 249:
~ ____________ TMS9903 SCR OR SCT \
Page 251 and 252:
Chapter 4 SINGLE CHIP NOVA MINICOMP
Page 253 and 254:
Clock Logic MicroNova anc:f~ Logic
Page 255 and 256:
NOVA MEMORY ADDRESSING MODES Both t
Page 257 and 258:
Program relative, indirect addressi
Page 259 and 260:
If. and only if indirect addressing
Page 261 and 262:
Table 4-1 briefly defines the funct
Page 263 and 264:
VBB 40 Vss (GROUND) P 39 nc WE 38 V
Page 265 and 266:
The 9440 has two I/O control signal
Page 267 and 268:
-Da-ta-D-u-tP-ut-T-o-~-s-tin-a-tio-
Page 269 and 270:
In summary, the five operations tha
Page 271 and 272:
o 1 2 3 .. 5 6 7 8 9 10 11 12 13 10
Page 273 and 274:
Both a status manipulation and a da
Page 275 and 276:
Figure 4-12 shows the CPU driving t
Page 277 and 278:
If a memory read operation is to be
Page 279 and 280:
I , I I , I I I I 01 180 -IBI5 MO-M
Page 281 and 282:
There will be a separate device int
Page 283 and 284:
Machine Cycle 1 Interrupt Acknowled
Page 285 and 286:
The 9440 has a more primitive DMA c
Page 287 and 288:
CSKCND) (@ ) DISP (.IX) (t) x [ ] [
Page 289 and 290:
I Table 4-2. MicroNova and 9440 Ins
Page 291 and 292:
Table 4-2. MicroNova and 9440 Instr
Page 293 and 294:
Table 4-3. MicroNova and 9440 Instr
Page 295 and 296:
Table 4-4.9440 Instruction Executio
Page 297 and 298:
9440 - NOVA BUS INTERFACE We will n
Page 299 and 300:
INTP may be connected to the comple
Page 301 and 302:
Instruction object code bits are co
Page 303 and 304:
educed context we can synthesize th
Page 305:
Figure 4-22. Timing for 9440-Based
Page 308 and 309:
MICRONOVA ABSOLUTE MAXIMUM RATINGS
Page 310 and 311:
9440 ABSOLUTE MAXIMUM RATINGS (beyo
Page 312 and 313:
9440 CLKOUT I ... ·---------------
Page 314 and 315:
9440 eLK OUT ,- ~------------------
Page 316 and 317:
9440 t-.-----------WAIT----------_
Page 318 and 319:
These are the most interesting inno
Page 320 and 321:
THE 8086 CPU Functions implemented
Page 322 and 323:
A H,L B,C 0, F Sf' PC 15 7 07 .----
Page 324 and 325:
During an instruction fetch, the Pr
Page 326 and 327:
Instructions that process data stri
Page 328 and 329:
Table 5-1. A Summary of Intel 8086
Page 330 and 331:
Direct, indexed addressing is also
Page 332 and 333:
Data memory base relative addressin
Page 334 and 335:
Base relative. direct. indexed data
Page 336 and 337:
Here is an illustration of base rel
Page 338 and 339:
8086 Jump and Subroutine Call instr
Page 340 and 341:
~ ~ The 8086 outputs a 20-bit memor
Page 342 and 343:
If a word lies on an odd-byte addre
Page 344 and 345:
There are eight pins that can outpu
Page 346 and 347:
8086 TIMING AND INSTRUCTION EXECUTI
Page 348 and 349:
8086 INSTRUCTION QUEUE Consider wha
Page 350 and 351:
Now. the illustration above is not
Page 352 and 353:
The memory or I/O device address is
Page 354 and 355:
Observe that OSO and OS1 change lev
Page 356 and 357:
T1 T2 T3 TW T4 elK RDY READY ROY co
Page 358 and 359:
ADO-AD15 A16-A19 OSO, OS1 I· One B
Page 360 and 361:
The processor Wait state can be use
Page 362 and 363:
Memory Interrupt Addresses Vector T
Page 364 and 365:
In the illustration above, RRRRP re
Page 366 and 367:
Once again you must subtract bytes.
Page 368 and 369:
Initially. AH contains 05 and AL co
Page 370 and 371:
But. precede this instruction with
Page 372 and 373:
Table 5-3. 8086 Memory Addressing O
Page 374 and 375:
U Status flag modified. but undefin
Page 376 and 377:
Table 5-4. A Summary of 8086 and 80
Page 378 and 379:
Page 380 and 381:
Page 382 and 383:
Page 384 and 385:
Page 386 and 387:
Page 388 and 389:
Page 390 and 391:
Page 392 and 393:
Page 394 and 395:
Page 396 and 397:
Page 398 and 399:
Table 5-5. 8086 and 8088 Instructio
Page 400 and 401:
Page 402 and 403:
Page 404 and 405:
Page 406 and 407:
Page 408 and 409:
Page 410 and 411:
Object Code Table 5-6. 8086 and 808
Page 412 and 413:
Table 5-7. 8080A to 8086 Instructio
Page 414 and 415:
GND A14 A13 A12 A11 A10 A9 A8 AD7 A
Page 416 and 417:
THE 8088 HALT STATE When operating
Page 418 and 419:
RES 0 Q RESET .ff X1 X2 TANK XTAl O
Page 420 and 421:
Cx XTAl ..dl§ Xl RDYl X2 asc R~DYa
Page 422 and 423:
Master Synchronizer - D 7474 Q .. 0
Page 424 and 425:
lOB ClK 51 DT/R ALE AEN MROC" lJI.W
Page 426 and 427:
Table 5-8. Effect of lOB. CEN. and
Page 428 and 429:
010 011 012 013 014 015 016 017 or
Page 430 and 431:
SOME 8086 MICROPROCESSOR BUS CONFIG
Page 432 and 433:
GND MN/MX J* AD8 GND J3HE so S1 52
Page 434 and 435:
8086/8086-2/8086-4 ABSOLUTE MAXIMUM
Page 436 and 437:
8086/8086-2/8086-4 ClK CI214 Output
Page 438 and 439:
8086/8086-2/8086-4 8086 MAX MODE SY
Page 440 and 441:
8086/8086-2/8086-4 T, T2 TJ T. ClK
Page 442 and 443:
-~-,. 8088 ABSOLUTE MAXIMUM RATINGS
Page 444 and 445:
8088 I T, Tz T3 Tw T. VCH v----\I--
Page 446 and 447:
8088 8088 MAX MODE SYSTEM (USING 82
Page 448 and 449:
8088 C1.K Ii. s,. iii (EXCEPT HAL T
Page 450 and 451:
8282/8283 ABSOLUTE MAXIMUM RATINGS
Page 452 and 453:
8282/8283 OUTPUT DELAY VS. CAPACITA
Page 454 and 455:
8284 TIMING RESPONSES Symbol Parame
Page 456 and 457:
TELOV-C= 8286/8287 INPUTS \'1 J~ OE
Page 458 and 459:
8288 ABSOLUTE MAXIMUM RA TlNGS· Te
Page 460 and 461:
8288 eEN DEN DEN, PDEN Qualificatio
Page 462 and 463:
Second sources include: ADVANCED MI
Page 464 and 465:
15 14 13 12 11 10 9 S 7 6 5 4 3 2 o
Page 466 and 467:
The segment number and offset trans
Page 468 and 469:
The New Program Status Area Pointer
Page 470 and 471:
Z8002 15 8 7 Z8001 o ...--Bit No.--
Page 472 and 473:
Some Za001 program memory reference
Page 474 and 475:
Z8001 and Z8002 indexed memory addr
Page 476 and 477:
Z8002 base relative addressing may
Page 478 and 479:
za001 program relative addressing,
Page 480 and 481:
MREQ is output low when memory is b
Page 482 and 483:
For the Z8001 only, memory is segme
Page 484 and 485:
..-1.--T1-----t·~I·--T2--..... ·
Page 486 and 487:
I---T1---t·~I·--T2 -~·*"'I·f---
Page 488 and 489:
Z8000 INSTRUCTION FETCH OVERLAP The
Page 490 and 491:
' .. rn T2 T3 ·1· ·1· I· T1---
Page 492 and 493:
InIT:-I--T3----11··I~ .. • -T-X
Page 494 and 495:
l8002 New Program Status Area Point
Page 496 and 497:
THE Z8000 RESET You r ••• t a
Page 498 and 499:
The divide instruction holds the di
Page 500 and 501:
A subroutine CALL can use segmented
Page 502 and 503:
MREQ uses MI and MO to request exte
Page 504 and 505:
The nomenclature used to identify Z
Page 506 and 507:
Instruction Mnemonics: The fixed pa
Page 508 and 509:
Table 6-3. A Summary of the Z8000 I
Page 510 and 511:
Page 512 and 513:
Table 6-3. A Summary of the zaooo I
Page 514 and 515:
Page 516 and 517:
I Table 6-3. A Summary of the zaooo
Page 518 and 519:
Page 520 and 521:
Page 522 and 523:
I Table 6-3. A Summary of the Z8000
Page 524 and 525:
Table 6-3. A Summary, of the Z8000
Page 526 and 527:
Page 528 and 529:
Page 530 and 531:
Table 6-3. A Summary of the zaooo I
Page 532 and 533:
Page 534 and 535:
Page 536 and 537:
Table 6-4. zaooo Instruction Set Ob
Page 538 and 539:
Mnemonic Object Code Bytes Table 6-
Page 540 and 541:
Table 6-4. Z8000 Instruction Set Ob
Page 542 and 543:
Table 6-5. zaooo Object Codes Objec
Page 544 and 545:
Table 6-5. zaooo Object Codes (Cont
Page 547 and 548:
DATA SHEETS This section contains s
Page 549 and 550:
zaOO1,Z8002 AC Number Symbol Parame
Page 551 and 552:
Chapter 7 THE MOTOROLA MC68000 The
Page 553 and 554:
31302928272625242322212019181716151
Page 555 and 556:
You will note that the first byte i
Page 557 and 558:
Table 7-1. MC68000 Addressing Mode
Page 559 and 560:
MC68000 PINS AND SIGNALS Figure 7-3
Page 561 and 562:
e generated with a Memory Managemen
Page 563 and 564:
inserted into the read timin~y~as i
Page 565 and 566:
Timing for a write word operation i
Page 567 and 568:
MC68000 READ-MODIFY-WRITE TIMING Th
Page 569 and 570:
The MC68000 RESET OPERATION The MC6
Page 571 and 572:
THE MC68000 BUS CYCLE RERUN TIMING
Page 573 and 574:
MC68000 EXCEPTION PROCESSING LOGIC
Page 575 and 576:
There are three different types of
Page 577 and 578:
3) The T-bit in the Status Register
Page 579 and 580:
Complete Current ----.+---Interrupt
Page 581 and 582:
5) Program Counter Relative Address
Page 583 and 584:
Data Register Direct EA = Dn Mode =
Page 585 and 586:
Address Registers Memory .- xxxxyyy
Page 587 and 588:
[PC]- 2 [PC] - ~[PC] Memory 1 xixl1
Page 589 and 590:
displacements. Accordingly. an inst
Page 591 and 592:
sadr sAn sOn SR USP vector [[J] [ ]
Page 593 and 594:
MC68000 INSTRUCTION OBJECT CODE TAB
Page 595 and 596:
Again, the MC68000 performs read/wr
Page 597 and 598:
so 52 54 5W SW SW SW SW SW 5W 56 so
Page 599 and 600:
Table 7-4. MC68000 Instructions Whi
Page 601 and 602:
I Table 7-6. MC68000 Instruction Se
Page 603 and 604:
Table 7-6. MC68000 Instruction Set
Page 605 and 606:
Page 607 and 608:
Table 7-6, MC68000 Instruction Set
Page 609 and 610:
Page 611 and 612:
Page 613 and 614:
Page 615 and 616:
Page 617 and 618:
Page 619 and 620:
Page 621 and 622:
Page 623 and 624:
Page 625 and 626:
Table 7-7. MC68000 Instruction Obje
Page 627 and 628:
Page 629 and 630:
Page 631 and 632:
Page 633 and 634:
Table 7-8. MC68000 Object Codes in
Page 635 and 636:
Table 7-8. MC68000 Object Codes in
Page 641 and 642:
F Id 01 :y d m II li e 5 ")1 iE
Page 643 and 644:
Chapter 8 2900 SERIES CHIP SLICE PR
Page 645 and 646:
Data In 16 x 4 bits of t--4 bits wi
Page 647 and 648:
A3 A2 A1 AO 16 18 17 RAM3 RAMO (+5V
Page 649 and 650:
2901 LOGIC We will now examine 2901
Page 651 and 652:
You use pins 80-83 to identify the
Page 653 and 654:
Data shifted up one bit receives a
Page 655 and 656:
We will now examine the arithmetic
Page 657 and 658:
Table 8-4. ALU Destination Control
Page 659 and 660:
, •• t 3-IN MUX t 3-IN MUX t Lo
Page 661 and 662:
~ ,. 1 ~ 3-IN 1\ X MUX i Local RAM
Page 663 and 664:
,.w "'" '" '" ,", "+'"~'''''''%''''
Page 665 and 666:
3-INauX shifiiJl, I i'" '" " "" "n'
Page 667 and 668:
want to perform the entire arithmet
Page 669 and 670:
Shifts do not always occur at the 2
Page 671 and 672:
Q314 ... Q4 m Q(N-4) 14 --I Q(N-3~i
Page 673 and 674:
You can generate an up rotate by in
Page 675 and 676:
Let us now look at the simple probl
Page 677 and 678:
Two microinstructions, with appropr
Page 679 and 680:
D 01- (X) W --.J 7 y S,l 1 s, r CY
Page 681 and 682:
The downshift microinstruction is s
Page 683 and 684:
4-bit Shifter Data in or out Figure
Page 685 and 686:
01°0 1 48 01°3 EA 2 47 B3 DAO 3 4
Page 687 and 688:
The 2903 has a 9-bit instruction co
Page 689 and 690:
2903 LOGIC We will now examine 2903
Page 691 and 692:
CPU register implementation and ALU
Page 693 and 694:
Now consider the same data paths il
Page 695 and 696:
But. moving away from complex opera
Page 697 and 698:
Data entering at DBO-DB3 could be i
Page 699 and 700:
to the following continuous three-a
Page 701 and 702:
With regard to Table 8-6. note that
Page 703 and 704:
The 2903 ALU shifter is located on
Page 705 and 706:
You can also discard the ALU output
Page 707 and 708:
I z z - 0103 MSS 0100 0103 0100 _X
Page 709 and 710:
The normalization operation upshift
Page 711 and 712:
+5V Z = 00 • 01 ••• ON Z Z
Page 713 and 714:
S3 - - - +5V 4) j= :~ Z Z Z Z - 010
Page 715 and 716:
After the low-order bit of the Q re
Page 717 and 718:
OO,LSS - - - - +5V C) :: .~ 4,.· Z
Page 719 and 720:
We will now examine the 2903 Twos C
Page 721 and 722:
Overflow status when performing the
Page 723 and 724:
Table 8-9. A Possible 2903 Twos Com
Page 725 and 726:
Q3, MSS F3 + R3 - - - - Z Z Z ....
Page 727 and 728:
In our binary example the divisor i
Page 729 and 730:
THE 2902 CARRY LOOK-AHEAD DEVICE Th
Page 731 and 732:
Table 8-10. P and G Generation Logi
Page 733 and 734:
...... " f-/ ~ roo- ~ """""' .....-
Page 735 and 736:
Macroinstruction Macroinstruction R
Page 737 and 738:
If every macroinstruction resulted
Page 739 and 740:
RE----------------~ RO-R3~ ________
Page 741 and 742:
As illustrated above. the Address r
Page 743 and 744:
You modify the Stack Pointer addres
Page 745 and 746:
The final instruction of the subrou
Page 747 and 748:
Table 8-11. The 2903 Twos Complemen
Page 749 and 750:
derived directly from its microinst
Page 751 and 752:
Microinstructions 6 and 7 both have
Page 753 and 754:
Y4 1 40 03 03 1 42 Y3 04 2 39 Y3 Y4
Page 755 and 756:
Note that the 2910 has no zero inpu
Page 757 and 758:
Macroinstruction D Macroinstruction
Page 759 and 760:
Instruction code 3 (CJP) is a Condi
Page 761 and 762:
Instruction code B is a Conditional
Page 763 and 764:
... More frequently. instruction co
Page 765 and 766:
Table 8-13. The 2903 Twos Complemen
Page 767 and 768:
THE 2930 AND 2932 PROGRAM CONTROL U
Page 769 and 770:
~ DO - 03 h 1 - 1 . > -----.. Accum
Page 771:
The Program Counter normally receiv
Page 774 and 775:
Am2901/ Am2901 A MICROCODE 12 11 10
Page 776 and 777:
Am2901 MAXIMUM RATINGS (Above which
Page 778 and 779:
Am2901 GUARANTEED OPERATING CONDITI
Page 780 and 781:
Am2901A SWITCHING CHARACTERISTICS O
Page 782 and 783:
Am2901B PRELIMINARY DATA ELECTRICAL
Page 784 and 785:
Am29018 I. Guaranteed Commercial A.
Page 786 and 787:
Am2902A MAXIMUM RATINGS (Above whic
Page 788 and 789:
Am2903 SWITCHING CHARACTERISTICS (T
Page 790 and 791:
Am2910 SWITCHING CHARACTERIST1CS Th
Page 792 and 793:
Am2909 • Am2911 Figure 7 illustra
Page 794 and 795:
Am2909 • Am2911 ELECTRICAL CHARAC
Page 796 and 797:
~-"~ -~-~ _ Am2930 MAXIMUM RATINGS
Page 799 and 800:
INDEX CP1600 direct addressing. 2-3
Page 801 and 802:
data output. 8-99 immediate data in
Page 803:
OSBORNE/McGraw-H ill Microprocessor
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