16-Bit Microprocessor Handbook

Most microprocessor.s have a Bus Request input signal that can be used by external logic to request
access to the System Busses. In a PACE or INS8900 system. the NHAL T input signal
can be used to force the CPU into a Processor Stall. as described earlier. and thus free
the System Busses for DMA operations. The Acknowledge Interrupt (ACK INT) pulse on
the CONTIN output line shown in Figure 1-10 is then equivalent to a Bus Grant signal.
and the DMA controller may begin the data transfer. When the transfer is complete. the
CONTIN line is used as a control input line to the CPU to terminate the Processor Stall.
Cycle-stealing DMA operations typically transfer a single word via the System Busses during a
brief interval when the CPU is not using the busses. With this method. CPU operations need
not be stopped; instead. they are only slowed down slightly. or in some cases not affected at
all. In order to implement cycle-stealing DMA. external logic must have a way of detect­
DMA BLOCK
DATA TRANSFERS
INITIATED BY
EXTERNAL LOGIC
IN PACE AND
INS8900
SYSTEMS
CYCLE-STEALING
DMA IN PACE
AND INS8900
SYSTEMS
ing those time intervals when the CPU will not be using the System Busses. There are' '--------...
two ways that this can be accomplished with the INS8900 or PACE CPU. The first method involves the use of the EX­
TEND input signal to the CPU to suppress or suspend input/output operations; the second method uses a special technique
to sense when the CPU is beginning an internal (non-I/O) machine cycle.
Earlier we described how to use the EXTEND input signal to lengthen the CPU input/output cycles.
The EXTEND signal can also be used to prevent the CPU from beginning an I/O cycle. and
thus ensure that the System Busses will be available to external devices for DMA operations.
Figure 1-11 illustrates both uses of the EXTEND signal. The CPU looks at the EXTEND input signal
at internal clock phases T1 and T6. Notice that during I/O cycles the IDS or ODS signal goes
high at the beginning of T6 and low at the beginning of T1. If EXTEND is high during T6. then extra
clock cycles are inserted after T8; this is the method that would be used to lengthen an I/O cy-
EXTEND USED
TO SUSPEND
INS8900 AND
PACE I/O
DURING DMA
OPERATIONS
cle. If EXTEND is high during T1. then extra clock cycles are inserted between T3 and T4; this is the method we would
use for DMA operations.
The trailing edge of IDS/ODS indicates that the CPU has just completed an I/O cycle and is therefore not using the
System Busses at this instant. By setting EXTEND high at this time. we suppress the beginning of another I/O cycle
while we use the busses for a DMA transfer.
Notice that we are merely lengthening the beginning of the machine cycle. and thus delaying that part of the machine
cycle where the CPU might begin I/O activity. We do not know whether the current machine cycle will be an internal
machine cycle or an I/O cycle. and we do not care. We have merely stolen the busses by slowing down the CPU.
750 nsec 1.5 j1.sec
Internal I . I ~ ~ I I .. ~I I
Clock Phase :T1 T2 T3 T4 T5 T6 T7 T8 EEl T1 T2 T3 E E T4 T5 T6 T7 T81T1 T2 T3 E E E E T4 T5 T61
, I I I
IDS/ODS I
j...---""
BUS
AVAILABLE
CPU I/O CYCLE CPU I/O CYCLE CPU I/O CYCLE
EXTENDED ONE CLOCK DELAYED ONE CLOCK DELAYED TWO CLOCK
PERIOD PERIOD PERIODS
!
I
1.5 j1.sec 2.25 j1.Sec
.. .1 C .l
Figure 1-11. Using PACE EXTEND Signal for Cycle-Stealing DMA
1-17