16-Bit Microprocessor Handbook

If indirect addressing with indexing is specified, then a direct address is first computed by adding the displacement. as
a signed binary number, to the contents of the specified Index register; the direct indexed address thus computed provides
the memory location where the indirect address will be found. This is illustrated as follows:
MEMORY
Memory .. OFDC
Address
OFDD
OFDE
AC2 = 1042'6 .. OFDF 217A Direct, indexed addressed word
DISP =90'6
OFEO
1042 + FF9D = OFDF
·
extended sign bit
. i ·
: •
! }
2178
2179
, J
Effective ~ 217A This word addressed indirectly
Memory
217B
Address
217C
INS8900 AND PACE STATUS AND CONTROL FLAGS
The INS8900 has a 16-bit Status and Control Flag register. This register is on the CPU chip and is illustrated as
follows:
Fourteen of the 16 register bits are used. Three of the 14 bits are status flags as we define a status flag. These
three flags are:
Overflow (OVF), which is a typical Overflow status.
Carry (CRY)'
Link (LINK),
which is set and reset by arithmetic operations, as described for a typical Carry status.
which is set and reset by Shift and Rotate instructions, as described for the hypothetical microcomputer's
Carry status in Volume 1, Chapter 7.
The separation of Carry into two statuses, one for shift and rotate operations, and the other for arithmetic
operations, isa fairly common minicomputer feature; the advantage of separating these two statuses is that the
results of arithmetic operations can be preserved across subsequent Shift and Rotate instructions.
BYTE causes data to be accessed in 8-bit lengths when this status is set to 1, or in 16-bit lengths when this status is
set to O.
Five bits (lE1 through IES) are reserved for interrupt processing. These five bits selectively enable and disable five
interrupt lines. One of these lines OE1) is reserved for the Stack Overflow interrupt the other four lines are available for
external device interrupt requests. There is also a master interrupt enable and disable bit (INT EN).
Bits F11, F12, F13 and F14 are control flags which are output directly to INS8900 and PACE device pins; they can
be used in any way to control external devices. One use, to select normal or split base page addressing, has already
been described.
Only the three status flags OVF, CRY and LINK are automatically set or reset in the course of instruction execution.
The remaining 11 bits of the Status and Control Flags register are set and reset by instructions or instruction sequences
that read data into, or write data out of, the Status and Control Flags register.
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