Tutorial - Using Xilinx System Generator 13.2 for Co-Simulation on ...

Figure 12: <strong>Co</strong>nfigure <strong>System</strong> <strong>Generator</strong> <strong>for</strong> HW/SW <strong>Co</strong>-<strong>Simulation</strong> - <strong>Co</strong>mpiling a new Board• When the compilation is complete, a new library is created including one block as shown in Figure14. The library name should be “sg tut 1 hwcosim lib” and the block name should be“sg tut 1 hwcosim”. The block has two inputs and one output as required by the DSP system.This block includes all the functionality required <strong>for</strong> the system to be executed on the FPGA.• Now we are ready to per<strong>for</strong>m HW/SW <strong>Co</strong>-<strong>Simulation</strong> <strong>for</strong> our DSP system.6 Hardware/Software <strong>Co</strong>-<strong>Simulation</strong>In the previous section two steps were per<strong>for</strong>med:• We configured <strong>System</strong> <strong>Generator</strong> <strong>for</strong> HW/SW <strong>Co</strong>-<strong>Simulation</strong> using NEXYS3 (Spartan-6) Board• We generated a library with a new block that encapsulate the hardware implementation of the DSPsystem. This block is linked to a bit-stream that will be downloaded into the FPGA during <strong>Co</strong>-<strong>Simulation</strong>.In this section we will modify the DSP model to use the new <strong>Co</strong>-<strong>Simulation</strong> block and replace thesimulation models used be<strong>for</strong>e.10