Tutorial - Using Xilinx System Generator 13.2 for Co-Simulation on ...

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Figure 21: Initialize Parts List– Clock Pin Location: V10– Clock Frequency: 100 MHz– The FPGA part number:∗ Family: spartan6∗ Part: xc6sLX16∗ Speed: -3∗ Package: csg324– The FPGA position in the JTAG chain: 1Click Install to build the required files to configure the board <strong>for</strong> <strong>System</strong> <strong>Generator</strong>.Note: You can save the configurations file into a compressed archive so that you can useit later to configure the board in case <strong>System</strong> <strong>Generator</strong> was reinstalled. Click “SaveZip” to create the compressed file.• After installing the new board configuration, the board name “NEXYS 3 Board” should appearin the <strong>Co</strong>-<strong>Simulation</strong> list in the <strong>System</strong> <strong>Generator</strong> properties as shown in Figure 22. Select the boardfrom the list.Note: Board configuration <strong>for</strong> <strong>Co</strong>-<strong>Simulation</strong> is required only once <strong>for</strong> each new board.The board name will always appear in <strong>Co</strong>-<strong>Simulation</strong> list every time you use <strong>System</strong><strong>Generator</strong>.18
Figure 22: <strong>Co</strong>nfigure <strong>System</strong> <strong>Generator</strong> <strong>for</strong> HW/SW <strong>Co</strong>-<strong>Simulation</strong> - Selecting the new Board19
Page 1 and 2: Tutorial - <strong
Page 3 and 4: 3 Creating a DSP systemIn this part
Page 5 and 6: Figure 4: Adding Multipliersin the
Page 7 and 8: 4. With Estimate selected from the
Page 9 and 10: Figure 11: Verifying the Si
Page 11 and 12: Figure 13: Building the Design Netl
Page 13 and 14: • When the download completes, <s
Page 15: 8 SummaryIn this tutorial we demons

Tutorial - Using Xilinx System Generator 13.2 for Co-Simulation on ...

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