IFCPAR AR (ENGLISH) for CD - CEFIPRA

CEFIPRA
Centre Franco-Indien pour la Promotion de la Recherche Avancée
Duration: Three years (October, 2009 to September, 2012)
Objectives
i) Novel designs that account for the physics of the DG-
MOSFET (very thin silicon film, fully-depleted body;
particular gm-ID, rout, and various capacitance
variations, etc.)
ii) Novel circuit designs for very-low-voltage operation (to
obtain good signal-to-noise margins, and large input and
output swings)
iii) Novel SRAM circuit architectures that benefit of the double
gates to improve both the stability and writeability in ultra
low voltage
iv) Novel circuit designs for ultra low power operation
(subthreshold conduction in DG-MOSFETs, novel
adaptive-bias, or high slew-rate, architectures, and other
novel power saving architectures).
Accomplishments
i) The following novel circuits have been designed with
double-gate MOSFETs:
• A 110 MHz rail-to-rail opamp architecture
• A 0.7-V rail-to-rail voltage buffer
• A low-power adder circuit
• A capacitor-based carry-generation circuit for binary
adders
Research papers published: Nil
Research Activities 2010-11
Other Priority Areas : Technology for Information and Communication
Project 4100-IT-1
ROBUST ULTRA-LOW-POWER DOUBLE-GATE MOSFET DESIGN OF
ANALOG, DIGITAL AND SRAM MEMORY CIRCUITS
Prof. Chetan D. Parikh
Dhirubhai Ambani Institute of
Information and Communication
Technology
Gandhinagar
Prof. Amara Amara
Institut Supérieur d’Electronique de Paris
Paris
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