The FEE Server Control Engine of the ALICE-TRD - Westfälische ...
The FEE Server Control Engine of the ALICE-TRD - Westfälische ...
The FEE Server Control Engine of the ALICE-TRD - Westfälische ...
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4 <strong>The</strong> <strong>ALICE</strong> Transition Radiation Detector<br />
channels which fulfil configurable conditions like <strong>the</strong> channel being part <strong>of</strong> a tracklet or<br />
<strong>the</strong> total signal sum is above a threshold are send.<br />
<strong>The</strong> MCMs have no nonvolatile memory. <strong>The</strong>refore <strong>the</strong> complete configuration has to<br />
be transmitted to <strong>the</strong> MCMs after each power up. This includes calibration values for<br />
<strong>the</strong> ADCs, <strong>the</strong> filter settings and settings for <strong>the</strong> tracklet preprocessor. <strong>The</strong> settings are<br />
transmitted to <strong>the</strong> MCMs via <strong>the</strong> SCSN bus and written to <strong>the</strong> configuration registers <strong>of</strong><br />
<strong>the</strong> TRAP chip. <strong>The</strong> TRAP chip has 434 configuration registers in total with sizes between<br />
1 and 32 bits [A + 05]. Not all registers are used to store configuration values. Writing to<br />
some registers initiates special actions <strong>of</strong> <strong>the</strong> TRAP like reading <strong>the</strong> internal temperature<br />
sensor (see chapter 6) whereas o<strong>the</strong>r registers contain counters or status information <strong>of</strong><br />
<strong>the</strong> chip. A complete list <strong>of</strong> all registers, <strong>the</strong>ir individual size and <strong>the</strong>ir function is given<br />
in <strong>the</strong> TRAP user manual [A + 05].<br />
<strong>The</strong> four tracklet processors which do <strong>the</strong> tracklet calculation are freely programmable<br />
CPUs. Each CPU has an instruction memory (IMEM) <strong>of</strong> 4096 times 24 bit (4096 ’words’)<br />
which contains <strong>the</strong> program for <strong>the</strong> CPU. Just like <strong>the</strong> configuration, <strong>the</strong> programs for <strong>the</strong><br />
CPUs have to be transmitted to <strong>the</strong> MCMs via <strong>the</strong> SCSN Bus. <strong>The</strong> current programs have<br />
a size <strong>of</strong> 1532 words for <strong>the</strong> first CPU, 1665 words for <strong>the</strong> second CPU, 1367 words for<br />
<strong>the</strong> third CPU and 1412 words for <strong>the</strong> forth CPU. Most parts <strong>of</strong> <strong>the</strong> four CPU programs<br />
are identical. <strong>The</strong> different sizes <strong>of</strong> <strong>the</strong> configurations are caused by <strong>the</strong> fact that <strong>the</strong><br />
programs do not only contain <strong>the</strong> routines for <strong>the</strong> tracklet calculation but test routines<br />
and o<strong>the</strong>r special functions, too. Since <strong>the</strong>re is space left in <strong>the</strong> IMEM <strong>the</strong> programs can<br />
be extended in <strong>the</strong> future.<br />
4.3.3 <strong>The</strong> Optical Readout Interface<br />
<strong>The</strong> Optical Readout Interface (ORI) is an optical transmitter card which transfers <strong>the</strong><br />
data from <strong>the</strong> MCMs to <strong>the</strong> global tracking unit (GTU). <strong>The</strong> ORI receives <strong>the</strong> data from<br />
<strong>the</strong> half chamber merger (see 4.3.6), converts and serializes <strong>the</strong> data and sends it via an<br />
optical fiber at 2.5 Gbit/s to <strong>the</strong> GTU.<br />
<strong>The</strong> four main components <strong>of</strong> an ORI are a CPLD chip (Complex Programmable Logic<br />
Device) which provides <strong>the</strong> interface between <strong>the</strong> half chamber merger and a serializer<br />
chip, <strong>the</strong> serializer chip, an optical driver chip for <strong>the</strong> laser diode and <strong>the</strong> diode itself.<br />
<strong>The</strong> ORI has a JTAG and an I 2 C interface. <strong>The</strong> JTAG interface provides access to <strong>the</strong><br />
CPLD chip. It can be used to reprogram <strong>the</strong> CPLD and to access some configuration<br />
registers in <strong>the</strong> CPLD. <strong>The</strong> I 2 C interface is used to program and control <strong>the</strong> laser driver<br />
chip [LARP06].<br />
Two MCMs on each ROB equipped with an ORI support a special operation mode. In<br />
this mode commands addressed to <strong>the</strong>se MCMs are forwarded via JTAG or I 2 C to <strong>the</strong><br />
ORI. Data from <strong>the</strong> ORI are received by <strong>the</strong> MCMs and stored in registers <strong>of</strong> <strong>the</strong> MCMs<br />
where <strong>the</strong>y can be read out via SCSN. Using <strong>the</strong>se MCMs, programs running on <strong>the</strong> DCS<br />
board have access to <strong>the</strong> CPLD and <strong>the</strong> optical driver chip on <strong>the</strong> ORI. To avoid access<br />
conflicts both MCMs must not be in <strong>the</strong> special operation mode at <strong>the</strong> same time.<br />
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