80960KA EMBEDDED 32-BIT MICROPROCESSOR - Datasheet ...

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80960KAdebug instruction. In each case, the 80960KAexecutes the instruction first and then calls a tracehandling routine (usually part of a software debugmonitor). Further program execution is halted until theroutine completes, at which time execution resumesat the next instruction. The 80960KA’s tracingmechanisms, implemented completely in hardware,greatly simplify the task of software test and debug.1.1.10. Fault DetectionThe 80960KA has an automatic mechanism to handlefaults. Fault types include trace and arithmetic faults.When the processor detects a fault, it automaticallycalls the appropriate fault handling routine and savesthe current instruction pointer and necessary stateinformation to make efficient recovery possible. Likeinterrupt handling routines, fault handling routines areusually written to meet the needs of specific applicationsand are often included as part of the operatingsystem or kernel.For each of the fault types, there are numeroussubtypes that provide specific information about afault. The fault handler can use this specific informationto respond correctly to the fault.1.1.11. Built-in TestabilityUpon reset, the 80960KA automatically conducts anexhaustive internal test of its major blocks of logic.Then, before executing its first instruction, it does azero check sum on the first eight words in memory toensure that the memory image was programmedcorrectly. If a problem is discovered at any pointduring the self-test, the 80960KA asserts its FAILUREpin and will not begin program execution. Self testtakes approximately 47,000 cycles to complete.System manufacturers can use the 80960KA’s selftestfeature during incoming parts inspection. Nospecial diagnostic programs need to be written. Thetest is both thorough and fast. The self-test capabilityhelps ensure that defective parts are discoveredbefore systems are shipped and, once in the field, theself-test makes it easier to distinguish betweenproblems caused by processor failure and problemsresulting from other causes.1.1.12. CHMOSThe 80960KA is fabricated using Intel’s CHMOS IV(Complementary High Speed Metal Oxide Semiconductor)process. The 80960KA is currently availablein 16, 20 and 25 MHz versions.7
80960KATable 3. 80960KA Pin Description: L-Bus Signals (Sheet 1 of 2)NAME TYPE DESCRIPTIONCLK2 I SYSTEM CLOCK provides the fundamental timing for 80960KA systems. It is dividedby two inside the 80960KA to generate the internal processor clock.LAD31:0ALEADSW/RDT/RI/OT.S.OT.S.OO.D.OO.D.OO.D.LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to andfrom memory. During an address (T a ) cycle, bits 2-31 contain a physical wordaddress (bits 0-1 indicate SIZE; see below). During a data (T d ) cycle, bits 0-31contain read or write data. These pins float to a high impedance state when notactive.Bits 0-1 comprise SIZE during a T a cycle. SIZE specifies burst transfer size in words.LAD1 LAD00 0 1 Word0 1 2 Words1 0 3 Words1 1 4 WordsADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE isasserted during a T a cycle and deasserted before the beginning of the T d state. It isactive LOW and floats to a high impedance state during a hold cycle (T h ).ADDRESS/DATA STATUS indicates an address state. ADS is asserted every T astate and deasserted during the following T d state. For a burst transaction, ADS isasserted again every T d state where READY was asserted in the previous cycle.WRITE/READ specifies, during a T a cycle, whether the operation is a write or read. Itis latched on-chip and remains valid during T d cycles.DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from theL-Bus. It is low during T a and T d cycles for a read or interrupt acknowledgment; it ishigh during T a and T d cycles for a write. DT/R never changes state when DEN isasserted.READY I READY indicates that data on LAD lines can be sampled or removed. If READY is notasserted during a T d cycle, the T d cycle is extended to the next cycle by inserting await state (T w ) and ADS is not asserted in the next cycle.LOCKI/OO.D.BUS LOCK prevents bus masters from gaining control of the L-Bus duringRead/Modify/Write (RMW) cycles. The processor or any bus agent may assertLOCK.At the start of a RMW operation, the processor examines the LOCK pin. If the pin isalready asserted, the processor waits until it is not asserted. If the pin is not asserted,the processor asserts LOCK during the T a cycle of the read transaction. Theprocessor deasserts LOCK in the T a cycle of the write transaction. During the timeLOCK is asserted, a bus agent can perform a normal read or write but not a RMWoperation.The processor also asserts LOCK during interrupt-acknowledge transactions.Do not leave LOCK unconnected. It must be pulled high for the processor to functionproperly.I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state8
Page 3 and 4: CONTENTSFigure 24.Figure 25.Figure
Page 6 and 7: 80960KATable 1. 80960KA Instruction
Page 8 and 9: 80960KApurpose registers provided i
Page 12 and 13: 80960KABE3:0OO.D.BYTE ENABLE LINES
Page 14 and 15: 80960KA2.3. Connection Recommendati
Page 16 and 17: 80960KATEMP = +22°C@5.5V@5.0V@4.5V
Page 18 and 19: 80960KA2.6. Absolute Maximum Rating
Page 20 and 21: 80960KA2.8.1. AC Specification Tabl
Page 22 and 23: 80960KA1. Clock rise and fall times
Page 24 and 25: 80960KA3.0 MECHANICAL DATA3.1. Pack
Page 26 and 27: 80960KA14 13 12 11 10 9 8 7 6 5 4 3
Page 28 and 29: 80960KA3.2. PinoutTable 9. 80960KA
Page 30 and 31: 80960KATable 11. 80960KA PQFP Pinou
Page 32 and 33: 80960KA3.3. Package Thermal Specifi
Page 34 and 35: 80960KATEMPERATURE ( o C)9085807570
Page 36 and 37: 80960KA4.0 WAVEFORMSFigures 27, 28,
Page 38 and 39: 80960KAT a T w T w T d T w T d T w
Page 40 and 41: 80960KAPREVIOUSCYCLEINTERRUPTACKNOW
Page 42 and 43: 80960KA39

80960KA EMBEDDED 32-BIT MICROPROCESSOR - Datasheet ...

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