Dual-Core Intel® Xeon® Processor 5200 Series

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Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 2 Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications 2.1 Front Side Bus and GTLREF Most Dual-Core Intel® Xeon® Processor 5200 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during the first clock of a low-to-high voltage transition. Platforms implement a termination voltage level for AGTL+ signals defined as V TT. Because platforms implement separate power planes for each processor (and chipset), separate V CC and V TT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families. Design guidelines for the processor FSB are detailed in the appropriate platform design guidelines (refer to Section 1.3). The AGTL+ inputs require reference voltages (GTLREF_DATA and GTLREF_ADD) which are used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF_DATA is used for the 4X front side bus signaling group and GTLREF_ADD is used for the 2X and common clock front side bus signaling groups. Both GTLREF_DATA and GTLREF_ADD must be generated on the baseboard (See Table 2-18 for GTLREF_DATA and GTLREF_ADD specifications). Refer to the applicable platform design guidelines for details. Termination resistors (R TT ) for AGTL+ signals are provided on the processor silicon and are terminated to V TT. The on-die termination resistors are always enabled on the Dual-Core Intel® Xeon® Processor 5200 Series to control reflections on the transmission line. Intel chipsets also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals. Some FSB signals do not include on-die termination (R TT ) and must be terminated on the baseboard. See Table 2-8 for details regarding these signals. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB, including trace lengths, is highly recommended when designing a system. Contact your Intel Field Representative to obtain the Dual-Core Intel® Xeon® Processor 5200 Series signal integrity models, which includes buffer and package models. 2.2 Power and Ground Lands For clean on-chip processor core power distribution, the processor has 223 V CC (power) and 273 V SS (ground) inputs. All V CC lands must be connected to the processor power plane, while all V SS lands must be connected to the system ground plane. The processor V CC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. See Table 2-3 for VID definitions. 15
Page 1 and 2: Dual-Core Intel® Xeon® Processor
Page 3 and 4: Contents 1 Introduction............
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Signal Definitions 5 Signal Definit
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Thermal Specifications 6 Thermal Sp
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Thermal Specifications 6.3 Platform
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Dual-Core Intel® Xeon® Processor 5200 Series

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