Dual-Core Intel® Xeon® Processor 5200 Series

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Table 2-12. Voltage and Current Specifications (Sheet 1 of 2) 28 Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Symbol Parameter Min Typ Max Unit Notes 1, 11 VID VID range 0.850 1.3500 V VCC VCC for processor core Launch - FMB See Table 2-13 and Figure 2-5, Figure 2-6, and Figure 2-6, V 2, 3, 4, 6, 9 V cc_boot V VID_STEP V VID_SHIFT V TT V CCPLL I CC I CC I CC I CC I CC_RESET I CC_RESET I CC_RESET I CC_RESET I TT Default VCC Voltage for initial power up VID step size during a transition Total allowable DC load line shift from VID steps FSB termination voltage (DC + AC specification) PLL supply voltage (DC + AC specification) I CC for Dual-Core Intel® Xeon® Processor X5200 Series with multiple VID Launch - FMB I CC for Dual-Core Intel® Xeon® Processor E5200 Series with multiple VID Launch - FMB I CC for Dual-Core Intel® Xeon® Processor L5200 Series with multiple VID Launch - FMB I CC for Dual-Core Intel® Xeon® Processor L5238 with multiple VID Launch - FMB I CC_RESET for Dual-Core Intel® Xeon® Processor X5200 Series with multiple VID Launch - FMB I CC_RESET for Dual-Core Intel® Xeon® Processor E5200 Series with multiple VID Launch - FMB I CC_RESET for Dual-Core Intel® Xeon® Processor L5200 Series with multiple VID Launch - FMB I CC_RESET for Dual-Core Intel® Xeon® Processor L5238 with multiple VID Launch - FMB I CC for V TT supply before V CC stable I CC for V TT supply after V CC stable 1.10 V 2 ± 12.5 mV 450 mV 10 1.045 1.10 1.155 V 8,13 1.455 1.500 1.605 V 12 90 A 4, 5, 6, 9 75 A 4, 5, 6, 9 50 A 4, 5, 6, 9 42 A 4, 5, 6, 9 90 A 17 75 A 17 50 A 17 42 A 17 4.5 4.6 A 15
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications Table 2-12. Voltage and Current Specifications (Sheet 2 of 2) I CC_TDC I CC_TDC I CC_TDC I CC_TDC I CC_VTT_OUT I CC_GTLREF Thermal Design Current (TDC) Dual-Core Intel® Xeon® Processor X5200 Series Launch - FMB Thermal Design Current (TDC) Dual-Core Intel® Xeon® Processor E5200 Series Launch - FMB Thermal Design Current (TDC) Dual-Core Intel® Xeon® Processor L5200 Series Launch - FMB Thermal Design Current (TDC) Dual-Core Intel® Xeon® Processor L5238 Launch - FMB DC current that may be drawn from V TT_OUT per land I CC for GTLREF_DATA and GTLREF_ADD 70 A 6,14 60 A 6,14 38 A 6,14 35 A 6,14 580 mA 16 200 µA 7 ICC_VCCPLL ICC for PLL supply 130 mA 12 ITCC ICC for Dual-Core Intel® Xeon® Processor X5200 Series during active thermal control circuit (TCC) 90 A I TCC I TCC I TCC Symbol Parameter Min Typ Max Unit Notes 1, 11 I CC for Dual-Core Intel® Xeon® Processor E5200 Series during active thermal control circuit (TCC) I CC for Dual-Core Intel® Xeon® Processor L5200 Series during active thermal control circuit (TCC) I CC for Dual-Core Intel® Xeon® Processor L5238 during active thermal control circuit (TCC) 75 A 50 A 42 A Notes: 1. Unless otherwise noted, all specifications in this table are based on final silicon characterization data. 2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.5 for more information. 3. The voltage specification requirements are measured across the VCC_DIE_SENSE and VSS_DIE_SENSE lands and across the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands with an oscilloscope set to 100 MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 4. The processor must not be subjected to any static V CC level that exceeds the V CC_MAX associated with any particular current. Failure to adhere to this specification can shorten processor lifetime. 5. I CC_MAX specification is based on maximum V CC loadline. Refer to Figure 2-5, Figure 2-6, and Figure 2-11 for details. The processor is capable of drawing I CC_MAX for up to 10 ms. Refer to Figure 2-1 for further details on the average processor current draw over various time durations. 6. FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See Section 2.13.1 for further details on FMB guidelines. 7. This specification represents the total current for GTLREF_DATA and GTLREF_ADD. 8. V TT must be provided via a separate voltage source and must not be connected to V CC . This specification is measured at the land. 9. Minimum V CC and maximum I CC are specified at the maximum processor case temperature (TCASE) shown in Figure 6-1 and Figure 6-2. 29
Page 1 and 2: Dual-Core Intel® Xeon® Processor
Page 3 and 4: Contents 1 Introduction............
Page 5 and 6: Figures 2-1 Input Device Hysteresis
Page 7 and 8: Revision History Revision Descripti
Page 9 and 10: 1 Introduction The Dual-Core Intel
Page 11 and 12: Commonly used terms are explained h
Page 13 and 14: communicates readings from the proc
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Page 39 and 40: Mechanical Specifications 3 Mechani
Page 41 and 42: Mechanical Specifications Figure 3-
Page 43 and 44: Mechanical Specifications 3.2 Proce
Page 45 and 46: Mechanical Specifications Figure 3-
Page 47 and 48: Land Listing 4 Land Listing 4.1 Dua
Page 49 and 50: Land Listing Table 4-1. Land Listin
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Thermal Specifications Figure 6-2.
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Thermal Specifications Table 6-9. D
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Thermal Specifications service any
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Thermal Specifications 6.3 Platform
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Thermal Specifications 6.3.2.3 PECI
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Features 7 Features 7.1 Power-On Co
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Features Table 7-2. Extended HALT M
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Features 7.2.4.2 Extended HALT Snoo
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Boxed Processor Specifications 8 Bo
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Boxed Processor Specifications Figu
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Boxed Processor Specifications 8.2.
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Debug Tools Specifications 9 Debug
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Dual-Core Intel® Xeon® Processor 5200 Series

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