Dual-Core Intel® Xeon® Processor 5200 Series

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Table 2-2. BSEL[2:0] Frequency Table 2.4.2 PLL Power Supply 18 Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications BSEL2 BSEL1 BSEL0 Bus Clock Frequency 0 0 0 266.66 MHz 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 333.33 MHz 1 0 1 Reserved 1 1 0 400 MHz 1 1 1 Reserved An on-die PLL filter solution is implemented on the Dual-Core Intel® Xeon® Processor 5200 Series. The V CCPLL input is used for this configuration in Dual-Core Intel® Xeon® Processor 5200 Series-based platforms. Please refer to Table 2-12 for DC specifications. Refer to the appropriate platform design guidelines for decoupling and routing guidelines. 2.5 Voltage Identification (VID) The Voltage Identification (VID) specification for the Dual-Core Intel® Xeon® Processor 5200 Series is defined by the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins. VID signals are open drain outputs, which must be pulled up to V TT. Please refer to Table 2-15 for the DC specifications for these signals. A voltage range is provided in Table 2-12 and changes with frequency. The specifications have been set such that one voltage regulator can operate with all supported frequencies. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings. This is reflected by the VID range values provided in Table 2-3. The Dual-Core Intel® Xeon® Processor 5200 Series uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages. Table 2-3 specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself. See the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details. Although the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines defines VID[7:0], VID7 and VID0 are not used on the Dual-Core Intel® Xeon® Processor 5200 Series; VID7 is always hard wired low at the voltage regulator.
Dual-Core Intel® Xeon® Processor 5200 Series Electrical Specifications The Dual-Core Intel® Xeon® Processor 5200 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V CC ). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 2-12 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 2-13 The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 2-12 and Table 2-13. Refer to the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design Guidelines for further details. Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable. 19
Page 1 and 2: Dual-Core Intel® Xeon® Processor
Page 3 and 4: Contents 1 Introduction............
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Thermal Specifications 6.3 Platform
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Thermal Specifications 6.3.2.3 PECI
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Features 7 Features 7.1 Power-On Co
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Dual-Core Intel® Xeon® Processor 5200 Series

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