130x1g2 - CCSDS

TM SYNCHRONIZATION AND CHANNEL CODING—SUMMARY OF CONCEPT AND RATIONALECONTENTS (continued)FigurePage7-3 CCSDS Turbo Encoder Block Diagram ....................................................................... 7-37-4 Structure of the Turbo Decoder .................................................................................... 7-57-5 Basic Circuits to Implement the Log-APP Algorithm .................................................. 7-67-6 BER and FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codes withBlock Size 1784 Bits, Measured from JPL DSN Turbo Decoder, 10 Iterations .......... 7-87-7 BER and FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codeswith Block Size 3568 Bits, Software Simulation, 10 Iterations ................................... 7-87-8 BER and FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codeswith Block Size 7136 bits, Software Simulation, 10 Iterations6 .................................. 7-97-9 BER and FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codes withBlock Size 8920 Bits, Measured from JPL DSN Turbo Decoder, 10 Iterations .......... 7-97-10 BER and FER Performance for Rate 1/2, 1/4, 1/3 and 1/6 Turbo Codes,Block Size 16384 Bits, Software Simulation, 10 Iterations ....................................... 7-107-11 Illustration of Decoder Speedup Using Stopping Rules ............................................. 7-107-12 BER Performance of Turbo Codes Compared to Older CCSDS Codes(Except Cassini/Pathfinder Code: Reed-Solomon (255,223) + (15,1/6)Convolutional Code), Block Size 1784 Bits (Interleaving Depth = 1),Software Simulation, 10 Iterations ............................................................................. 7-127-13 BER Performance of Turbo Codes Compared to Older CCSDS Codes(Except Cassini/Pathfinder Code: Reed-Solomon (255,223) + (15,1/6)Convolutional Code), Block Size 8920 Bits (Interleaving Depth = 5),Software Simulation, 10 Iterations ............................................................................. 7-137-14 Illustration of Turbo Code Error Floor ....................................................................... 7-148-1 Power Efficiency versus Spectral Efficiency for Several CCSDS Codes .................... 8-38-2 Power Efficiency versus Spectral Efficiency for Higher Order Modulations .............. 8-48-3 Parity Check Matric for Code C2 ................................................................................. 8-48-4 Protographs for the AR4JA Code Family ..................................................................... 8-58-5 Parity Check Matrix for the (n=1280, k=1024) AR4JA Code ...................................... 8-68-6 One Encoder for Block-Circulant LDPC Codes ........................................................... 8-78-7 Another Encoder for Block-Circulant LDPC Codes .................................................... 8-78-8 Bit Error Rate (Solid) and Frame Error Rate (Dashed) for Nine AR4JACodes and C2, with Code Rates 1/2 (Red), 2/3 (Green), 4/5 (Blue), and7/8 (Black); and Block Lengths k=16384, 4096, 1024 (Left to Right in EachGroup), and 7156 (Code C2). ..................................................................................... 8-109-1 Block Diagram of the Recommended Pseudo-Randomizer ......................................... 9-39-2 Turbo Codeword with Attached Sync Marker .............................................................. 9-99-3 A State-Diagram Based Frame Synchronizer ............................................................. 9-119-4 An Argmax Frame Synchronizer ................................................................................ 9-129-5 Performance of Several Frame Synchronizers, Compared with TwoRate-1/2 LDPC Codes ................................................................................................ 9-149-6 CRC Encoding Principle ............................................................................................. 9-16CCSDS 130.1-G-2 Page ix November 2012