130x1g2 - CCSDS

TM SYNCHRONIZATION AND CHANNEL CODING—SUMMARY OF CONCEPT AND RATIONALESoftware decoders must typically perform the computations for each variable node and checknode serially. Hardware decoders usually contain several variable node and check nodeprocessing units, but not enough for the entire code graph, so the nodes are partitioned intosets that are updated simultaneously. While details depend strongly on the hardwareresources available, three techniques for the recommended block-circulant codes deservemention. A ‘universal decoder’ contains general-purpose variable node and check node unitsand performs computations based on a programmed description of the code and updateschedule. A ‘protograph decoder’ contains variable and check node units wired together intoone (or more) copies of the protograph. It updates all the nodes in a protographsimultaneously and proceeds serially through the copies of the protograph. A ‘SIMDdecoder’ uses the Single-Instruction Multiple-Data concept and contains all the copies of oneprotograph node in hardware. This decoder updates all the copies of one nodesimultaneously and proceeds sequentially through the other protograph nodes.Decoders also vary in the number of decoding iterations performed. Conceptually, it issimplest to perform some fixed number of iterations for every codeword, where the numberrequired is larger for lower code rates, longer block lengths, and lower SNR. The averageamount of computation can be dramatically reduced with a stopping rule that halts thedecoder when it has converged to a solution. The most common stopping rule uses tentativehard decisions from the variable nodes and halts decoding either when all the constraintequations are satisfied or when some fixed maximum number of iterations is reached. Undertypical operating conditions, a very few codewords fail to decode after the maximum numberof iterations allowed, and most decode in a small fraction of this maximum. By stopping ahardware decoder early, power can be saved; if the decoder can proceed and decode the nextcodeword, its average throughput can be increased.An iterative decoder with a stopping rule takes a variable amount of time to decode a noisycodeword. If this is problematic for either the preceding or following signal processingstages, memory buffers may be inserted before or after the decoder. Buffers large enough tostore just a few codewords are sufficient to increase a decoder’s throughput from its worstcasecapability to nearly its average capability, and this is typically several times faster.Further details are in reference [52].8.6 PERFORMANCE OF THE RECOMMENDED LDPC CODESPerformance does not only depend on the code, but also on the decoder for the code. Manydesign choices must be made when implementing a practical belief-propagation decoder, andone cannot expect independent implementations to perform identically. However, experienceshows that, in the ‘waterfall’ region, good implementations perform within 0.1 dB of thecurves shown here. The ‘error floor’ region is subject to much greater variability, oftenchanging in error rate by an order of magnitude or more. Consistent design of good decodersin this region remains an open research question.Performance curves were determined by simulation on a Field Programmable Gate Array(FPGA) at JPL, and the results are shown in figure 8-8 (reference [51]). The dashed curvesshow FER, and the solid curves show BER. While FER is the more useful metric for packet-CCSDS 130.1-G-2 Page 8-9 November 2012