130x1g2 - CCSDS

TM SYNCHRONIZATION AND CHANNEL CODING—SUMMARY OF CONCEPT AND RATIONALEA diagram of an encoder for the recommended convolutional code of rate 1/2 and K=7 isshown in figure 4-1. The particular encoder structure depends on the manner in which theadders are connected to the shift register. These connections are denoted by a set of vectorsg i = (g i,1 , g i,2 , … , g i,m ) i = 1, 2, … , n (1)where g il = 1 denotes a connection between the ith stage of the shift register and the lth adder,and g il = 0 denotes the absence of a connection. The complete set of the g i s defines the code.INPUTDDDDG 2G 1DDC 1C 212S1OUTPUTNOTES:1.D= SINGLE BIT DELAY.2.3.4.FOR EVERY INPUT BIT, TWOSYMBOLS ARE GENERATED BYCOMPLETION OF A CYCLE FORS1: POSITION 1, POSITION 2.S1 IS IN THE POSITIONSHOWN (1) FOR THE FIRSTSYMBOL ASSOCIATED WITH ANINCOMING BIT.= MODULO-2 ADDER.5.= INVERTER.Figure 4-1: Example of Convolutional Encoder: Constraint Length K=7, Rate 1/2,CCSDS Standard Convolutional CodeThe encoder for the CCSDS standard code is extremely simple, as shown in figure 4-1. Itconsists of a shift register and some exclusive OR gates that implement the two parity checks.The two checks are then multiplexed into one line. This means that the encoder can be madesmall and that it dissipates very little power. These are good attributes for spacecraft hardware.CCSDS 130.1-G-2 Page 4-2 November 2012