130x1g2 - CCSDS

TM SYNCHRONIZATION AND CHANNEL CODING—SUMMARY OF CONCEPT AND RATIONALEFigure 8-6: One Encoder for Block-Circulant LDPC CodesOne natural implementation is shown in figure 8-6 (reference [49]). First, the n-k digits fromthe first row of the generator matrix are placed in the top row of the boxes in the figure, withm digits in each of the (n-k)/m cyclic shift registers. The first message bit is multiplied bythis vector, and the result is placed in an accumulator. Then the shift registers are cycled oneposition to construct the second row of the generator matrix; the result is multiplied by thenext message bit and added to the accumulator. This is repeated m times to complete the firstrow of circulants in the generator matrix. Then the first row from the next set of circulants isloaded into the cyclic shift registers, and the process is repeated until all k message bits areencoded. The k message bits, concatenated with the n-k symbols in the accumulator, give theoutput codeword. This implementation requires 2(n-k) memory cells and k(n-k) binarymultiply-accumulate operations.Figure 8-7: Another Encoder for Block-Circulant LDPC CodesThis implementation can be simplified as shown in figure 8-7 (reference [50]). Rather thancyclically shifting the memory cells holding the generator matrix patterns, the cyclic shiftCCSDS 130.1-G-2 Page 8-7 November 2012