130x1g2 - CCSDS

TM SYNCHRONIZATION AND CHANNEL CODING—SUMMARY OF CONCEPT AND RATIONALES 15S 14S 13S 12S 11S 10S 9S 8S 7S 6S 5S 4S 3S 2S 1S 0X 0 X 1 X 2 X 3 X 4 X 5 X 6 X 7 X 8 X 9 X 10 X 11 X 12 X 13 X 14 X 15FRAME BITS C 0* C n-1*(C 0* transferred first)Figure 9-8: Logic Diagram of the DecoderThe initial value of the shift register storage cells has in principle no effect on the CRCundetected error probability. However, there might be practical considerations leading to usean initial word instead of another one. For example, any CRC encoder where all the shiftregister storage cells are initialized to ‘0’ has no state transition if an all-‘zero’ message isinput. In some situations a non-‘zero’ initial word may be preferred. A non-‘zero’ initialword is recommended in reference [2], where the encoding and syndrome computation rulesare slightly different from (1) and (2). A degree-15 presetting polynomial150L(X) = ∑ i =iX (4)is first introduced, corresponding to the all-one sequence of length 16. Then, the FECF(encoding side) and the syndrome (decoding side) are computed asandFECF = [(X 16 ⋅ M(X)) + (X (n–16) ⋅ L(X))] mod G(X) (5)S(X) = [(X 16 ⋅ C * (X)) + (X n ⋅ L(X))] mod G(X) (6)respectively. It is possible to show that (5) and (6) correspond to input M(X) and C * (X) tothe encoding and decoding circuits, respectively, presetting in both circuits all the storagecells to ‘1’ (a proof can be found, for instance, in reference [58]).Serial concatenation of CRC encoding (FECF addition) and Turbo encoding is shown infigure 9-9.Transfer Framew/o FECFCRCencoderTransfer FrameturboencoderEncodedTransfer FrameFigure 9-9: Turbo-CRC EncoderCCSDS 130.1-G-2 Page 9-19 November 2012