Arria II GX Devices Family Overview

Chapter 1: Arria II GX Device Family Overview 1–5Arria II GX Device ArchitectureHigh-Speed Transceiver FeaturesArria II GX devices integrate up to 16 transceivers on a single device. The transceiverblock is optimized for cost and power consumption. Arria II GX transceivers supportthe following features:■■■■Configurable pre-emphasis and equalization, and adjustable output differentialvoltageFlexible and easy-to-configure transceiver datapath to implement proprietaryprotocolsSignal integrity features■■■■Programmable transmitter pre-emphasis to compensate for inter-symbolinterference (ISI)User-controlled five-stage receiver equalization with up to 7 dB ofhigh-frequency gainOn-die power supply regulators for transmitter and receiver PLL charge pumpand voltage-controlled oscillator (VCO) for superior noise immunityCalibration circuitry for transmitter and receiver on-chip termination (OCT)resistorsDiagnostic features■■■■■Serial loopback from the transmitter serializer to the receiver CDR fortransceiver physical coding sublayer (PCS) and physical media attachment(PMA) diagnosticsParallel loopback from the transmitter PCS to the receiver PCS with built-in selftest (BIST) pattern generator and verifierReverse serial loopback pre- and post-CDR to transmitter buffer for physicallink diagnosticsLoopback master and slave capability in PCIe hard IP blocksSupport for protocol features such as MSB-to-LSB transmission in aSONET/SDH configuration and spread-spectrum clocking in a PCIeconfiguration© July 2010 Altera Corporation Arria II GX Device Handbook, Volume 1